CN102484108A - 高带宽倾斜叠层芯片封装 - Google Patents

高带宽倾斜叠层芯片封装 Download PDF

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Publication number
CN102484108A
CN102484108A CN2010800328618A CN201080032861A CN102484108A CN 102484108 A CN102484108 A CN 102484108A CN 2010800328618 A CN2010800328618 A CN 2010800328618A CN 201080032861 A CN201080032861 A CN 201080032861A CN 102484108 A CN102484108 A CN 102484108A
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semiconductor die
chip packaging
tilt component
vertical
described chip
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CN2010800328618A
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CN102484108B (zh
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R·J·德罗斯特
J·G·米切尔
D·C·道格拉斯
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Oracle America Inc
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Oracle America Inc
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Abstract

说明了一种芯片封装。所述芯片封装包括相互偏移，从而限定出带有露出的焊盘的梯台的半导体裸片或芯片的叠层。近似平行于所述梯台布置的高带宽倾斜组件与露出的焊盘电耦合。例如，倾斜组件可以利用微弹簧，各向异性膜和/或焊料与半导体裸片电耦合。从而，电触点可具有传导阻抗、电容阻抗，或者通常具有复阻抗。此外，可以利用球坑对准技术，相对于彼此布置芯片和/或倾斜组件。通过消除对半导体裸片中的成本高并且占用面积的硅穿孔(TSV)的需要，芯片封装可有利于按照提供高带宽和低成本的方式堆叠芯片。

Description

高带宽倾斜叠层芯片封装
技术领域
本公开一般性涉及半导体芯片封装。更具体地说，本公开涉及包括排列成叠层的一组芯片，和相对于所述叠层成一定角度，并与所述芯片耦合的倾斜组件的芯片封装。
背景技术
与连接到印刷电路板的常规的单独封装芯片相比，包括堆叠的半导体芯片的芯片封装能够带来更高的性能和较低的成本。这些芯片封装还带来一些优点，比如对叠层中的不同芯片使用不同的处理，组合更高密度的逻辑器件和存储器，和利用较低功率传送数据的能力。例如，实现动态随机存取存储器(DRAM)的芯片叠层能够在基底芯片中使用高金属层数、高性能逻辑工艺来实现输入/输出(I/O)和控制器功能，并且一组低金属层数、DRAM专用加工芯片可用于叠层的剩余部分。这样，与包括利用DRAM工艺制造的I/O和控制器功能的单芯片；包括利用逻辑工艺制造的存储电路的单芯片、和/或利用单一工艺产生逻辑和存储器物理结构的尝试相比，组合的一组芯片具有更好的性能和更低的成本。
堆叠芯片的现有技术包括引线接合法和硅穿孔(TSV)。引线接合法是一种低带宽、低成本技术，其中相互偏移地堆叠芯片，以形成包括露出的接合焊盘的阶梯芯片边缘。通过把导线接合到这些接合焊盘，实现与芯片的电连接。
相反，TSV一般具有比引线接合法高的带宽。在TSV制备技术中，芯片被加工，以致在其活性面上的其金属层中的一个或多个金属层导电地连接到在其背面的新焊盘。随后，芯片被胶粘地连接成叠层，以致在一个芯片的背面的新焊盘与相邻芯片的活性面上的对应焊盘导电地接触。
不过，TSV的成本一般高于引线接合。这是因为TSV穿过芯片的活性硅层。结果，TSV占据本来可用于晶体管或布线的面积。这种机会成本可能较大。例如，如果TSV排除或禁止布线直径为20微米，并且按30微米节距布置TSV，那么TSV消耗大约45％的硅面积。这约略使叠层中的芯片之中的任何电路的单位面积成本加倍(事实上，由于一般使电路散开以容纳TSV，而这浪费更多的面积，因此开销可能甚至更大)。另外，制备TSV一般需要额外的加工操作，这也增大了芯片成本。
从而，需要一种提供叠层芯片的优点，而无上述问题的芯片封装。
发明内容
本公开的一个实施例提供一种芯片封装，所述芯片封装包括在垂直方向排列成叠层的一组半导体裸片，所述垂直方向基本上与平行于垂直叠层中的第一半导体裸片的平面垂直。在所述垂直叠层中，在第一半导体裸片之后的给定半导体裸片在所述平面中的水平方向从垂直叠层中的前一个半导体裸片偏移一个偏移值，从而在垂直叠层的一侧限定出梯状平台。此外，芯片封装包括倾斜组件，所述倾斜组件与半导体裸片电耦合和机械耦合。所述倾斜组件位于垂直叠层的一侧，并且近似平行于沿着梯状平台的介于所述水平方向和所述垂直方向之间的方向。
注意，倾斜组件可以是无源组件，比如具有与半导体裸片电耦合的金属迹线的塑料衬底。或者，倾斜组件可以是另一个半导体裸片。此外，倾斜组件可包括被配置成可重新配合地与电路板电耦合和机械耦合的边缘连接器。
在一些实施例中，芯片封装包括在第一半导体裸片之下的衬底，所述衬底近似平行于所述平面，其中所述衬底至少与倾斜组件电耦合。
此外，在一些实施例中，芯片封装包括环绕半导体裸片和倾斜组件的至少一部分的封包。
另外，倾斜组件可被焊接到每个半导体裸片。为了便于把倾斜组件焊接到半导体裸片，半导体裸片可包括凸块。为了容纳垂直方向的机械对准误差，在所述垂直方向，凸块的高度和节距在半导体裸片之间可变化。
在一些实施例中，倾斜组件借助微弹簧和/或各向异性导电膜与每个半导体裸片电耦合。为了便于半导体裸片和倾斜组件之间的电耦合，半导体裸片可包括在半导体裸片顶面上的压缩元件，当装配芯片封装时，所述压缩元件压缩各向异性导电膜。
注意，可在不把半导体裸片插入倾斜组件中的槽的情况下，使倾斜组件与半导体裸片机械耦接。在一些实施例中，在无半导体裸片中的芯片穿孔的情况下，倾斜组件有利于将电信号和功率信号传递到半导体裸片。
此外，倾斜组件可包括用于半导体裸片的机械挡块，所述机械挡块有利于芯片封装的装配。
另外，倾斜组件和半导体裸片中的给定半导体裸片之间的电耦合可具有复阻抗，所述复阻抗包括同相分量和异相分量。
在一些实施例中，芯片封装包括垂直叠层中的至少两个半导体裸片之间的中间芯片。所述中间芯片可沿着水平方向，传送因半导体裸片至少之一的工作而产生的热量。
在一些实施例中，半导体裸片的表面包括蚀坑，并且蚀坑中的球保持垂直叠层中的半导体裸片的相对对准。
另一个实施例提供一种包括所述芯片封装的计算机系统。
另一个实施例提供一种包括所述芯片封装的电子器件。
附图说明
图1A是图解说明按照本公开的一个实施例的芯片封装的框图。
图1B是图解说明按照本公开的一个实施例的芯片封装的框图。
图2A是图解说明按照本公开的一个实施例的芯片封装的框图。
图2B是图解说明按照本公开的一个实施例的芯片封装的框图。
图3A是图解说明按照本公开的一个实施例的芯片封装的框图。
图3B是图解说明按照本公开的一个实施例的芯片封装的框图。
图3C是图解说明按照本公开的一个实施例的芯片封装的框图。
图3D是图解说明按照本公开的一个实施例的芯片封装的框图。
图4A是图解说明按照本公开的一个实施例的芯片封装的框图。
图4B是图解说明按照本公开的一个实施例的芯片封装的框图。
图5是图解说明按照本公开的一个实施例的芯片封装的框图。
图6是图解说明按照本公开的一个实施例的包括一个或多个芯片封装的电子器件的框图。
图7是图解说明按照本公开的一个实施例的包括一个或多个芯片封装的计算机系统的框图。
注意在附图中，相同的附图标记表示对应的部分。此外，相同部分的多个实例用借助虚线，与实例编号隔开的公共前缀表示。
具体实施方式
提供下述说明是为了使本领域的技术人员能够实现和使用本发明，下述说明是在特定的应用及其要求的上下文下进行的。对本领域的技术人员来说，对所公开实施例的各种修改是显而易见的，这里定义的一般原理可适用于其它实施例和应用，而不脱离本发明的精神和范围。从而，本发明并不局限于所示的实施例，相反应被赋予与这里公开的原理和特征一致的最宽广的范围。
说明了芯片封装、包括所述芯片封装的电子器件，和包括所述芯片封装的计算机系统的实施例。所述芯片封装包括相互偏移从而限定出带有露出的焊盘的梯台的半导体裸片或芯片的叠层。近似平行于所述梯台布置的高带宽倾斜组件与露出的焊盘电耦合。例如，倾斜组件可以利用微弹簧、各向异性膜和/或焊料与半导体裸片电耦合。从而，电触点可具有传导阻抗，电容阻抗，或者通常具有复阻抗。此外，可以利用球坑对准(ball-and-pit alignment)技术，相对于彼此布置芯片和/或倾斜组件。
通过消除对半导体裸片中的成本高并且占用面积的硅穿孔(TSV)的需要，芯片封装可有利于按照提供高带宽和低成本的方式堆叠芯片。例如，通过避免与半导体裸片中的TSV相关的加工操作和浪费的面积，可降低成本。因此，叠层中的芯片可使用标准加工工艺制造。此外，与引线接合相比，微弹簧和/或各向异性膜可具有较低成本，和/或可提供提高的可靠性。注意在芯片和倾斜组件之间的机械和/或电耦合是可重新配合的实施例中，通过允许返工(比如替换在装配或老化测试期间识别的坏芯片)，可以提高芯片封装的成品率。
另外，所述芯片封装可提供比引线接合更高的组件间通信带宽。虽然TSV原则上提供更高的带宽，不过这一般需要消耗半导体裸片中相当高百分比的硅面积。相对于浪费较少硅面积的数目适中的TSV，倾斜组件可提供相当的组件间通信带宽。
现在说明芯片封装的实施例。图1A是图解说明芯片封装100的侧视图的框图，芯片封装100包括沿着垂直方向120排列成叠层116的一组芯片或半导体裸片110，垂直方向120基本上垂直于与半导体裸片110-1平行的平面。在所述垂直叠层中，使半导体裸片110-1之后的每个半导体裸片(比如半导体裸片110-2)沿着所述平面中的水平方向118从垂直叠层116中的前一个半导体裸片至少偏移最小偏移值126，从而在垂直叠层116的一侧限定出梯状平台128(具有定角124)。此外，芯片封装100包括倾斜组件112，倾斜组件112与半导体裸片110电耦合和机械耦合。所述倾斜组件被置于垂直叠层116的一侧上，并且近似平行于沿着梯状平台128的方向122，方向122介于水平方向118和垂直方向120之间。
在一些实施例中，半导体裸片110是利用标准硅加工工艺制备的。特别地，在这些实施例中，半导体裸片110不包括TSV。这些半导体裸片可提供支持逻辑和/或存储器功能的硅面积。
此外，半导体裸片110可以借助倾斜组件112相互通信，和与外部器件或系统通信。特别地，如图1A中图解所示，倾斜组件112可以借助微弹簧114，与每个半导体裸片110电耦合。注意可在各种表面上制备微弹簧114，包括：印刷电路板(PCB)，有机或陶瓷集成电路(IC)，和/或半导体裸片的表面。此外，可以按超过高性能IC上的输入/输出(I/O)信号的密度的芯片间连接的面密度，制备微弹簧114，微弹簧114的柔量能够提高对芯片封装100中的组件的机械移动和失准的容差。
微弹簧114还能够提供机械接触和电接触，而不使用焊料。从而，倾斜组件112和半导体裸片110之间的机械和/或电耦合可以是可移除或者可重新配合的(即，可以重新配合地耦合这些组件)，这使装配和/或测试期间和/或之后的芯片封装100的返工更容易。注意可重新配合的机械或电耦合应被理解为可在不需要返工或加热(例如，借助焊料)的情况下，可反复(即，两次或更多次)建立和断开的机械或电耦合。在一些实施例中，可重新配合的机械或电耦合涉及被设计成相互耦合的阴阳组件(比如咬合在一起的组件)。从而，可重新配合的组件是被配置成允许建立可重新配合的耦合的组件。不过，如下参考图2B进一步所述，在一些实施例中，倾斜组件112和半导体裸片110之间的机械和/或电耦合更持久(例如，所述机械和/或电耦合可以不是可重新配合的，比如焊接触点)。
注意，倾斜组件112可以是无源组件，比如具有与半导体裸片110电耦合的金属迹线的塑料衬底。例如，倾斜组件112可以利用注射成型塑料制备。或者，倾斜组件112可以是具有通过光刻形成的引线或信号线的另一个半导体裸片。在倾斜组件112包括半导体裸片的实施例中，可以包括有源器件，比如限幅放大器，以降低信号线之间的串扰。另外，通过利用差分信令，在有源或无源倾斜组件112中，可以降低串扰。
在一些实施例中，倾斜组件112包括经由微弹簧114，在半导体裸片110之间来回传送数据信号和功率信号的晶体管和导线。例如，倾斜组件112可包括高压信号。通过利用降压稳压器(比如电容-电容降压稳压器)，以及电容器和/或电感器离散组件耦合半导体裸片110，这些信号可被降压，以便在半导体裸片110上使用。
在一些实施例中，芯片封装110包括在半导体芯片110-1之下的可选衬底130，可选衬底130近似平行于所述平面。可选衬底130至少与倾斜组件112电耦合(这可在不利用半导体裸片110中的TSV的情况下，有利于与半导体裸片110-1的电信号或功率信号的通信)，并且可以刚性地与半导体裸片110机械耦合。此外，可选衬底130可包括：存储器用缓冲器或逻辑芯片，和/或与外部器件和/或系统的输入/输出(I/O)。例如，所述I/O可包括一个或多个球接合或引线接合(如图1A中图解所示)。
注意可存在环绕至少一部分的芯片封装100的可选封包132-1。
图1B是图解说明具有4个半导体裸片110的芯片封装100的顶视图的框图。图1B表示可选衬底130可延伸到叠层116(图1A)之外，使得通过利用：引线接合、球接合，和/或近程通信(PxC)，可选衬底130的多达4个边缘可被访问以供通信之用。
通常，通过利用比如电容耦合信号的电磁耦合信号的PxC(称为“电磁近程通信”)，和/或光信号的近程通信(分别称为“电近程通信”和“光近程通信”)，半导体裸片110和倾斜组件112、倾斜组件112和可选衬底130、可选衬底130和外部器件或系统，和/或倾斜组件112和外部器件或系统可相互通信。在一些实施例中，电磁近程通信包括电感耦合信号和/或传导耦合信号。
于是，与微弹簧114和半导体裸片110之间的电触点相关的阻抗可以是传导(即，同相)阻抗和/或电容(即，异相)阻抗，比如当在半导体裸片110的表面上或者邻近所述表面的金属焊盘之上存在钝化层(例如，玻璃层)时。通常，该阻抗可以是包括同相分量和异相分量的复阻抗。与电触点机构(例如，微弹簧114，下面参考图2A说明的各向异性层，或者下面参考图2B说明的焊料)无关，如果与触点相关的阻抗是传导阻抗，那么在芯片封装100中的各个组件中可以使用常规的发送和接收I/O电路。不过，对于具有复(并且可能变化的)阻抗的触点来说，发送和接收I/O电路可包括在Robert J.Drost等于2009年4月17日提交的美国专利申请12/425871，“Receive Circuit forConnectors with Variable Complex Impedance”(代理人案卷号SUN09-0285)中说明的一个或多个实施例，该专利申请的内容包括在此引为参考。
注意在一些实施例中，在给定的半导体裸片上，可存在两个或更多个微弹簧114。例如，数据-信号微弹簧可较短而带有钝端，而功率-信号微弹簧可较长而带有更尖利的顶端。另外，通过包括冗余功率-信号微弹簧，即使一定数目的功率-信号微弹簧失去其连接，也能够提高成品率和长期可靠性。
为了增大触点的电容，在一些实施例中，可在触点区域添加传导液体、传导膏或传导膜，以填充任何间隙。就所述传导液体、传导膏或传导膜扩散到给定微弹簧的边缘之外来说，这还可获得增大重叠面积的有益效果。
虽然图1A和1B图解说明芯片封装100的特定结构，不过可以利用多种技术和结构来实现与倾斜组件112和/或可选衬底130的电接触、机械对准、装配和/或电气I/O。现在说明这些实施例中的一些实施例。
图2A是图解说明芯片封装200的框图，其中倾斜组件112通过各向异性膜210，比如各向异性弹性体膜(有时被称为“各向异性传导膜”)，与半导体裸片110电耦合。注意，各向异性膜210的各向异性性质增强各向异性膜210的表面的法线方向的导电率，同时还降低各向异性膜210的表面的切线方向的导电率。结果，各向异性膜210电耦合在各向异性膜210相反两面上的机械对准的焊盘。
例如，各向异性膜210可以包括
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材料(来自Massachusetts，Fall River的Paricon Technologies，Inc.)，以及许多取得专利权的各项异性膜，包括：美国专利5624268，“ElectricalConductors Using Anistropic Conductive Films”，和美国专利4778950，“Anisotropic Elastomeric Interconnecting System”。在PariPoser类各向异性传导弹性体膜中，小的导电球悬浮在硅橡胶中，使得所述球通常排列成列，从而沿着与各向异性膜的表面的法线(而不是切线)的方向导电。和微弹簧114(图1A)的情况一样，所产生的电触点的阻抗通常是传导性和/或电容性的。如果阻抗是传导性的，那么在芯片封装200的各个组件中，可以使用常规的发送和接收I/O电路。不过，如果阻抗是复阻抗，那么芯片封装200中的发送和接收I/O电路可包括在美国专利申请12/425871中说明的一个或多个实施例，
在一些实施例中，利用在半导体裸片110和/或倾斜组件112的顶面上的压缩元件(例如，压缩元件212-1和214-1)，有利于半导体裸片110和倾斜组件112之间借助各向异性膜210的电耦合，当装配芯片封装200时，所述压缩元件压缩各向异性膜210。
另一方面，如作为图解说明芯片封装250的框图的图2B中所示，利用焊料(例如，可回流的焊料层)，可实现倾斜组件112和半导体裸片110之间的电接触。例如，微弹簧260(或引线)可被焊接到在半导体裸片110表面上的凸块，比如凸块262-1。为了容纳垂直方向120(图1A)的机械对准误差，沿着垂直方向120(图1A)，在半导体裸片110之间，凸块焊盘的高度和节距可发生变化。在例证实施例中，在相对于半导体裸片110和/或可选衬底130机械定位倾斜组件112之后，加热芯片封装250，并且焊料回流，从而在微弹簧260与半导体裸片110和/或可选衬底130之间形成焊接连接点。
虽然在半导体裸片110中可不存在TSV，不过在一些实施例中，在可选衬底130中包括TSV。这示于图3A中，图3A是图解说明芯片封装300的框图。区域焊接接合312可用于电耦合可选衬底130和其它半导体裸片和/或PCB。通常，在关于可选衬底130的引线接合和TSV(借助区域焊接接合)之间，存在成本和性能方面的折衷。与叠层中的半导体裸片110相反，在可选衬底130中，可以更能容忍增加的成本，因为可选衬底130经常是每个芯片封装使用一次的更高价的芯片。另外可设想在相同的可选衬底130上，可以使用引线接合和TSV的组合。
此外，虽然图1A图解说明与可选衬底130的引线接合，不过在其它实施例中，可选衬底130包括连接器。这示于图3B中，图3B是图解说明具有在一端的连接器340，和在另一端的可选连接器342的芯片封装330的框图。这些连接器可包括配置成可重新配合地与PCB电耦合和机械耦合的边缘连接器。另一方面或者另外地，所述连接器可包括PxC连接器。
在一些实施例中，连接器340和/或可选连接器342包含在倾斜组件112的正面和/或背面上。这示于图3C中，图3C是图解说明芯片封装360的框图。
图3D中示出了另一种结构，图3D是图解说明芯片封装380的框图。在这种芯片封装中，基底芯片390借助在倾斜组件392的背面的一个或多个微弹簧(比如微弹簧394)与倾斜组件392耦合。这些微弹簧借助穿过倾斜组件392的一个或多个通孔(比如通孔396)与微弹簧114电耦合，从而与半导体裸片112电耦合。
如前所述，在芯片封装的实施例中，可以使用各种对准技术。一种对准技术涉及与蚀坑中的球相结合地使用蚀坑来保持叠层中的半导体裸片110的相对对准。这示于图4A中，图4A是图解说明包括球(比如球410-1)和相关的蚀坑(比如蚀坑412-1)的芯片封装400的框图。球坑对准技术可以在使表面咬合在一起的轻微压力下，以小于一微米的机械容差对准半导体裸片110和/或可选衬底130的表面。在施加所述压力之前，可以使用贴片机(pick-and-place machine)实现当把组件放置在一起时小于10微米的机械容差。利用一点额外的时间(以及因此产生的装配成本)，这些机器能够以小于1微米的机械容差对准各个组件。给定初始对准，随后能够粘着可选衬底130和半导体裸片110，从而在半导体裸片110之间形成空间上限定良好的梯台128。在这个例子中，使倾斜组件112对准可选衬底130，或者对准半导体裸片110至少之一就可足够了。
例如，最低限度的方案可以使用两个蚀坑以相对于可选衬底130和相对于一组半导体裸片110固定倾斜组件112的表面的x-y位置。施加于倾斜组件112和可选衬底130的背面的机械力于是会挤压倾斜组件112以使其与可选衬底130和半导体裸片110接触。不过，热变形和其它机械力可能会妨碍弱粘合技术提供牢固、长期的芯片封装技术。虽然可选衬底130和半导体裸片110的强而持久的粘合较牢固，不过可能会妨碍装配和测试期间和/或部署后的返工。通常，当在封装和装配之前，广泛面临较低的半导体裸片成品率或者较高的测试费用时，允许某些返工的封装技术成本效率更高。从而，避免强粘合的封装技术可能是有利的。
在芯片封装400中，使用球和蚀坑以对准倾斜组件112，以及可选衬底130和半导体裸片110。在这种方案中，各个组件都不需要持久粘合或弱粘合。除了球-蚀坑对准技术之外，可以结合或者代替球和蚀坑中的任何一个而使用有关的半球形凸起-蚀坑技术以对准各个组件。更一般地，机械锁定倾斜组件112、可选衬底130和/或半导体裸片110上的阴阳表面特征的任何组合可以无需粘合或与粘合相组合地对准组件。
注意，在一些实施例中，可以利用电子对准技术来校正芯片封装中的平面机械失准。例如，如果给定微弹簧接触发送或接收微焊盘或微条的阵列，那么电子对准可以和传导和/或电容触点一起使用。
在一些实施例中，倾斜组件112包括使芯片封装的装配更容易的特征。这示于图4B中，图4B是图解说明芯片封装450的框图，芯片封装450包括机械挡块，比如在半导体裸片110上的机械挡块460-1。例如，机械档块可利用聚酰亚胺制备。通过沿着水平方向118(图1A)把半导体裸片110推压向倾斜组件112，这些机械挡块可有利于半导体裸片110和倾斜组件112之间的良好机械接触。另外，机械挡块可降低对半导体裸片110的粗糙(并且可能不分明的)边缘的敏感度。在一些实施例中，在不把半导体裸片110插入倾斜组件112中的槽的情况下，倾斜组件112与半导体裸片110机械耦接。
在一些实施例中，芯片封装包括消除在一个或多个半导体裸片110、倾斜组件112和/或可选衬底130上的电路的工作期间产生的热量的特征。这示于图5中，图5是图解说明芯片封装500的框图。特别地，芯片封装500包括至少两个半导体裸片110之间的中间芯片或中间层510。所述中间芯片可沿着水平方向118(图1A)传递因半导体裸片至少之一的工作而产生的热量。此外，中间芯片510上的微射流可有利于热传递。注意，在一些实施例中，中间芯片510还可降低两个或更多个半导体裸片110之间的串扰。
在一个例证实施例中，叠层116(图1A)包含DRAM存储单元，和这些存储单元的一些支持电路。此外，可选衬底130包含I/O电路和/或另外的DRAM支持电路(比如选择比特、行、列、块和/或组的电路，以及芯片冗余)。作为替代地或者额外地，叠层116(图1A)可包含静态随机存取存储器(SRAM)宏单元，以及这些宏单元的一些支持电路。在这些实施例中，可选衬底130可包括额外的SRAM支持电路(比如冗余)，以及开关和I/O电路。
现在说明电子器件和计算机系统的实施例。图6是图解说明包括一个或多个芯片封装612，比如芯片封装的前述实施例之一的电子器件600的框图。
图7是图解说明包括一个或多个芯片封装708，比如芯片封装的前述实施例之一的计算机系统700的框图。计算机系统700包括：一个或多个处理器(或处理器核芯)710、通信接口712、用户接口714，和把这些组件耦接在一起的一条或多条信号线722。注意，所述一个或多个处理器(或处理器核芯)710可支持并行处理和/或多线程操作，通信接口712可具有持久性通信连接，且所述一条或多条信号线722可构成通信总线。此外，用户接口714可包括：显示器716、键盘718、和/或指示器720，比如鼠标。
设备700中的存储器724可包括易失性存储器和/或非易失性存储器。更具体地说，存储器724可包括：ROM、RAM、EPROM、EEPROM、闪存、一个或多个智能卡、一个或多个磁盘存储设备，和/或一个或多个光学存储设备。存储器724可保存操作系统726，操作系统726包括用于处理各种基本系统服务以用于执行依赖于硬件的任务的过程(或一组指令)。此外，存储器724还可保存通信模块728中的通信过程(或一组指令)。这些通信过程可用于与一个或多个计算机、设备和/或服务器(包括相对于设备700位于远程的计算机、设备和/或服务器)通信。
存储器724还可包括一个或多个程序模块730(或者一组指令)。注意，程序模块730中的一个或多个可构成计算机程序机构。存储器724中的各个模块之中的指令可用高级过程语言、面向对象的编程语言和/或用汇编或机器语言实现。编程语言可被编译或解释(即，可配置或已配置)，以便由一个或多个处理器(或者处理器核芯)710执行。
计算机系统700可包括但不限于服务器、膝上型计算机、个人计算机、工作站、大型计算机、刀片、企业计算机、数据中心、便携式计算设备、巨型计算机、网络附加存储器(NAS)系统、存储区域网(SAN)系统，和/或其它电子计算设备。例如，芯片封装708可被包括在与多个处理器刀片耦接的底板中，或者芯片封装708可以耦接不同种类的组件(比如处理器、存储器、I/O设备，和/或外围设备)。从而，芯片封装708可执行交换机、集线器、桥接器和/或路由器的功能。注意，计算机系统700可以在一个位置，或者可以分布在多个地理上分散的位置上。
芯片封装100(图1A和1B)、芯片封装200(图2A)、芯片封装250(图2B)、芯片封装300(图3A)、芯片封装330(图3B)、芯片封装360(图3C)、芯片封装380(图3D)、芯片封装400(图4A)、芯片封装450(图4B)、芯片封装500(图5A)、电子器件600(图6)和/或计算机系统700可包括更少的组件或者另外的组件。例如，返回参见图1A，叠层116中的半导体裸片110可具有不同的厚度或宽度。为了保持倾斜组件112相对于可选衬底130和半导体裸片110的表面的定角124，较厚的半导体裸片的水平位置的偏移可大于较薄的半导体裸片110的水平位置的偏移。
此外，可以部署多种增强来改进来自可选衬底130和半导体裸片110的电力分配。可以与倾斜组件112结合地使用常规引线接合来连接可选衬底130和半导体裸片110。一些半导体裸片110和/或倾斜组件112可包括在初始硅制备之后的较厚顶部金属层或者重新分配层(RDL)，以降低电力分配网络的电阻率。另外，例如通过在硅裸片上制备电容器，或者把离散的电容器焊接到其背面，并利用TSV或者用另一种技术，使离散的电容器和供电输送或调节电路电连接，倾斜组件112可包括另外的电源去耦电容器。也可通过主动调节网络输送电力。例如，在倾斜组件112和/或可选衬底130上可包括诸如降压变换器，或者电容器-电容器变换器之类的电路，以提高输送给半导体裸片110的电力供应的质量。
此外，尽管这些器件和系统被图解表示成具有许多不连续的部件，不过这些实施例旨在成为可能存在的各种特征的功能描述，而不是这里描述的实施例的结构示意图。从而，在这些实施例中，两个或更多个组件可被组合成单个组件，和/或可以改变一个或多个组件的位置。此外，两个或更多个前述实施例中的特征可以相互结合。
注意，电子器件600(图6)和/或计算机系统700的一些或者全部功能可用一个或多个专用集成电路(ASIC)和/或一个或多个数字信号处理器(DSP)实现。此外，如本领域中已知，可以更多地用硬件，从而更少地用软件实现前述实施例的功能，或者更少地用硬件，从而更多地用软件实现前述实施例的功能。
虽然前述实施例在芯片封装中使用半导体裸片110(比如硅)，不过在其它实施例中，除半导体外的不同材料可用作这些芯片中的一个或多个芯片中的衬底材料。
上面只是出于举例说明的目的，描述了本发明的实施例。上述说明不是详尽的，也不意图把本发明局限于公开的形式。因而，对本领域的技术人员来说，许多修改和变化将是显而易见的。另外，上面的公开内容并不意图限制本发明。本发明的范围由所附权利要求限定。

Claims (20)

1.一种芯片封装，包括：
在垂直方向，排列成叠层的一组半导体裸片，所述垂直方向基本上与平行于垂直叠层中的第一半导体裸片的平面垂直，其中，在第一半导体裸片之后的给定半导体裸片在所述平面中的水平方向从垂直叠层中的前一个半导体裸片偏移一个偏移值，从而在垂直叠层的一侧限定出梯状平台；和
倾斜组件，所述倾斜组件与半导体裸片电耦合和机械耦合，其中所述倾斜组件被置于垂直叠层的所述一侧，并且
其中所述倾斜组件近似平行于沿着梯状平台的介于所述水平方向和所述垂直方向之间的方向。
2.按照权利要求1所述的芯片封装，其中所述倾斜组件是无源组件。
3.按照权利要求2所述的芯片封装，其中所述无源组件包括具有与半导体裸片电耦合的金属迹线的塑料衬底。
4.按照权利要求1所述的芯片封装，其中所述倾斜组件是另一个半导体裸片。
5.按照权利要求1所述的芯片封装，其中所述倾斜组件包括配置成可重新配合地与电路板电耦合和机械耦合的边缘连接器。
6.按照权利要求1所述的芯片封装，还包括在第一半导体裸片之下的衬底，所述衬底近似平行于所述平面，其中所述衬底至少与所述倾斜组件电耦合。
7.按照权利要求1所述的芯片封装，还包括环绕半导体裸片和倾斜组件的至少一部分的封包。
8.按照权利要求1所述的芯片封装，其中所述倾斜组件被焊接到每个半导体裸片。
9.按照权利要求8所述的芯片封装，其中半导体裸片包括便于把倾斜组件焊接到半导体裸片的凸块，其中所述凸块的高度和节距沿着所述垂直方向在半导体裸片之间变化。
10.按照权利要求1所述的芯片封装，其中所述倾斜组件借助微弹簧，与每个半导体裸片电耦合。
11.按照权利要求1所述的芯片封装，其中所述倾斜组件借助各向异性导电膜，与每个半导体裸片电耦合。
12.按照权利要求11所述的芯片封装，其中半导体裸片包括在半导体裸片顶面上的压缩元件，当装配芯片封装时，所述压缩元件压缩所述各向异性导电膜，从而便于半导体裸片和倾斜组件之间的电耦合。
13.按照权利要求1所述的芯片封装，其中在不把半导体裸片插入倾斜组件中的槽的情况下，使倾斜组件与半导体裸片机械耦接。
14.按照权利要求1所述的芯片封装，其中倾斜组件包括用于半导体裸片的机械挡块，所述机械挡块便利于所述芯片封装的装配。
15.按照权利要求1所述的芯片封装，其中所述倾斜组件和半导体裸片中的给定半导体裸片之间的电耦合具有复阻抗，所述复阻抗包括同相分量和异相分量。
16.按照权利要求1所述的芯片封装，其中在不进行半导体裸片中的芯片穿孔的情况下，所述倾斜组件便于将电信号和功率信号传递到所述半导体裸片。
17.按照权利要求1所述的芯片封装，还包括垂直叠层中的至少两个半导体裸片之间的中间芯片，其中所述中间芯片被配置成沿着水平方向传送由半导体裸片至少之一的工作而产生的热量。
18.按照权利要求1所述的芯片封装，其中半导体裸片的表面包括蚀坑；和
其中蚀坑中的球保持垂直叠层中的半导体裸片的相对对准。
19.一种包括芯片封装的计算机系统，其中所述芯片封装包括：
在垂直方向排列成叠层的一组半导体裸片，所述垂直方向基本上与平行于垂直叠层中的第一半导体裸片的平面垂直，其中，在第一半导体裸片之后的给定半导体裸片在所述平面中的水平方向从垂直叠层中的前一个半导体裸片偏移一个偏移值，从而在垂直叠层的一侧限定出梯状平台；和
倾斜组件，所述倾斜组件与半导体裸片电耦合和机械耦合，其中所述倾斜组件被置于垂直叠层的所述一侧上，并且
其中所述倾斜组件近似平行于沿着所述梯状平台的介于所述水平方向和所述垂直方向之间的方向。
20.一种包括芯片封装的电子器件，其中所述芯片封装包括：
在垂直方向排列成叠层的一组半导体裸片，所述垂直方向基本上与平行于垂直叠层中的第一半导体裸片的平面垂直，其中，在第一半导体裸片之后的给定半导体裸片在所述平面中的水平方向从垂直叠层中的前一个半导体裸片偏移一个偏移值，从而在垂直叠层的一侧限定出梯状平台；和
倾斜组件，所述倾斜组件与半导体裸片电耦合和机械耦合，其中所述倾斜组件被置于垂直叠层的所述一侧，并且
其中所述倾斜组件近似平行于沿着所述梯状平台的介于所述水平方向和所述垂直方向之间的方向。
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