CN103545280B - 多芯片封装体 - Google Patents

多芯片封装体 Download PDF

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Publication number
CN103545280B
CN103545280B CN201210584020.9A CN201210584020A CN103545280B CN 103545280 B CN103545280 B CN 103545280B CN 201210584020 A CN201210584020 A CN 201210584020A CN 103545280 B CN103545280 B CN 103545280B
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chip
semiconductor chip
main substrate
semiconductor
encapsulation body
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CN103545280A (zh
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金基永
朴明根
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

本发明公开了一种多芯片封装体，包括：主基板；多个第一半导体芯片，堆叠在主基板的上表面上，并且具有与主基板电连接的接合焊垫；以及半导体封装体，粘附到堆叠的第一半导体芯片的侧表面，并且与主基板电连接。

Description

多芯片封装体
技术领域
本发明总体涉及半导体封装体，更具体涉及具有能够实现重量轻、薄、紧凑和小型化的新颖形状的多芯片封装体。
背景技术
在半导体封装体中，为了增加容量和扩展功能性，逐渐增加晶片状态下的集成度。此外，其中合并了至少两种半导体芯片或半导体封装体的半导体封装体被普及。
为了扩展在晶片状态下的半导体装置的功能性，在晶片制造工艺中需要充实的设备投资，发生大量的花费，并且应首先解决工艺中容易发生的各种问题。然而，在制造半导体芯片之后将半导体芯片组装为半导体封装体的过程中，可实现将至少两个半导体芯片或至少两个半导体封装体合并成一个封装体而不需解决前述问题。此外，当与在晶片状态下增加容量和扩展功能性相比时，因为该合并需要较低程度的设备投资且不产生大量的花费，所以半导体装置制造者已经在对合并型的半导体封装体（例如，系统级封装（system-in-package，SIP）、多芯片封装体（MCP）以及叠层封装体（package-on-package，POP））进行积极研究。
在这些合并型的半导体封装体中，多芯片封装体通过在一个封装中合并至少两个具有不同功能性的封装体而被制造。在多芯片封装体的示例中，采用这样的结构，其中多个存储器芯片堆叠在基板上，控制器芯片堆叠在堆叠的存储器芯片上，并且存储器芯片和基板以及控制器芯片和基板采用布线电连接。
然而，即使在这样的多芯片封装体中，封装体的厚度也因堆叠在存储器芯片上的控制器芯片的存在而增加，并且用于连接控制器芯片和基板的布线很可能与连接存储器芯片的布线短路。为了防止与控制器芯片连接的布线和与存储器芯片连接的布线短路，连接控制器芯片和基板的布线形成得长。因此，设计复杂，封装体的尺寸增加，并且很可能在模制工艺中发生诸如布线偏移（wire sweeping）和布线损坏的失效。
发明内容
实施例涉及具有能实现重量轻、薄、紧凑和小型化的新颖形状的多芯片封装体。
在实施例中，多芯片封装体包括：主基板；多个第一半导体芯片，堆叠在主基板的上表面上并且具有与主基板电连接的接合焊垫；以及半导体封装体，粘附到堆叠的第一半导体芯片的侧表面并且与主基板电连接。
半导体封装体可包括：子基板，包括安装部分和连接部分，安装部分粘附到堆叠的第一半导体芯片的侧表面且具有第一焊垫，连接部分从安装部分弯曲和延伸，放置在主基板的上表面上并且具有与第一焊垫和主基板电连接的第二焊垫；以及第二半导体芯片，设置在安装部分的的另一表面上，并且具有与第一焊垫电连接的接合焊垫，安装部分的另一表面背对安装部分的粘附到堆叠的第一半导体芯片的侧表面的一个表面。
多芯片封装体还可包括固定构件，形成在连接部分和主基板之间并且使连接部分和主基板彼此固定。
子基板可包括柔性基板、硅基板和引线框基板中的任何一者。
第一半导体芯片和第二半导体芯片可为不同种类的芯片。例如，第一半导体芯片可为存储器芯片，并且第二半导体芯片可为控制器芯片。
主基板还可具有其中安装半导体封装体的凹槽。在此情况下，半导体封装体可包括：子基板，包括安装部分和连接部分，安装部分粘附到堆叠的第一半导体芯片的侧表面且具有第一焊垫，连接部分从安装部分延伸，安装到主基板的凹槽中并且具有与第一焊垫和主基板电连接的第二焊垫；以及第二半导体芯片，设置在安装部分的另一表面上，并且具有与第一焊垫电连接的接合焊垫，安装部分的另一表面背对安装部分的粘附到堆叠的第一半导体芯片的侧表面的一个表面。
多芯片封装体还可包括电连接第一半导体芯片的接合焊垫和主基板的连接构件。另外，各个第一半导体芯片还可具有与接合焊垫电连接的贯穿电极，并且第一半导体芯片可堆叠在主基板上使得贯穿电极彼此连接且与主基板电连接。
第一半导体芯片可垂直堆叠为使得第一半导体芯片的侧表面对齐，并且半导体封装体可粘附到第一半导体芯片的对齐的侧表面。
第一半导体芯片可以实质上台阶状形状堆叠使得接合焊垫被暴露。在此情况下，第一半导体芯片的每一个，在其背对其上设置有接合焊垫的一端的另一端上，可具有面对主基板的台阶表面，并且半导体封装体可粘附到第一半导体芯片的台阶表面和第一半导体芯片的与台阶表面连接的侧表面。
多芯片封装体还可包括第二粘合剂构件，使得第一半导体芯片的侧表面和半导体封装体彼此连接。此外，多芯片封装体还可包括模制部分，模制部分密封主机板的包括第一半导体芯片和半导体封装体的上表面。
多芯片封装体还包括密封主基板的包括第一半导体芯片和半导体封装体的上表面的模制部分。该模制部分包括环氧模制化合物。
第一半导体芯片包括电路模块。多芯片封装体还包括形成在半导体芯片的一个表面上的接合焊垫，接合焊垫构造为用作半导体芯片的电路模块的电接触。主基板是印刷电路板。
附图说明
图1是示出根据实施例的多芯片封装体的截面图。
图2是示出根据实施例的多芯片封装体的截面图。
图3是示出根据实施例的多芯片封装体的截面图。
图4是示出根据实施例的多芯片封装体的截面图。
图5是示出根据实施例的多芯片封装体的截面图。
图6是示出根据实施例的多芯片封装体的截面图。
图7是示出具有根据实施例的多芯片封装体的电子设备的透视图。
图8是示出包括根据实施例的多芯片封装体的电子设备的示例的方框图。
具体实施方式
在下文，将参考附图具体描述各种实施例。
这里，应理解的是，附图不必按比例，并且在某些情况下比例可夸大，以更加清楚地描述本发明的某些特征。
图1是示出根据实施例的多芯片封装体的截面图。
参见图1，根据实施例的多芯片封装体包括主基板10、多个第一半导体芯片20和半导体封装体100。另外，多芯片封装体还可包括第一和第二连接构件51和52、第一和第二粘合剂构件61和62、模制部分（molding part）70以及固定构件80。
主基板10具有上表面11和下表面12。第一连接垫13和第二连接垫14可形成在主基板10的上表面11上，并且球焊盘（ball lands）15可形成在主基板10的下表面12上。外部连接端子16可安装到球焊盘15。主基板10可为印刷电路板（PCB）。
第一半导体芯片20的每一个具有一个表面21、背向该一个表面21的另一表面22和连接一个表面21和另一表面22的侧表面23以及接合焊垫24。
尽管没有示出，但是第一半导体芯片20的每一个可包括电路模块，该电路模块由诸如晶体管、电容器、电阻器等元件构成，用于存储、处理和传输数据。作为电路模块的连接到外部的电接触的接合焊垫24可形成在每个第一半导体芯片20的一个表面21上。
第一半导体芯片20可借助于第一粘合剂构件61堆叠在主基板10的第一和第二连接垫13和14内侧的上表面11上。第一粘合剂构件61可形成在堆叠的第一半导体芯片20之间，并且可形成在堆叠的第一半导体芯片20当中最下面的第一半导体芯片20和主基板10之间。例如，第一粘合剂构件61可将第一半导体芯片20的一个表面21粘附到另一个第一半导体芯片20的另一表面22，并且第一粘合剂构件61可将主基板10的上表面11粘附到第一半导体芯片20的另一表面22。另外，在实施例中，第一半导体芯片20可垂直地堆叠为使它们的侧表面23对齐。
主基板10的第一连接垫13和第一半导体芯片20的接合焊垫24可借助于第一连接构件51电连接。在实施例中，第一连接构件51可由布线构成。
半导体封装体100可包括子基板30和第二半导体芯片40。另外，半导体封装体100还可包括第三连接构件53。
子基板30可包括安装部分31和连接部分32。
安装部分31可借助于第二粘合剂构件62粘附到第一半导体芯片20的对齐的侧表面23。在实施例中，安装部分31可粘附到第一半导体芯片20的另一端的侧表面23，第一半导体芯片20的另一端背对第一半导体芯片20的其上可设置接合焊垫24的一端。
连接部分32可从安装部分31弯曲和延伸，并且可放置在主基板10的上表面11上。
第一焊垫33可形成在安装部分31的另一表面31B上，安装部分31的另一表面31B背对安装部分31的可粘附到第一半导体芯片20的侧表面23的一个表面31A。第二焊垫34可形成在连接部分32的面对主基板10的一个表面32A上，并且可与主基板10的第二连接垫14电连接。尽管没有示出，但是电路迹线可形成在子基板30中，并且第一焊垫33和第二焊垫34可由电路迹线彼此电连接。
尽管子基板30可由柔性基板构成，但是应注意子基板30可由硅基板和引线框基板中的任一者构成。
第二连接构件52可形成在子基板30的第二焊垫34和主基板10的第二连接垫14之间，并且可电连接子基板30的第二焊垫34和主基板10的第二连接垫14。每个第二连接构件52可包括凸块和焊料球中的任一者。
第二半导体芯片40具有在其一个表面40A上的接合焊垫41，并且可以面向下的形式安装到安装部分31使得形成有接合焊垫41的一个表面40A面向安装部分31的另一表面31B。
第二半导体芯片40与第一半导体芯片20可以是不同种类的芯片。例如，第一半导体芯片20可为存储器芯片，而第二半导体芯片40可为控制器芯片。与此不同，第二半导体芯片40与第一半导体芯片20可为相同种类的芯片。
第三连接构件53可形成在子基板30的第一焊垫33和第二半导体芯片40的接合焊垫41之间，并且可电连接子基板30的第一焊垫33和第二半导体芯片40的接合焊垫41。在实施例中，每个第三连接构件53可包括凸块和焊料球中的任一者。
尽管实施例中示例和描述了第二半导体芯片40以面向下的形式设置在子基板30的安装部分31上且第二半导体芯片40的接合焊垫41和子基板30的第一焊垫33可借助于凸块或焊料球电连接，但是应注意，第二半导体芯片40可以面相上的形式设置在子基板30的安装部分31上，使得第二半导体芯片40的另一表面面向子基板30的安装部分31，第二半导体芯片40的另一表面背对第二半导体芯片40的形成有接合焊垫41的一个表面40A，并且第二半导体芯片40的接合焊垫41和子基板30的第一焊垫33可采用布线电连接。
固定构件80可形成在连接部分32的一个表面32A和主基板10之间，并且可使连接部分32和主基板10彼此固定。模制部分可密封包括第一半导体芯片20和半导体封装体100的主基板10的上表面11。模制部分可包括环氧模制化合物（EMC）。
根据实施例，由于第二半导体芯片40和主基板10之间的电连接长度被缩短，所以在防止发生失效和实现重量轻、薄、紧凑和小型化方面可提供优点。
图2是示出根据实施例的多芯片封装体的截面图。根据与图2关联的实施例的多芯片封装体可具有其中第一半导体芯片20可堆叠成台阶状形状的构造。因此，除第一半导体芯片20的堆叠结构之外，根据与图2关联的实施例的多芯片封装体与根据与图1关联的实施例的多芯片封装体可具有基本相同的结构。因此，这里将省略相同构件部分的重复描述，并且相同的术语和相同的参考标号用于指示相同的构件部分。
参见图2，第一半导体芯片20可堆叠成台阶状形状使得接合焊垫24可被暴露。
第一半导体芯片20的每一个，在其背对其上可设置接合焊垫24的一端的另一端上，可具有面对主基板10的台阶表面25。
半导体芯片100的子基板30的安装部分31可粘附到第一半导体芯片20的台阶表面25和第一半导体芯片20的可与台阶表面25连接的侧表面23，并且半导体封装体100可设置在第一半导体芯片20的台阶表面25和主基板10之间的空间中。
根据与图2关联的实施例，因为半导体封装体100设置在第一半导体芯片20的台阶表面25和主基板10之间的空间中，所以可减少由于存在半导体封装体100引起的可能增加封装尺寸的问题，因此在实现重量轻、薄、紧凑和小型化方面可提供优点。
图3是示出根据实施例的多芯片封装体的截面图。根据与图3关联的实施例的多芯片封装体可具有这样的结构，其中电连接子基板30的第二焊垫34和主基板10的第二连接垫14的第二连接构件52可包括布线。因此，除第二连接构件52之外，根据与图3关联的实施例的多芯片封装体与图2关联的各种实施例的多芯片封装体具有基本上相同的构造。因此，这里将省略相同构件部分的重复描述，并且相同的术语和相同的参考标号用于指示相同的构件部分。
参见图3，子基板30的第二焊垫34可形成在连接部分32的背对一个表面32A的另一表面32B上，一个表面32A面对主基板10。子基板30的第二焊垫34和主基板10的第二连接垫14可采用由布线构成的第二连接构件52电连接。
图4是示出根据实施例的多芯片封装体的截面图。根据与图4关联的实施例的多芯片封装体可具有这样的结构，其中第一半导体芯片20还包括贯穿电极25，并且第一半导体芯片20的接合焊垫24和主基板10的第一连接垫13可采用贯穿电极25电连接。因此，除贯穿电极25之外，根据与图4关联的实施例的多芯片封装体与根据与图1关联的各种实施例的多芯片封装体具有基本相同的构造。因此，这里将省略相同构件部分的重复描述，并且相同的术语和相同的参考标号用于指示相同的构件部分。
参见图4，第一半导体芯片20的每一个具有可与接合焊垫24电连接的贯穿电极25。各个第一半导体芯片20的贯穿电极25穿过接合焊垫24。第一半导体芯片20可堆叠在主基板10上，使得它们的贯穿电极25彼此连接，并且贯穿电极25和主基板10的第一连接垫13可电连接。
图5是示出根据实施例的多芯片封装体的截面图。根据与图5关联的实施例的多芯片封装体具有这样的结构，其中主基板10另外具有凹槽17，并且半导体封装体100安装到主基板10的凹槽17中。因此，除主基板10和半导体封装体100之外，根据与图5关联的实施例的多芯片封装体与根据与图4关联的实施例的多芯片封装体可具有基本相同的结构。因此，这里将省略相同构件部分的重复描述，并且相同的术语和相同的参考标号用于指示相同的构件部分。
参见图5，主基板10具有限定在主基板10的上表面11上的凹槽17，并且半导体封装体100安装到凹槽17中。主基板10的第二连接垫14可设置在主基板10的内表面上，主基板10的内表面可因限定凹槽17而形成。
半导体封装体100的子基板30的连接部分32插入主基板10的凹槽17中，并且形成在子基板30的连接部分32上的第二焊垫34可与形成在主基板10的内表面上的第二连接垫14电连接。
图6是示出根据实施例的多芯片封装体的截面图。根据与图6关联的实施例的多芯片封装体可具有这样的结构，其中主基板10另外具有半导体封装体100安装到其中的凹槽17，并且半导体封装体100的子基板30的连接部分32安装到主基板10的凹槽17中。因此，除主基板10和半导体封装体100之外，根据与图6关联的实施例的多芯片封装体与根据与图1关联的实施例的各种实施例的多芯片封装体具有基本相同的构造。因此，这里将省略相同的构件部分的重复描述，并且相同的术语和相同的参考标号用于指示相同的构件部分。
参见图6，主基板10具有凹槽17，其限定在主基板10的上表面11中并且半导体封装体100安装在其中。主基板10的第二连接垫14可设置在主基板10的内表面上，主基板10的内表面可因限定凹槽17而形成。
半导体封装体100的子基板30的连接部分32插入主基板10的凹槽17中，并且形成在子基板30的连接部分32上的第二焊垫34可与形成在主基板10的内表面上的第二连接垫14电连接。
尽管在图1至6所示的前述实施例中示出和描述了仅一个半导体封装体100可粘附到第一半导体芯片20的侧表面23，但是应注意各种实施例不限于此，并且可包括粘附至少两个半导体封装体100的情况。
上述的多芯片封装体可应用于各种电子设备。
图7是示出具有根据实施例的多芯片封装体的电子设备的透视图。
参见图7，根据各种实施例的多芯片封装体可应用于诸如便携式电话的电子设备1000。因为根据本发明实施例的多芯片封装体提供的优点在于能够防止发生失效且实现重量轻、薄、紧凑和小型化，所以提供了改善电子设备1000的可靠性和减小其尺寸的优点。电子设备1000不限于图7所示的便携式电话，并且可包括各种电子应用，例如，诸如移动电子应用、膝上电脑、笔记本电脑、便携式多媒体播放器（PMP）、MP3播放器、便携式摄像机、网络写字板、无线电话、导航仪和个人数字助理（PDA）等。而且，根据本发明实施例的多芯片封装体可应用于用于电子应用中的SD（安全数字）卡、记忆棒、MMC（多媒体卡）、CF（紧凑式闪存，compact flash）和SSC（固态驱动器）等。
图8是示出可包括根据各种实施例的多芯片封装体的电子设备的示例的方框图。
参见图8，电子系统1300可包括控制器1310、输入/输出单元1320和存储器1330。控制器1310、输入/输出单元1320和存储器1330可通过总线1350彼此耦合。总线1350用作数据通过其移动的通路。例如，控制器1310可包括至少一个微处理器、至少一个数字信号处理器、至少一个微控制器和能够执行与这些构件的相同的功能的逻辑装置中的至少任何一种。控制器1310和存储器1330可包括根据本发明的多芯片封装体。输入/输出单元1320可包括选自键区、键盘和显示装置等当中的至少之一。存储器1330是存储数据的装置。存储器1330可存储控制器1310等要执行得数据和/或指令。存储器1330可包括易失性存储装置和/或非易失性存储装置。另外，存储器1330可由闪存构成。例如，应用本发明技术的闪存可安装到信息处理系统，例如，移动终端或台式电脑。闪存可由固态驱动器（SSD）构成。在此情况下，电子系统1300可在闪存系统中稳定地存储大量的数据。电子系统1300还可包括接口1340，构造为从通讯网络接收数据以及传输数据到通讯网络。接口1340可为有线型或无线型。例如，接口1340可包括天线、或者有线或无线收发器。此外，尽管没有示出，但是本领域的技术人员应容易理解，电子系统1300可另外提供有应用芯片组、相机成像处理器（CIS）、输入/输出单元等。
尽管为了示例的目的已经描述了各种实施例，但是本领域的技术人员应理解，在不脱离所附权利要求公开的本发明的范围和精神的情况下，各种变型、附加和替换都是可能的。
本申请要求于2012年7月11日提交韩国知识产权局的韩国专利申请第10-2012-0075576号的优先权，其全文通过引用结合于此。

Claims (17)

1.一种多芯片封装体，包括：
主基板；
多个第一半导体芯片，堆叠在该主基板的上表面上，并且具有与该主基板电连接的接合焊垫；以及
半导体封装体，粘附到堆叠的第一半导体芯片的侧表面，并且具有与该主基板电连接的第二焊垫；以及
第一连接构件，电连接该第一半导体芯片的该接合焊垫和该主基板，
其中在不穿过该主基板的情况下，该半导体封装体不电连接到该第一半导体芯片，
其中该第一半导体芯片垂直堆叠，使该第一半导体芯片的侧表面对齐，并且该半导体封装体粘附到该第一半导体芯片的该对齐的侧表面，
其中该半导体封装体的该第二焊垫中的每一个通过该主基板和该第一连接构件共用地连接到该第一半导体芯片。
2.根据权利要求1所述的多芯片封装体，其中该半导体封装体包括：
子基板，包括安装部分以及连接部分，该安装部分粘附到堆叠的第一半导体芯片的侧表面并且具有与该第二焊垫电连接的第一焊垫，该连接部分从该安装部分弯曲和延伸，放置在该主基板的上表面上并且具有该第二焊垫；以及
第二半导体芯片，设置在该安装部分的另一表面上，并且具有与该第一焊垫电连接的接合焊垫，该安装部分的另一表面背对该安装部分的粘附到堆叠的第一半导体芯片的侧表面的一个表面。
3.根据权利要求2所述的多芯片封装体，还包括：
固定构件，形成在该连接部分和该主基板之间，并且使该连接部分和该主基板彼此固定。
4.根据权利要求2所述的多芯片封装体，其中该子基板包括柔性基板、硅基板和引线框基板中的任何一者。
5.根据权利要求2所述的多芯片封装体，其中该第一半导体芯片和该第二半导体芯片是不同种类的芯片。
6.根据权利要求5所述的多芯片封装体，其中该第一半导体芯片是存储器芯片，而该第二半导体芯片是控制器芯片。
7.根据权利要求1所述的多芯片封装体，其中该主基板还具有其中安装该半导体封装体的凹槽。
8.根据权利要求7所述的多芯片封装体，其中该半导体封装体包括：
子基板，包括安装部分和连接部分，该安装部分粘附到堆叠的第一半导体芯片的侧表面且具有第一焊垫，该连接部分从该安装部分延伸，安装到该主基板的该凹槽中并且具有与该第一焊垫和该主基板电连接的第二焊垫；以及
第二半导体芯片，设置在与该安装部分的另一表面上，并且具有与该第一焊垫电连接的接合焊垫，该安装部分的另一表面背对该安装部分的粘附到堆叠的第一半导体芯片的侧表面的一个表面。
9.根据权利要求8所述的多芯片封装体，其中该第二焊垫通过电路迹线与该第一焊垫电连接。
10.根据权利要求8所述的多芯片封装体，其中该子基板包括柔性基板、硅基板和引线框基板中的任何一者。
11.根据权利要求8所述的多芯片封装体，其中该第一半导体芯片和该第二半导体芯片是不同种类的芯片。
12.根据权利要求11所述的多芯片封装体，其中该第一半导体芯片是存储器芯片，而该第二半导体芯片是控制器芯片。
13.根据权利要求1所述的多芯片封装体，其中该第一连接构件包括布线。
14.根据权利要求1所述的多芯片封装体，
其中各个第一半导体芯片还具有与该接合焊垫电连接的贯穿电极，并且
其中该第一半导体芯片堆叠在该主基板上，使贯穿电极彼此连接且与该主基板电连接。
15.根据权利要求1所述的多芯片封装体，其中该第一半导体芯片的每一个，在其背对其上设置有该接合焊垫的一端的另一端上，具有面对该主基板的台阶表面，并且该半导体封装体粘附到该第一半导体芯片的该台阶表面以及该第一半导体芯片的与该台阶表面连接的侧表面。
16.根据权利要求1所述的多芯片封装体，还包括：
第一粘合剂构件，形成在堆叠的第一半导体芯片之间以及该主基板和堆叠的第一半导体芯片当中最下面的第一半导体芯片之间。
17.根据权利要求1所述的多芯片封装体，还包括：
第二粘合剂构件，使得该第一半导体芯片的侧表面和该半导体封装体彼此粘附。
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