JP6000951B2 - 組立部品およびチップパッケージを組立てるための方法 - Google Patents
組立部品およびチップパッケージを組立てるための方法 Download PDFInfo
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- JP6000951B2 JP6000951B2 JP2013527082A JP2013527082A JP6000951B2 JP 6000951 B2 JP6000951 B2 JP 6000951B2 JP 2013527082 A JP2013527082 A JP 2013527082A JP 2013527082 A JP2013527082 A JP 2013527082A JP 6000951 B2 JP6000951 B2 JP 6000951B2
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- semiconductor die
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Description
分野
本開示は、概して、半導体チップパッケージを製造するプロセスに関する。より具体的には、本開示は、組立部品、および、チップパッケージを組立てるための技術に関し、それは、スタック内に配列された一群のチップと、スタックに対して角度が付けられた傾斜部品を含む。
スタック状の半導体ダイまたはチップを含むチップパッケージは、プリント回路基板に接続された従来の個別にパッケージ化されたチップに比べて、非常に高い性能を提供することができる。これらのチップパッケージは、スタック内における異なるチップに対して異なるプロセスを用いる能力、高密度のロジックとメモリとを組み合わせる能力、および、より少電力でデータを転送する能力のような特定の利点も提供する。たとえば、ダイナミックランダムアクセスメモリ(DRAM)を実現するチップのスタックは、ベースチップ内の入出力(I/O)およびコントローラ機能を実現するために高金属層カウント(high-metal-layer-count)で高機能な論理プロセスを使用し、より低い金属層カウントでDRAM専用のプロセスチップが、スタックの残余のために用いられ得る。このように、結合された一組のチップは、DRAMプロセスを用いて製造されたI/Oおよびコントローラの機能を含む単一のチップ、ロジックプロセスを用いて製造されたメモリ回路を含む単一のチップ、および/または、ロジックおよびメモリ双方の物理構造を製造するために単一のプロセスを用いようとすることよりも、良好な性能でかつ低コストを有し得る。
本開示の1つの実施形態は、第1の階段状テラス(stepped terrace)を有する筐体を含む組立部品を提供する。この第1の階段状テラスは、垂直方向に一連の段を含み、一連の段における第1の段以降の各段は、一連の段における直前の段から第1のオフセット値だけ水平方向にオフセットされる。さらに、筐体は、一組の半導体ダイと結合するように構成され、一組の半導体ダイは、垂直スタックにおいて、垂直方向に配列され、垂直方向は、垂直スタックにおける第1の半導体ダイ対して実質的に垂直である。さらに、第1の半導体ダイの後の各半導体ダイは、垂直スタックにおける直前の半導体ダイから第2のオフセット値だけ水平方向にオフセットされ、それによって、垂直スタックの一方の側面に第2の階段状テラスを規定する。
組立部品、組立部品を用いてチップパケージを組立てるための方法、および、組立部品を用いずにチップパケージを組立てるための他の方法の実施形態が記載される。このチップパッケージは、垂直方向にスタック状に配列された一組の半導体ダイを含み、一組の半導体ダイは、水平方向に互いにオフセットされて、垂直スタックの一方の側面において階段状テラスを規定する。さらに、チップパッケージは、垂直スタックの上記の一方の側面に位置付けられた傾斜部品を含み、傾斜部品は、階段状テラスに沿った方向に略平行である。このチップパッケージは、上記の組立部品を用いて組立てられ得る。特に、その組立部品は、他の階段状テラスを有する筐体を含み得る。この他方の階段状テラスは、垂直方向に一連の段を含み、その一連の段は水平方向に互いにオフセットされる。さらに、筐体は、一組の半導体ダイが垂直方向においてスタック内に配列されるように、一組の半導体ダイと結合するように構成され得る。たとえば、他方の階段状テラスは、階段状テラスの略鏡像であり得る。
Claims (18)
- 組立部品であって、
第1の階段状テラスを含む筐体を備え、
前記第1の階段状テラスは、垂直方向に一連の段を含み、
前記一連の段における第1段の後の各段は、前記一連の段における直前の段から第1のオフセット値だけ水平方向にオフセットされ、
前記筐体は、垂直スタック内において一組の半導体ダイが前記垂直スタック内の第1の半導体ダイに実質的に垂直な垂直方向に配列されるように前記一組の半導体ダイと結合するように構成され、
前記第1の半導体ダイの後の各半導体ダイは、前記垂直スタック内における直前の半導体ダイから第2のオフセット値だけ水平方向にオフセットされ、それによって、前記垂直スタックの一方の側面に第2の階段状テラスを規定し、
前記第1のオフセット値は、前記第2のオフセット値よりも大きい、組立部品。 - 前記第1の階段状テラスは、前記第2の階段状テラスの略鏡像である、請求項1に記載の組立部品。
- 前記一組の半導体ダイにおける所与の半導体ダイは、公称厚みを有し、
前記一連の段における所与の段の垂直変位は、前記公称厚みよりも大きい、請求項1に記載の組立部品。 - 前記組立部品は、傾斜部品が前記半導体ダイと堅固に機械的に結合されるチップパッケージの組立を容易にし、
前記傾斜部品は、前記垂直スタックの前記一方の側面に位置付けられ、
前記傾斜部品は、水平方向と垂直方向との間である前記第2の階段状テラスに沿った方向に略平行である、請求項1に記載の組立部品。 - 前記チップパッケージは追加基板を含み、前記傾斜部品および前記半導体ダイは、前記追加基板上に搭載される請求項4に記載の組立部品。
- 前記第1のオフセット値および前記第2のオフセット値は、前記方向と、前記傾斜部品を前記一組の半導体ダイに堅固に機械的に結合するために用いられるはんだの公称厚みと
に基づいて決定される、請求項4に記載の組立部品。 - 前記組立部品は、垂直方向における前記一組の半導体ダイにわたり、前記一組の半導体ダイと前記半導体ダイ間の一組の接着層とに関連する垂直誤差の合計よりも小さい積算位置誤差を伴って、前記一組の半導体ダイの組立てを容易にする、請求項1に記載の組立部品。
- 前記積算位置誤差は、前記半導体ダイの厚み変動に関連する、請求項7に記載の組立部品。
- 前記積算位置誤差は、前記一組の接着層の厚み変動に関連する、請求項7に記載の組立部品。
- 前記積算位置誤差は、前記一組の接着層における熱拡散材料の厚み変動に関連する、請求項7に記載の組立部品。
- 前記組立部品は、前記半導体ダイの端部変動に関連した、所定値よりも小さい最大位置誤差を伴って、前記一組の半導体ダイの組立てを容易にする、請求項1に記載の組立部品。
- チップパッケージを組立てるための方法であって、
筐体の垂直方向における第1の階段状テラス内の一連の段における第1の段に近接した半導体ダイの垂直スタックにおいて、第1の半導体ダイの端部を位置付けるステップを備え、
垂直方向は、前記第1の半導体ダイに実質的に垂直であり、
前記方法は、
前記第1の半導体ダイの上面に接着層を塗布するステップと、
前記筐体の垂直方向における前記一連の段内の第2の段に近接した前記半導体ダイの前記垂直スタックにおいて、第2の半導体ダイの端部を位置付けるステップとをさらに備え、
前記第2の半導体ダイの底面は、前記接着層に機械的に結合され
前記第2の段は、前記第1の段から第1のオフセット値だけ水平方向にオフセットされ、
前記第2の半導体ダイは、第2のオフセット値だけ水平方向にオフセットされ、それによって前記垂直スタックの一方の側面に第2の階段状テラスを規定し、
前記方法は、
前記第1の半導体ダイおよび前記第2の半導体ダイに傾斜部品を堅固に機械的に結合するステップをさらに備え、
前記傾斜部品は、前記垂直スタックの前記一方の側面に位置付けられ、
前記傾斜部品は、水平方向と垂直方向との間である前記第2の階段状テラスに沿った方向に略平行であり、
前記第1のオフセット値は、前記第2のオフセット値よりも大きい、方法。 - 前記第1の半導体ダイおよび前記第2の半導体ダイのうちの1つにすることができる所与の半導体ダイを位置付けるステップは、ピックアンドプレースツールを含む、請求項12に記載の方法。
- 前記第1の半導体ダイおよび前記第2の半導体ダイのうちの1つにすることができる所与の半導体ダイを位置付けるステップは、前記所与の半導体ダイ上の光学アライメントマーカに基づく、請求項12に記載の方法。
- チップパッケージを組立てるための方法であって、
半導体ダイの垂直スタック内において第1の半導体ダイを位置付けるステップを備え、
前記垂直スタックは、前記第1の半導体ダイに実質的に垂直な垂直方向に沿っており、
前記方法は、
前記第1の半導体ダイの上面に接着層を塗布するステップと、
前記半導体ダイの前記垂直スタックにおける第2の半導体ダイの端部を、前記第1の半導体ダイに対して位置付けるステップとをさらに備え、
前記第2の半導体ダイの底面は、前記接着層に機械的に結合され、
前記第2の半導体ダイは、あるオフセット値だけ水平方向にオフセットされ、それによって、前記垂直スタックの一方の側面に階段状テラスを規定し、
前記方法は、
傾斜部品を前記第1の半導体ダイおよび前記第2の半導体ダイに堅固に機械的に結合するステップをさらに備え、
前記傾斜部品は、前記垂直スタックの前記一方の側面に位置付けられ、
前記傾斜部品は、水平方向と垂直方向との間である前記階段状テラスに沿った方向に略平行であり、
前記第1の半導体ダイおよび前記第2の半導体ダイのうちの1つにすることができる所与の半導体ダイを位置付けるステップは、ピックアンドプレースツールを用いることと、前記所与の半導体ダイ上の光学アライメントマーカを基準とすることとを含む、方法。 - 前記接着層は、所与の半導体ダイの平面内に熱を優先的に伝達する熱拡散材料を含む、請求項7に記載の組立部品。
- 前記チップパッケージは追加基板を含み、前記傾斜部品および前記半導体ダイは、前記追加基板上に搭載される請求項12または15に記載の方法。
- 前記接着層は、所与の半導体ダイの平面内に熱を優先的に伝達する熱拡散材料を含む、請求項12または15に記載の方法。
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