CN103081103A - 制造斜坡-叠层芯片封装的固定装置 - Google Patents
制造斜坡-叠层芯片封装的固定装置 Download PDFInfo
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- CN103081103A CN103081103A CN2011800421931A CN201180042193A CN103081103A CN 103081103 A CN103081103 A CN 103081103A CN 2011800421931 A CN2011800421931 A CN 2011800421931A CN 201180042193 A CN201180042193 A CN 201180042193A CN 103081103 A CN103081103 A CN 103081103A
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Abstract
描述了组装组件以及用于使用该组装组件来组装芯片封装的技术。此芯片封装包括在垂直方向成叠层地排列的一组半导体管芯,这些半导体管芯在水平方向彼此偏移,以在垂直叠层的一边限定阶梯台阶。此芯片封装可以使用组装组件来组装。该组装组件可以包括具有另一阶梯台阶的外壳。此另一阶梯台阶可以包括在水平方向彼此偏移的垂直方向的一系列梯级。此外,外壳还可以被配置成与该组半导体管芯匹配,以便该组半导体管芯在垂直方向上成叠层地排列。例如,另一阶梯台阶可以大致是阶梯台阶的镜像。
Description
技术领域
本发明一般涉及制造半导体芯片封装的工艺。更具体而言,本发明涉及用于组装包括叠层地排列的一组的芯片和相对于叠层成一定角度的斜坡组件的芯片封装的组装组件和技术。
背景技术
包括叠层的半导体芯片或管芯的芯片封装与连接到印刷电路板的常规独立封装的芯片相比,可以提供显著更高的性能。这些芯片封装还提供某些优点,诸如下列能力:在叠层中的不同的芯片上使用不同的工艺以组合较高密度逻辑和存储器,以及使用较少的功率来传输数据。例如,实现动态随机存取存储器(DRAM)的芯片的叠层可以在基芯片中使用高金属层数(high-metal-layer-count)、高性能的逻辑工艺来实现输入/输出(I/O)和控制器功能,对于叠层的其余部分,可以使用一组较低的金属层数、DRAM专用的处理的芯片。如此,该组合的芯片集可以比下列各项具有更好的性能和较低的成本:使用DRAM工艺制造的包括I/O和控制器功能的单个芯片;使用逻辑工艺制造的包括存储器电路的单个芯片;和/或尝试使用单个工艺来制造逻辑和存储器物理结构。
然而,难以组装包括叠层的半导体芯片的芯片封装。具体而言,现有的组装技术耗时且产量低(可能增大芯片封装的成本)。例如,在许多现有的组装技术中,半导体芯片的叠层上的总的垂直位置误差是与半导体芯片中的每一个相关联的垂直位置误差的总和。结果,包括多个半导体芯片的叠层的总的垂直位置误差可能变得特别大。这可能导致紧张的制造容限,从而降低单个垂直位置误差(这可能增大半导体管芯的成本)和/或可能约束在叠层中组装的半导体芯片的数量(这可能会限制性能)。
因此,所需要的是用于组装芯片的叠层而不会产生上文所描述的问题的技术。
发明内容
本发明的一个实施例提供包括具有第一阶梯台阶的外壳的组装组件。此第一阶梯台阶包括垂直方向的一系列梯级,其中,该一系列梯级中的第一梯级之后的每一个梯级都在水平方向从该一系列梯级中的紧邻的前面的梯级偏移第一偏移值。此外,外壳还被配置成与一组半导体芯片匹配,以便该组半导体管芯在垂直方向上成叠层地排列,垂直方向基本上垂直于垂直叠层中的第一半导体管芯。另外,第一半导体芯片之后的每一个半导体芯片都在水平方向从垂直叠层中的紧邻的前面的半导体芯片偏移第二偏移值,从而,在垂直叠层的一边限定第二阶梯台阶。
此组装组件可以有利于芯片封装的组装,其中:斜坡组件以刚性机械方式耦合到半导体芯片;斜坡组件被定位在垂直叠层的一边上;以及,斜坡组件大致平行于沿着第二阶梯台阶的方向,所述方向介于所述水平方向和所述垂直方向之间。例如,为有利于组装,第一阶梯台阶大致可以大致是第二阶梯台阶的镜像。此外,该组半导体管芯中的给定半导体芯片可以具有额定厚度,一系列梯级中的给定梯级的垂直位移可以大于该额定厚度。另外,第一偏移值可以与第二偏移值相同或大于它。
注意到,所述第一偏移值和所述第二偏移值可以基于所述方向和用来以刚性机械方式将所述斜坡组件耦合到该组半导体管芯的焊料的额定厚度来确定。
在某些实施例中,所述组装组件有利于该组半导体管芯的组装,在垂直方向上在该组半导体管芯上累积的位置误差小于与该组半导体管芯和所述半导体芯片之间的一组粘合剂层相关联的垂直误差的总和。例如,累积的位置误差可以与下列各项相关联:半导体芯片的厚度变化,该组粘合剂层的厚度变化;和/或该组粘合剂层中的散热材料的厚度变化。另外,所述组装组件可以有利于该组半导体管芯的组装,与所述半导体芯片的边缘变化相关联的最大位置误差小于预定义的值。
另一实施例提供了用于使用组装组件来组装芯片封装的方法。在此方法中,半导体芯片的垂直叠层中的第一半导体芯片的边缘被定位在外壳的垂直方向中第一阶梯台阶中的一系列梯级中的第一梯级附近。注意到,垂直方向基本上垂直于第一半导体芯片。然后,对第一半导体管芯的顶表面施加粘合剂层。此外,半导体管芯的垂直叠层中的第二半导体管芯的边缘被定位在外壳的垂直方向中一系列梯级中的第二梯级附近。接下来,第二半导体管芯的底表面以机械方式耦合到粘合剂层,其中,所述第二梯级在水平方向从所述第一梯级偏移第一偏移值,并且其中,所述第二半导体管芯在水平方向偏移第二偏移值,从而,在所述垂直叠层的所述一边限定第二阶梯台阶。此外,斜坡组件还以刚性机械方式耦合到第一半导体管芯和第二半导体管芯,其中,斜坡组件被定位在垂直叠层的一边上,以及,其中,斜坡组件大致平行于沿着第二阶梯台阶的方向,所述方向介于所述水平方向和所述垂直方向之间。
注意到,定位可以是所述第一半导体管芯和所述第二半导体管芯中的一个的给定半导体管芯可以涉及拾取与放置工具。此外,此定位还可以基于给定半导体管芯上的光学校准标记。
在某些实施例中,粘合剂层包括优选地在给定半导体管芯的平面中导热的散热材料。
另外,以刚性机械方式将所述斜坡组件耦合到所述第一半导体管芯和所述第二半导体管芯可以涉及在下列各项中的一个上熔化焊料:斜坡组件和/或第一半导体管芯和第二半导体管芯。注意到,当以刚性机械方式将所述斜坡组件耦合到所述第一半导体管芯和所述第二半导体管芯时,可以在垂直方向上施加压缩力。
另一实施例提供了用于不使用组装组件来组装芯片封装的方法。在此方法中,第一半导体管芯被定位在半导体管芯的垂直叠层中,其中,垂直叠层沿着基本上垂直于第一半导体管芯的垂直方向。然后,对第一半导体管芯的顶表面施加粘合剂层。此外,半导体管芯的垂直叠层中的第二半导体管芯的边缘被相对于第一半导体管芯定位,其中,所述第二半导体管芯的底表面以机械方式耦合到所述粘合剂层,其中,所述第二半导体管芯在水平方向偏移第二偏移值,从而,在所述垂直叠层的一边限定阶梯台阶。此外,斜坡组件还以刚性机械方式耦合到第一半导体管芯和第二半导体管芯,其中,斜坡组件被定位在垂直叠层的所述一边上,以及,其中,斜坡组件大致平行于介于水平方向和垂直方向之间的沿着第二阶梯台阶的方向。
附图说明
图1是示出了根据本发明的一个实施例的用于组装芯片封装的组装组件的框图。
图2是示出了根据本发明的实施例的使用图1的组装组件来组装芯片封装的框图。
图3是示出了根据本发明的实施例的组装的芯片封装的侧视图的框图。
图4是示出了根据本发明的实施例的组装的芯片封装的顶视图的框图。
图5是示出了根据本发明的实施例的使用图1的组装组件来组装芯片封装的方法的流程图。
图6是示出了根据本发明的实施例的不使用图1的组装组件来组装芯片封装的方法的流程图。
注意到,在整个附图中类似的附图标记表示对应的部分。此外,相同的部分的多个实例通过利用虚线与实例编号分离的共同的前缀来表示。
具体实施方式
描述了组装组件、用于使用组装组件来组装芯片封装的方法,以及用于在不使用组装组件的情况下组装芯片封装的另一方法的各实施例。此芯片封装包括在垂直方向叠层地排列的一组半导体管芯,这些半导体管芯在水平方向彼此偏离,以在垂直叠层的一边限定出的阶梯台阶。此外,该芯片封装包括定位在垂直叠层的一边的斜坡组件,该斜坡组件大致平行于沿着阶梯台阶的方向。此芯片封装可以使用组装组件来组装。具体而言,该组装组件可以包括具有另一阶梯台阶的外壳。此另一阶梯台阶可以包括垂直方向的一系列梯级,该一系列梯级在水平方向彼此偏移。此外,外壳可以被配置成与该组半导体管芯匹配,以便该组半导体管芯在垂直方向上叠层地排列。例如,另一阶梯台阶可以大致是阶梯台阶的镜像。
通过有利于芯片封装的组装,该组装组件和组装技术可以实现高性能的芯片封装(诸如带有高带宽互连的芯片封装)的低成本、高生产量制造。具体而言,这些实施例可以在芯片封装的组装过程中有利于机械误差缩小,以及更能够容忍芯片封装中的组件的大小和位置中的机械变化的芯片封装。例如,通过使用这些实施例,可以在芯片封装中组装该组半导体管芯,叠层上的总的垂直位置误差小于与半导体管芯和半导体管芯之间的粘合剂层相关联的垂直位置误差(有时称为“垂直误差”)。这可以通过独立地定位每一个半导体管芯到组装组件(代替在组装过程中以机械方式定位叠层中的给定半导体管芯到紧邻的前面的半导体管芯)来实现。因而,组装组件和相关联的组装技术可以阻止单个垂直位置误差被复合。作为替代地,在具有少量的半导体管芯的叠层中(诸如其中与叠层相关联的复合的总的垂直位置误差不太大的那些),可以使用其他组装技术来来组装芯片封装而不使用组装组件。
我们现在描述组装组件和芯片封装的各实施例。图1呈现了示出了在组装芯片封装(诸如图3和4中的芯片封装300,有时称为“斜坡叠层芯片封装”)过程中可以被用来定位和固定半导体管芯(或芯片)的组装组件100的框图。此组装组件包括具有阶梯台阶112的外壳110。此外,此阶梯台阶在垂直方向116包括一系列梯级114。注意到,梯级114-1之后的每一个梯级都在水平方向118从一系列梯级114中的紧邻的前面的梯级偏移偏移值120中的相关联的一个偏移值。此外,偏移值120中每一个还可以对于一系列梯级114具有大致恒定的值,或者可以在一系列梯级114上变化(即,阶梯台阶112中的不同的梯级114的偏移值可以不同)。另外,与一系列梯级114相关联的垂直位移122(除梯级114-1或梯级114-N的那些以外的)每一个都可以具有大致恒定的值或可以在一系列梯级114上变化(即,阶梯台阶112中的不同的梯级114的垂直位移可以不同)。
如呈现了示出了使用此组装组件来组装芯片封装的框图的图2所示,外壳110可以被配置成与一组半导体管芯210匹配,以便该组半导体管芯210在垂直方向116在叠层212中排列。注意到,垂直方向116基本上垂直于叠层212中的半导体管芯210-1(并因此带有水平方向118)。另外,半导体管芯210-1之后的每一个半导体管芯都可以在水平方向118从叠层212中的紧邻的前面的半导体管芯偏移“偏移值”214中的相关联的一个偏移值,从而,在叠层212的一边限定阶梯台阶216。这些偏移值可以对于该组半导体管芯210具有大致恒定的值或者可以在该组半导体管芯210上变化(即,对于阶梯台阶216中的不同的梯级的偏移值可以不同)。
此外,如呈现了示出了组装的芯片封装300的侧面图的框图的图3所示,组装组件100(图1)可以有利于芯片封装300的组装,其中:高带宽斜坡组件312以刚性机械方式和以电的方式耦合到半导体管芯210,从而有利于半导体管芯210之间的通信,并向半导体管芯210供电;斜坡组件312被定位在叠层212(图2)的一边上;以及,斜坡组件312大致平行于沿着阶梯台阶216(图2)的方向314(以角度316),该方向314在水平方向118和垂直方向116之间。
回头参考图2,为有利于组装,阶梯台阶112(图1)可以大致是阶梯台阶216(图2)的镜像。此外,该组半导体管芯210中的给定半导体管芯可以具有额定厚度220,一系列梯级114的序列中的给定梯级的垂直位移可以大于额定厚度220(或者它可以大于半导体管芯210中的任何一个的最大厚度)。然而,注意到,在某些实施例中,叠层212中的至少某些半导体管芯210的厚度可以不同(例如,厚度可以在叠层212上变化)。
在示例性实施例中,垂直位移122可以各自是160μm对150±5μm的额定厚度220。(然而,在其他实施例中,厚度220可以介于30和250μm之间)相对于厚度220的此额外的垂直位移可以使粘合剂层222中的粘合剂在组装过程中展开。注意到,对于150μm的额定厚度220,角度316(图3)可以介于15°和20°之间。一般而言,额定厚度220部分地取决于叠层212中的半导体管芯210的数量。此外,还注意到,粘合剂层222的额定厚度224可以是10μm。(然而,在其他实施例中,粘合剂层222的厚度可以沿着叠层212中的垂直方向116变化。)
另外,阶梯台阶112(图1)中的给定梯级中的偏移值可以大于或等于阶梯台阶216中的相关联的偏移值。一般而言,偏移值120(图1)和偏移值214可以基于图3中的方向314(或角度316)和用来以刚性机械方式将斜坡组件312(图3)耦合到该组半导体管芯210的焊料(诸如图3中的焊球318)的额定厚度来确定。注意到,焊料的厚度可以在叠层212上大致是恒定的,或者可以在叠层上变化(即,沿着垂直方向116)。
在某些实施例中,组装组件100(图1)有利于该组半导体管芯210的组装,在垂直方向116该组半导体管芯210上的累积的位置误差(即,叠层212上的半导体管芯的垂直位置中的累积的位置误差)小于与该组半导体管芯210和半导体管芯210之间的粘合剂层222(诸如在150°C在10s内硫化的环氧树脂或胶水)相关联的垂直误差的总和。例如,累积的位置误差可以与下列各项相关联:半导体管芯210的厚度变化,粘合剂层222的厚度变化;和/或至少某些粘合剂层222中的可选的散热材料226(诸如模压石墨纤维)的厚度变化。在某些实施例中,累积的位置误差可以小于1μm,可以小到0μm。另外,组装组件100(图1)可以有利于该组半导体管芯210的组装,与半导体管芯210的边缘变化(诸如锯齿线位置中的变化)相关联的最大位置误差(即,图3中的距离320中的最大误差)小于预定义的值(例如,最大位置误差可以小于1μm,并可以小到0μm)。如下面参考图5进一步描述的,这可以通过使用拾取和放置工具,使用半导体管芯210上的光学校准标记(诸如基准标记)来组装芯片封装300(图3)来实现,以便相对于半导体管芯210的锯齿道的中心来测量距离320(图3)。(另选地或另外地,在某些实施例中,图1中的组装组件100包括诸如使用聚酰亚胺制造的机械限动器之类的机械限动器,在组装图3中的芯片封装300过程中,可以对着这些机械限动器向上推半导体管芯210,从而在水平方向118和/或垂直方向116有利于期望的容许度。)
回头参考图3,注意到,为了适应垂直方向116的机械校准误差,焊料块或焊盘(诸如焊盘322-1和/或焊盘322-2)和/或焊料318的高度和节距可以沿着垂直方向116在至少一些半导体管芯210之间变化。例如,距离320(即,焊盘322-1相对于半导体管芯210-1的锯齿道的中心的位置)可以是60μm,焊盘322可以各自都具有80μm宽度。此外,在回流或熔化之前焊球(诸如焊球318)可以具有120μm的直径,在熔化之后,可以具有40和60μm之间的大致厚度。在某些实施例中,两行或更多行焊球可以刚性地将斜坡组件312耦合到给定半导体管芯。
图4呈现了示出了其中叠层212(图2)包括四个半导体管芯210的组装的芯片封装300的顶视图的框图。芯片封装300的此视图示出了,在某些实施例中,焊盘410可以具有非矩形的形状。例如,焊盘410可以具有长方形,诸如80μm宽和120μm长的那些。半导体管芯210和/或斜坡组件312上的这些焊盘形状可以容忍某些水平和/或垂直位置误差。
在某些实施例中,焊盘可以被移到斜坡组件312的边缘。这可以有利于垂直取向(即,图3中的角度316可以是0°)。此配置可以有利于存储器模块,其中,与输入/输出(I/O)信号线和电源线相关联的触点或焊盘位于斜坡组件的边缘(代替沿着“脊骨”)。如此,可以缩小斜坡组件中的扩散层的数量。例如,此存储器模块中沿着斜坡组件312的边缘可以有60个触点或焊盘。
通过在芯片封装300的组装过程中允许叠层工艺被定位到图1中的组装组件100(而不是图2中的叠层212中的紧邻的前面的半导体管芯),此组装组件可以有效地缩小与芯片封装300中的组件的大小和厚度的机械变化相关联的水平和/或垂直位置误差。如此,图1中的组装组件100可以有利于芯片封装300的高度准确的和高产量的组装。此外,由于此组装组件还有利于诸如“拾取与放置”工具之类的高容量的和低成本的制造技术的使用,它可以大大地降低芯片封装300的成本。
另外,组装低成本的,高产量的芯片封装的能力可以有利于高性能的设备。例如,在某些实施例中,斜坡叠层芯片封装(诸如芯片封装300)被包括在双列直插存储器模块中。例如,在斜坡-叠层芯片封装中可以有多达80个存储器设备(诸如动态随机存取存储器或另一种类型的存储器存储设备)。如果需要,可以禁用“坏的”或有故障的存储器设备。如此,可以使用(80个中的)72个存储器设备。此外,此配置还可以暴露存储器模块中的存储器设备的全带宽,以便在访问存储器设备中的任何一个时延迟很少或没有延迟。
作为替代地,双列直插存储器模块可以包括多个字段,每一个字段都可包括斜坡-叠层芯片封装。例如,在双列直插存储器模块中可以有四个斜坡-叠层芯片封装(每一个都包括九个存储器设备)。
在某些实施例中,这些双列直插存储器模块(可包括一个或多个斜坡-叠层芯片封装)中的一个或多个可以耦合到处理器。例如,处理器可以使用以电容方式耦合的信号的电容性近程通信(PxC)耦合到一个或多个双列直插存储器模块。处理器又可以使用C4焊球安装在衬底上。
我们现在描述组装技术的各实施例。图5呈现了示出了用于使用组装组件100(图1)来组装芯片封装的方法500的流程图。在此方法中,半导体管芯的垂直叠层中的第一半导体管芯的边缘被定位在诸如组装组件中的外壳之类的外壳的垂直方向的第一阶梯台阶中的一系列梯级中的第一梯级的附近(操作510)。注意到,垂直方向基本上垂直于第一半导体管芯。然后,对第一半导体管芯的顶表面施加粘合剂层(操作512)。
此外,半导体管芯的垂直叠层中的第二半导体管芯的边缘被定位在外壳的垂直方向的一系列梯级中的第二梯级附近,而第二半导体管芯的底表面以机械方式耦合到粘合剂层(操作514)。注意到,第二梯级在水平方向从第一梯级偏移第一偏移值,而第二半导体管芯在水平方向偏移第二偏移值,从而在垂直叠层的一边限定第二阶梯台阶。此外,斜坡组件还以刚性机械方式耦合到第一半导体管芯和第二半导体管芯(操作516),其中,斜坡组件被定位在垂直叠层的一边上,以及,其中,斜坡组件大致平行于沿着第二阶梯台阶的方向,所述方向介于所述水平方向和所述垂直方向之间。
注意到,定位给定半导体管芯(可以是所述第一半导体管芯和所述第二半导体管芯中的一个)可以涉及拾取与放置工具。在示例性实施例中,水平和/或垂直校准在1-10μm内。此外,此定位还可以基于给定半导体管芯上的光学校准标记。例如,光学校准标记可以包括基准标记。
另外,以刚性机械方式将斜坡组件耦合到第一半导体管芯和第二半导体管芯可以涉及在下列各项中的一个上熔化焊料:斜坡组件和/或第一半导体管芯和第二半导体管芯。当回流焊料时,斜坡组件可以被置于叠层上或反之亦然。这可以使斜坡组件(或半导体管芯的叠层)的重量帮助克服焊料的表面张力。
注意到,当以刚性机械方式将所述斜坡组件耦合到所述第一半导体管芯和所述第二半导体管芯时,可以在垂直方向上施加压缩力。这可以确保组装的芯片封装具有所需的高度。在某些实施例中,沿着斜坡组件的法线施加压缩力。这些压缩力中的任何一个都可以例如通过填充或缩小芯片封装中的各组件之间的间隔而改善叠层内的热传递。
尽管方法500示出了组装组件100(图1)的使用,但是,在其他实施例中,芯片封装300(图3和4)在不使用组装组件100(图1)的情况下被组装。这在具有几个半导体管芯(或较少)并且因此对累积的位置误差不太敏感的芯片封装中是可能的。
在图6中示出了对应的组装技术,该图呈现了示出了用于不使用组装组件100(图1)来组装芯片封装的方法600的流程图。在此方法中,第一半导体管芯被定位在半导体管芯的垂直叠层中(操作610),其中,垂直叠层沿着基本上垂直于第一半导体管芯的垂直方向。然后,对第一半导体管芯的顶表面施加粘合剂层(操作612)。此外,半导体管芯的垂直叠层中的第二半导体管芯的边缘被相对于第一半导体管芯定位(操作614),其中,所述第二半导体管芯的底表面以机械方式耦合到所述粘合剂层,其中,所述第二半导体管芯在水平方向偏移第二偏移值,从而,在所述垂直叠层的一边限定一个阶梯台阶。此外,斜坡组件还以刚性机械方式耦合到第一半导体管芯和第二半导体管芯(操作616),其中,斜坡组件被定位在垂直叠层的一边上,以及,其中,斜坡组件大致平行于沿着阶梯台阶的方向,所述方向介于水平方向和垂直方向之间。
在方法500(图5)和600的某些实施例中,可以有额外的或更少的操作。例如,可以以包括半导体管芯的子集的构件组装,构件随后被合并到完整叠层。此外,操作的顺序可以更改,和/或可以将两个或更多操作合并到单个操作中。
注意到,组装组件100(图1)和芯片封装300(图3和4)可以包括更少的组件或额外的组件。例如,在斜坡-叠层芯片封装中的半导体管芯的叠层中可以定义中断,诸如通过在斜坡组件上不包括用于半导体管芯中的一个或多个的焊盘来实现。此外,虽然这些设备和系统被示为具有若干个离散的项,但是,这些实施例旨在作为可以存在的各种特征的功能描述,而并非此处所描述的各实施例的结构示意。因此,在这些实施例中,可以将两个或更多组件合并到单个组件中,和/或可以更改一个或多个组件的位置。
尽管前面的各实施例在芯片封装中使用半导体管芯(诸如硅),但是,在其他实施例中,在这些芯片中的一个或多个中可以使用半导体之外的不同的材料来作为衬底材料。然而,在使用硅的各实施例中,半导体管芯210(图2-4)可以使用标准的硅处理来制造。这些半导体管芯可以提供支持逻辑和/或存储器功能的硅区域。
此外,在图3中,斜坡组件312还可以是无源组件,诸如带有金属迹线以电耦合到半导体管芯210的塑料衬底。例如,斜坡组件312可以使用注模塑料来制造。作为替代地,斜坡组件312可以是带有平版印刷地定义的线路或信号线的另一半导体管芯。在斜坡组件312包括半导体管芯的各实施例中,可以包括诸如限制放大器之类的有源设备,以降低信号线之间的串扰。另外,可以使用差分信号来在有源或者无源斜坡组件312中减小串扰。
在某些实施例中,斜坡组件312包括晶体管和通过焊球(诸如焊球318)在半导体管芯210之间往复地传输数据和功率信号的线路。例如,斜坡组件312可以包括高电压信号。这些信号可以通过使用下列各项被递降以供用于半导体管芯210上:递降调节器(诸如电容器-电容器递降调节器),以及电容器和/或电感器分立组件,以耦合到半导体管芯210。
另外,斜坡组件312可以包括存储器的缓存器或逻辑芯片,和/或到外部设备和/或系统的I/O连接器。例如,I/O连接器可以包括一个或多个:球键合、线键合、用于耦合到外部设备的边缘连接器和/或PxC连接器。在某些实施例中,这些I/O连接器可以在斜坡组件312的背面上,而斜坡组件312可以包括将I/O连接器耦合到诸如焊盘322-2之类的焊盘的一个或多个硅通孔(TSV)。
在某些实施例中,芯片封装300中的斜坡组件312和半导体管芯210安装在可选衬底(诸如印刷电路板或半导体管芯)上。此可选衬底可以包括:球键合、线键合、用于耦合到外部设备的边缘连接器和/或PxC连接器。如果这些I/O连接器位于可选衬底的背面,则该可选衬底可以包括一个或多个TSV。
尽管在前面的各实施例中作为斜坡组件312和半导体管芯210的电气和机械耦合的说明使用了焊球,但是,在其他实施例中,这些组件可以使用其他技术来电耦合和/或机械耦合,诸如:微弹簧、微球体(在下面所描述的球坑(ball-in-pit)配置中),和/或各向异性膜(诸如各向异性弹性体膜,有时称为“各向异性导电膜”)。
在芯片封装中的各组件与电磁耦合的信号的PxC(诸如斜坡组件312和半导体管芯210之间的、斜坡组件312和外部设备之间的、斜坡组件312和可选衬底之间的、可选衬底和半导体管芯210之间的和/或可选衬底和外部设备之间的PxC)进行通信的各实施例中,PxC可以包括:以电容方式耦合的信号的通信(称为“电近程通信”)、以光学方式耦合的信号的通信(称为“光近程通信”)、电磁耦合的信号的通信(称为“电磁近程通信”)、感应耦合的信号的通信,和/或传导耦合的信号的通信。
一般而言,所产生的电触点的阻抗可以是传导和/或电容性的,即,可以具有包括同相分量和/或异相分量的复阻抗。不管电触点机制是什么(诸如焊、微弹簧、各向异性层等等),如果与触点相关联的阻抗是导电的,则常规发射与接收I/O电路可以用于芯片封装300中的各组件中。然而,对于具有复合(以及,可能,可变的)阻抗的触点,发射与接收I/O电路可以包括2009年4月日17日提出的Robert J.Drost等人的律师卷号为SUN09-0285的标题为“Receive Circuit forConnectors with Variable Complex Impedance”的美国专利申请12/425,871中所描述的一个或多个实施例,该申请的内容以引用的方式并入本文中。
注意到,当面临较低的半导体管芯产量或在封装和组装之前的比较高的代价来充分地测试,允许某些返工的封装技术更有成本效益。因此,在半导体管芯210和斜坡组件312之间的机械和/或电气耦合是可重新匹配的各实施例中,可以通过允许返工(诸如替换在组装过程中标识的坏的芯片、测试或预烧)来增大芯片封装300的产量。关于这一点,可重新匹配的机械的或电气的耦合应该被理解为是可以反复地(即,两次或更多次)建立和中断而不要求返工或加热(诸如利用焊料)的机械的或电气的耦合。在某些实施例中,可重新匹配的机械的或电气的耦合包括被设计用于彼此耦合的阴阳组件(诸如按压在一起的组件)。
尽管图3示出了芯片封装300的特定配置,但是,可以使用若干种技术和配置来实现机械校准和组装,使用或不使用组装组件100(图1)。例如,半导体管芯210和/或斜坡组件312可以使用球-坑校准技术(更一般而言,正特征在负特征中(positive-feature-in-negative-feature)校准技术),相对于彼此定位。具体而言,可以将球定位到蚀刻坑中,以相对地对齐诸如叠层212(图2)中的半导体管芯210之类的组件。正的特征的其他示例包括半球形的凸起。然而,以机械方式锁定芯片封装300中的组件上的正的和负的表面特征的任何组合可以被用来对齐和/或组装芯片封装300。
参考图2,如前面在某些实施例中所指出的,可选的散热材料226(图2)(更一般而言,半导体管芯210之间的具有高导热性的中间材料)可以帮助消除在一个或多个半导体管芯210和/或斜坡组件312(图3和4)上的电路的操作过程中所生成的热量。此热管理可以包括下列热通路中的任何一个:半导体管芯210的平面中的第一热通路;粘合剂层222的平面中的第二热通路;和/或可选的散热材料226的平面中的第三热通路。具体而言,可以通过芯片封装的边缘中的热耦合,来彼此独立地管理与这些热通路相关联的热通量。注意到,此热管理可以包括使用:相变冷却、浸没冷却,和/或冷板。还要注意,通过芯片封装的边缘中的截面区域扩散的与第一热通路相关联的热通量是额定厚度220的函数。如此,热管理在具有较大的或较小的额定厚度的半导体管芯210的芯片封装中不同。
注意到,在芯片封装300(图3和4)的至少一部分周围可以有可选的包封。另外,芯片封装300(图3和4)中的各组件之间的气隙可以不被填满以改善散热。这可以通过缩小图3中的角度316来促进,即,半导体管芯210朝向垂直方向116更倾斜。
前述的描述计划使任何所属技术领域的专业人员实现并使用本发明,是在特定申请以及其要求的上下文中提供的。此外,前面的对本发明的各实施例的描述只是为了说明和描述。它们不是为了详尽的解释或将本发明限制在所公开的准确的形式。相应地,许多修改方案和变化将对本领域技术人员显而易见,此处所定义的一般原理可以应用于其他实施例和申请,而不会偏离本发明的精神和范围。另外,对前面的各实施例的讨论不旨在限制本发明。如此,本发明不仅限于所示出的实施例,而是根据与所公开的原理和特点一致的最广阔的范围。
Claims (20)
1.一种组装组件,包括外壳,所述外壳包括第一阶梯台阶,其中,所述第一阶梯台阶包括垂直方向的一系列梯级,
其中,所述一系列梯级中的第一梯级之后的每一个梯级在水平方向中从所述一系列梯级中的紧邻的前面的梯级偏移第一偏移值,
其中,所述外壳被配置成与一组半导体管芯匹配,以便该组半导体管芯在垂直方向上成叠层地排列,所述垂直方向基本上垂直于所述垂直叠层中的第一半导体管芯,以及
其中,所述第一半导体管芯之后的每一个半导体管芯在水平方向与所述垂直叠层中的紧邻的前面的半导体管芯偏移第二偏移值,从而在所述垂直叠层的一边限定第二阶梯台阶。
2.如权利要求1所述的组装组件,其中,所述第一阶梯台阶大致是所述第二阶梯台阶的镜像。
3.如权利要求1所述的组装组件,其中,该组半导体管芯中的给定半导体管芯具有额定厚度;以及
其中,所述一系列梯级中的给定梯级的垂直位移大于所述额定厚度。
4.如权利要求1所述的组装组件,其中,所述第一偏移值大于所述第二偏移值。
5.如权利要求1所述的组装组件,其中,所述组装组件有利于芯片封装的组装,其中,斜坡组件以刚性机械方式耦合到所述半导体管芯,
其中,所述斜坡组件被定位在所述垂直叠层的一边上,以及
其中,所述斜坡组件大致平行于沿着所述第二阶梯台阶的方向,所述方向介于所述水平方向和所述垂直方向之间。
6.如权利要求5所述的组装组件,其中,所述第一偏移值和所述第二偏移值是基于所述方向和用来以刚性机械方式将所述斜坡组件耦合到该组半导体管芯的焊料的额定厚度来确定的。
7.如权利要求1所述的组装组件,其中,所述组装组件有利于该组半导体管芯的组装,使得在垂直方向上在该组半导体管芯上累积的位置误差小于与该组半导体管芯和所述半导体管芯之间的一组粘合剂层相关联的垂直误差的总和。
8.如权利要求7所述的组装组件,其中,所述累积的位置误差与所述半导体管芯的厚度变化相关联。
9.如权利要求7所述的组装组件,其中,所述累积的位置误差与该组粘合剂层的厚度变化相关联。
10.如权利要求7所述的组装组件,其中,所述累积的位置误差与该组粘合剂层中的散热材料的厚度变化相关联。
11.如权利要求1所述的组装组件,其中,所述组装组件有利于该组半导体管芯的组装,使得与所述半导体管芯的边缘变化相关联的最大位置误差小于预定义的值。
12.一种用于组装芯片封装的方法,包括:
将半导体管芯的垂直叠层中的第一半导体管芯的边缘定位于外壳的垂直方向中第一阶梯台阶中的一系列梯级中的第一梯级附近,其中,所述垂直方向基本上垂直于所述第一半导体管芯;
对所述第一半导体管芯的顶表面施加粘合剂层;
将半导体管芯的所述垂直叠层中的第二半导体管芯的边缘定位于所述外壳的垂直方向中所述一系列梯级中的第二梯级附近,其中,所述第二半导体管芯的底表面以机械方式耦合到所述粘合剂层,其中,所述第二梯级在水平方向从所述第一梯级偏移第一偏移值,其中,所述第二半导体管芯在水平方向偏移第二偏移值,从而,在所述垂直叠层的一边限定第二阶梯台阶;以及
以刚性机械方式将斜坡组件耦合到所述第一半导体管芯和所述第二半导体管芯,其中,所述斜坡组件被定位在所述垂直叠层的所述一边上,以及
其中,所述斜坡组件大致平行于介于所述水平方向和所述垂直方向之间的沿着所述第二阶梯台阶的方向。
13.如权利要求12所述的方法,其中,定位给定半导体管芯涉及拾取与放置工具,所述半导体管芯能够是所述第一半导体管芯和所述第二半导体管芯中的一个。
14.如权利要求12所述的方法,其中,定位给定半导体管芯是基于所述给定半导体管芯上的光学校准标记的,所述半导体管芯能够是所述第一半导体管芯和所述第二半导体管芯中的一个。
15.如权利要求12所述的方法,其中,所述粘合剂层包括优选地在给定半导体管芯的平面中导热的散热材料。
16.如权利要求12所述的方法,其中,以刚性机械方式将所述斜坡组件耦合到所述第一半导体管芯和所述第二半导体管芯包括在下列各项中的一个上熔化焊料:所述斜坡组件、所述第一半导体管芯和所述第二半导体管芯,以及所述斜坡组件以及所述第一半导体管芯和所述第二半导体管芯。
17.如权利要求12所述的方法,其中,以刚性机械方式将所述斜坡组件耦合到所述第一半导体管芯和所述第二半导体管芯包括在垂直方向施加压缩力。
18.如权利要求12所述的方法,其中,所述第一阶梯台阶大致是所述第二阶梯台阶的镜像。
19.如权利要求12所述的方法,其中,能够是所述第一半导体管芯和所述第二半导体管芯中的一个的给定半导体管芯具有额定厚度;以及
其中,所述一系列梯级中的给定梯级的垂直位移大于所述额定厚度。
20.一种用于组装芯片封装的方法,包括:
将第一半导体管芯定位在半导体管芯的垂直叠层中,其中,所述垂直叠层沿着基本上垂直于所述第一半导体管芯的垂直方向;
对所述第一半导体管芯的顶表面施加粘合剂层;
将半导体管芯的所述垂直叠层中的第二半导体管芯的边缘相对于所述第一半导体管芯定位,其中,所述第二半导体管芯的底表面以机械方式耦合到所述粘合剂层,其中,所述第二半导体管芯在水平方向偏移一个偏移值,从而,在所述垂直叠层的一边限定阶梯台阶;以及
以刚性机械方式将斜坡组件耦合到所述第一半导体管芯和所述第二半导体管芯,其中,所述斜坡组件被定位在所述垂直叠层的所述一边上,以及
其中,所述斜坡组件大致平行于介于所述水平方向和所述垂直方向之间的沿着所述阶梯台阶的方向。
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- 2011-08-04 WO PCT/US2011/046517 patent/WO2012030469A2/en active Application Filing
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- 2011-08-04 EP EP11754564.0A patent/EP2612355B1/en active Active
- 2011-08-04 KR KR1020137005216A patent/KR101807743B1/ko active IP Right Grant
- 2011-08-04 JP JP2013527082A patent/JP6000951B2/ja active Active
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CN104603640A (zh) * | 2013-09-05 | 2015-05-06 | 皇家飞利浦有限公司 | 辐射探测器元件 |
CN104603640B (zh) * | 2013-09-05 | 2018-03-30 | 皇家飞利浦有限公司 | 辐射探测器元件 |
CN105659382A (zh) * | 2013-10-21 | 2016-06-08 | 甲骨文国际公司 | 用于控制堆叠裸片的位置的技术 |
CN105659382B (zh) * | 2013-10-21 | 2019-04-12 | 甲骨文国际公司 | 用于控制堆叠裸片的位置的技术 |
CN111048479A (zh) * | 2019-12-27 | 2020-04-21 | 华天科技(西安)有限公司 | 一种多芯片堆叠封装结构及其封装方法 |
CN111048479B (zh) * | 2019-12-27 | 2021-06-29 | 华天科技(南京)有限公司 | 一种多芯片堆叠封装结构及其封装方法 |
CN111554682A (zh) * | 2020-05-18 | 2020-08-18 | 中国科学院微电子研究所 | 一种半导体器件及其制作方法 |
CN111554682B (zh) * | 2020-05-18 | 2023-03-21 | 中国科学院微电子研究所 | 一种半导体器件及其制作方法 |
Also Published As
Publication number | Publication date |
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KR20130105819A (ko) | 2013-09-26 |
WO2012030469A2 (en) | 2012-03-08 |
US20120049376A1 (en) | 2012-03-01 |
EP2612355B1 (en) | 2021-06-30 |
JP6000951B2 (ja) | 2016-10-05 |
TWI517353B (zh) | 2016-01-11 |
JP2013536998A (ja) | 2013-09-26 |
US8373280B2 (en) | 2013-02-12 |
EP2612355A2 (en) | 2013-07-10 |
TW201220464A (en) | 2012-05-16 |
WO2012030469A3 (en) | 2012-05-10 |
KR101807743B1 (ko) | 2017-12-13 |
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