CN105659382A - 用于控制堆叠裸片的位置的技术 - Google Patents

用于控制堆叠裸片的位置的技术 Download PDF

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Publication number
CN105659382A
CN105659382A CN201480057576.XA CN201480057576A CN105659382A CN 105659382 A CN105659382 A CN 105659382A CN 201480057576 A CN201480057576 A CN 201480057576A CN 105659382 A CN105659382 A CN 105659382A
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semiconductor die
assembling
ladder
vertical
stacked chips
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CN201480057576.XA
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CN105659382B (zh
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M·H·S·达伊里格尔
R·D·霍普金斯
A·乔
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Oracle International Corp
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Oracle International Corp
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Abstract

描述了组装部件(100)和用于使用该组装部件组装芯片封装的技术。这种芯片封装包括布置在垂直方向中的堆叠中的半导体裸片集合(310-1至310-N)，其中半导体裸片在水平方向彼此偏移，以便在垂直堆叠的一侧定义阶梯台阶(112-1)。而且，可以利用该组装部件(100)来组装芯片封装。特别地，组装部件可以包括大致镜像芯片封装的阶梯台阶并且在芯片封装组装期间为在垂直堆叠中定位半导体裸片集合的组装工具提供垂直位置参照的阶梯台阶对(112-1，112-2)。

Description

用于控制堆叠裸片的位置的技术
发明人：MichaelH.S.Dayringer、R.DavidHopkins和AlexChow
技术领域
本公开内容一般而言涉及制造半导体芯片封装的过程。更具体而言，本公开内容涉及用于组装芯片封装的组装部件和关联技术，其中芯片封装包括在垂直堆叠中彼此偏移以定义阶梯台阶的一组芯片。
背景技术
与连接到印刷电路板的常规单独封装芯片相比，包括堆叠的半导体芯片或裸片的芯片封装可以提供显著更高的性能。这些芯片封装还提供某些优点，诸如以下能力：对堆叠中的不同芯片使用不同工艺、组合更高密度的逻辑和存储器，以及利用较少的功率传送数据。例如，实现动态随机存取存储器(DRAM)的芯片堆叠可以在基础芯片(basechip)中使用高金属层计数、高性能逻辑工艺来实现输入/输出(I/O)和控制器功能，并且对于堆叠的其余部分可以使用一组较低金属层计数、DRAM专门处理过的芯片。以这种方式，组合的芯片集可以比：包括利用DRAM工艺制造的I/O和控制器功能的单个芯片；包括利用逻辑工艺制造的存储器电路的单个芯片；和/或试图使用单个工艺来制造逻辑和存储器物理结构二者具有更好的性能和更低的成本。
但是，组装包括堆叠的半导体芯片的芯片封装会是困难的。特别地，现有的组装技术可能是耗时的并且可能具有低成品率(这会增加芯片封装的成本)。例如，在许多现有的组装技术中，半导体芯片堆叠各处的总垂直位置误差是与每个半导体芯片关联的垂直位置误差的总和。因此，对于包括多个半导体芯片的堆叠而言，总垂直位置误差会变得过大。这会导致严格的制造公差以减少各个垂直位置误差(这会增加半导体裸片的成本)，和/或会限制可以在堆叠中被组装的半导体芯片的数量(这会限制性能)。
因此，所需要的是没有上述问题的、用于组装芯片堆叠的技术。
发明内容
本公开内容的一种实施例提供一种组装部件，该组装部件包括具有垂直的阶梯堆叠的阶梯台阶对，其中给定的阶梯在阶梯的平面内从相邻的阶梯偏移，以定义该阶梯台阶对。阶梯台阶对中的阶梯提供在斜坡堆叠芯片封装的组装期间限制组装工具的垂直位置的垂直参照位置，在斜坡堆叠芯片封装中，半导体裸片集合布置在垂直堆叠中。而且，斜坡堆叠芯片封装中给定的半导体裸片在该半导体裸片集合的平面内从相邻的半导体裸片偏移，以定义阶梯台阶。在斜坡堆叠芯片封装的组装期间，当阶梯台阶对限制组装工具的垂直位置时，组装工具机械耦合到给定的半导体裸片的顶表面，并且给定的半导体裸片的底表面机械耦合到斜坡堆叠芯片封装。
应当注意的是，半导体裸片集合可以包括N个半导体裸片(诸如超过40个半导体裸片)，并且斜坡堆叠芯片封装中半导体裸片集合沿垂直堆叠在垂直方向的位置误差可以独立于在斜坡堆叠芯片封装中的垂直位置。例如，位置误差可以各自小于±20μm。此外，组装部件可以便于斜坡堆叠芯片封装的组装，半导体裸片集合沿垂直堆叠在垂直方向的累积位置误差小于与半导体裸片集合和半导体裸片之间的粘合层关联的位置误差的总和。累积位置误差可以与半导体裸片的厚度变化和/或粘合层的厚度变化关联。
此外，给定的半导体裸片可以包括顶表面上的焊盘和凸块，并且组装工具可以在顶表面上除焊盘和凸块所处位置之外的区域中拾取给定的半导体裸片。
在一些实施例中，阶梯台阶是阶梯台阶对的镜像图像。
应当注意的是，给定的半导体裸片可以具有标称厚度，并且阶梯台阶中给定阶梯的垂直位移可以大于该标称厚度。
而且，组装部件可以便于斜坡部件刚性机械耦合到斜坡堆叠芯片封装。这个斜坡部件可以在垂直堆叠的一侧上定位并且可以大致平行于沿阶梯台阶的方向，该方向在半导体裸片集合的平面中的水平方向与沿垂直堆叠的垂直方向之间。
另一种实施例提供一种用于组装斜坡堆叠芯片封装的方法。在这种方法期间，粘合剂施加到斜坡堆叠芯片封装中的半导体裸片的顶表面，在该斜坡堆叠芯片封装中，半导体裸片集合布置在垂直堆叠中，其中在垂直堆叠中的给定的半导体裸片在该半导体裸片集合的平面中从相邻的半导体裸片偏移，以定义阶梯台阶。然后，利用组装工具，第二半导体裸片在第二半导体裸片的顶表面上被拾取。接下来，第二半导体裸片的底表面被放置在半导体裸片的顶表面上的粘合剂上，同时组装工具的垂直位置由具有布置在斜坡堆叠芯片封装的两侧上的阶梯台阶对的组装部件中的给定阶梯限制，其中阶梯台阶对中的阶梯提供垂直参照位置。
应当注意的是，对半导体裸片集合中的附加半导体裸片重复执行施加操作、拾取操作和放置操作，以组装斜坡堆叠芯片封装，并且在组装斜坡堆叠芯片封装时，组装工具的垂直位置由阶梯台阶对中的阶梯限制。
附图说明
图1是示出根据本公开内容实施例、用于组装芯片封装的组装部件的顶视图的框图。
图2是示出根据本公开内容实施例的图1的组装部件的侧视图的框图。
图3是示出根据本公开内容实施例、利用图1和图2的组装部件的芯片封装的组装的侧视图的框图。
图4是示出根据本公开内容实施例、利用图1和图2的组装部件的芯片封装的组装的前视图的图。
图5是示出根据本公开内容实施例的组装好的芯片封装的侧视图的框图。
图6是示出根据本公开内容实施例的组装好的芯片封装的顶视图的框图。
图7是示出根据本公开内容实施例、利用图1和图2的组装部件组装芯片封装的方法的流程图。
应当注意的是，相同的标号贯穿附图指对应的部分。而且，相同部分的多个实例由通过破折号与实例编号分开的公共前缀指定。
具体实施方式
描述了组装部件和用于利用该组件部件组装芯片封装的方法的实施例。这种芯片封装包括布置在垂直方向中的堆叠中的半导体裸片集合，这些半导体裸片在水平方向彼此偏移，以便在垂直堆叠的一侧定义阶梯台阶。而且，芯片封装包括在垂直堆叠的一侧上定位的斜坡部件，该斜坡部件大致平行于沿阶梯台阶的方向。这种芯片封装可以利用组装部件进行组装。特别地，该组装部件可以包括大致镜像芯片封装的阶梯台阶并且为组装工具提供垂直位置参照的一对阶梯台阶，其中组装工具在芯片封装的组装期间在垂直堆叠中定位半导体裸片集合。
通过便于芯片封装的组装，组装部件和组装技术可以使得能够实现高性能芯片封装(诸如具有高带宽互连的芯片封装)的低成本、高吞吐量制造。特别地，这些实施例可以便于芯片封装的组装期间降低的机械误差，以及对芯片封装中部件的尺寸和位置的机械变化更宽容的芯片封装。例如，利用这些实施例，半导体裸片集合可以在芯片封装中被组装，其中堆叠各处的总垂直位置误差小于与半导体裸片和半导体裸片之间的粘合层关联的垂直位置误差(其有时被称为“垂直错误”)。这可以通过独立地参照(referencing)将芯片封装中的每个半导体裸片定位到组装部件的组装工具来实现(而不是在组装期间机械地将堆叠中的给定的半导体裸片参照到紧挨着之前的半导体裸片)。因此，组装部件和关联的组装技术可以防止个别垂直位置误差混合(compounded)。
现在描述组装部件和芯片封装的实施例。图1给出了示出可被用来在芯片封装(诸如图5和图6中的芯片封装500，其有时被称为“斜坡堆叠芯片封装”)的组装期间定位和固定半导体裸片(或芯片)的组装部件100(其有时被称为“制造夹具”)的顶视图的框图。这种组装部件包括一对阶梯台阶112，其可利用研磨机来制作。这些阶梯台阶可以在正被组装的斜坡堆叠芯片封装的两侧上。而且，给定的阶梯台阶(诸如阶梯台阶112-1)包括在垂直方向116的一系列阶梯114(图2)。应当注意的是，阶梯114-1之后的每个阶梯在水平方向118从阶梯序列114中紧挨着的前一阶梯偏移偏移值120中的关联的偏移值。此外，对于阶梯序列114偏移值120可以各自具有大致恒定的值，或者对阶梯序列114偏移值120可以变化(即，用于阶梯台阶112对中的不同阶梯114的偏移值可以不同)。
此外，如给出示出组装部件100的侧视图的框图的图2中所示，与阶梯序列114关联的垂直位移122(而不是用于阶梯114-1或阶梯114-N的垂直位移)可以各自具有大致恒定的值，或者对阶梯序列114可以变化(即，用于阶梯台阶112中的不同阶梯114的垂直位移可以不同)。
如给出示出利用这种组装部件进行芯片封装组装的侧视图的框图的图3中所示，阶梯台阶对可以被配置为与定位半导体裸片集合310(例如，50个半导体裸片310)的组装工具308配对，使得半导体裸片集合310布置在垂直方向116中的堆叠312中。应当注意的是，垂直方向116基本上垂直于堆叠312中的半导体裸片310-1(并且因此垂直于水平方向118)。此外，半导体裸片310-1之后的每个半导体裸片可以在水平方向118从堆叠312中紧挨着的前一半导体裸片偏移偏移值314中的关联的偏移值，由此在堆叠312的一侧定义阶梯台阶。对半导体裸片310这些偏移值可以具有大致恒定的值，或者对半导体裸片310这些偏移值可以变化(即，用于阶梯台阶112-1中不同阶梯的偏移值可以不同)。
在芯片封装的组装期间，当阶梯台阶对限制与给定阶梯对114(图1和图2)配对的组装工具308的垂直位置的时候，组装工具308被机械耦合到给定的半导体裸片的顶表面(例如，给定的半导体裸片可以利用真空被保持在适当位置)，并且给定的半导体裸片的底表面被机械耦合到芯片封装(例如，利用粘合剂，诸如胶水)。不像现有的其中给定的半导体裸片的底表面被用作参照的组装技术，通过使用顶表面作为参照，这种组装技术可以对会导致堆叠312中位置误差的半导体裸片310的厚度变化(诸如与不均匀减薄关联的厚度320的变化)不太敏感。特别地，阶梯台阶对中的给定的阶梯对和顶表面确保给定的半导体裸片的底表面处于正确的位置。
应当注意的是，给定的半导体裸片可以在顶表面上包括焊盘和凸块。因此，可能不可能通过将半导体裸片310面朝下放置在堆叠312上来组装芯片封装(尽管这种布置也将对半导体裸片310的厚度变化不太敏感)，因为这会损坏焊盘和凸块。代替地，组装工具308可以在顶表面上除焊盘和凸块位于其中的位置之外的其它区域中拾取给定的半导体裸片。此外，组装工具308可以确保给定的半导体裸片不接触阶梯台阶对。特别地，组装工具308可以在一个或多个边缘上悬挂半导体裸片310。这些所谓的“翅膀”(诸如翅膀328-1)可以是能够靠着阶梯台阶对中的阶梯被放置的刚性结构。这些阶梯充当控制组装工具308以及因此给定的半导体裸片的顶表面的位置的刚性挡块。这在图4中示出，该图给出了示出用于芯片封装410的组装过程的正视图的图。在图4中，应当注意的是，在半导体裸片310之间存在由粘合层322(诸如胶水)填充并且可以是能够容忍半导体裸片310的厚度变化的故意的间隙，使得它不影响最终的放置精度和位置误差。但是，这种组装技术可能会对堆叠312中半导体裸片310-1的厚度比较敏感，因为这种半导体裸片可以靠在保持阶梯台阶对的夹具上。对这种挑战的一种解决方案是对半导体裸片310-1使用“虚设”裸片，这将允许堆叠312中的第一位置被牺牲，而不会浪费堆叠312中的真实半导体裸片310。在这种情况下，堆叠312的总高度可以被调整，使得堆叠312包括相同数量的真实半导体裸片310。
当附加的半导体裸片310被放置时，组装工具308可以沿阶梯台阶对当中每一个向上和向后移动，每次以在水平方向的偏移量靠在新的共平面阶梯集合上。在堆叠312中放置半导体裸片之前，粘合层可以沉积在堆叠312中前一半导体裸片的顶表面上。应当注意的是，与现有的组装技术相反，这些粘合层可以只需要在组装芯片封装时被设置一次。
如给出示出组装好的芯片封装500的侧视图的框图的图5中所示，组装部件100(图1和图2)可以便于芯片封装500的组装，其中：高带宽斜坡部件512被刚性机械和电耦合到半导体裸片310，由此便于半导体裸片310之间的通信并且向半导体裸片310供电；斜坡部件512被定位在堆叠312的一侧上(图3)；并且斜坡部件512大致平行于沿阶梯台阶112-1的方向514(处于角度516)(图3)，该方向在水平方向118与垂直方向116之间。
回头参照图3，为了便于组装，阶梯台阶对可以大致是阶梯台阶112-1的镜像图像。此外，半导体裸片310集合中给定的半导体裸片可以具有标称厚度320，并且阶梯序列114中给定阶梯的垂直位移(图1和图2)可以大于标称厚度320(或者它可以大于半导体裸片310中任一个的最大厚度)。但是，应当注意的是，在一些实施例中，堆叠312中至少一些半导体裸片310的厚度可以不同(例如，厚度可以在堆叠312中各处变化)。
在示例性实施例中，垂直位移122(图2)可以各自是160μm相对于150±5μm的标称厚度320。(但是，在其它实施例中，厚度320可以在30μm和250μm之间，诸如90μm)。相对于厚度320的这种附加垂直位移可以允许在粘合层322中的粘合剂在组装期间扩散。应当注意的是，对于150μm的标称厚度320，角度516(图5)可以在15和20°之间。一般而言，标称厚度320部分地依赖于堆叠312中半导体裸片310的数量。此外，应当注意的是，粘合层322的标称厚度324可以是10μm。但是，在其它实施例中，粘合层322的厚度可以在堆叠312中沿垂直方向116变化(应当注意的是，粘合层322可以对堆叠312中的垂直位置误差提供公差)。
此外，在阶梯台阶112中给定阶梯处的偏移值(图1和图2)可以与阶梯台阶112-1中关联的偏移值相同或更大。一般而言，偏移值120(图1和图2)和偏移值314可以基于图5中的方向514(或角度516)和用来将斜坡部件512(图5)刚性机械耦合到半导体裸片310集合的焊料(诸如图5中的焊料球518)的标称厚度来确定。应当注意的是，焊料的厚度可以在堆叠中各处大致恒定或者可以在堆叠中各处变化(即，沿着垂直方向116)。
因为组装部件100(图1和图2)降低了芯片封装对半导体裸片310的厚度(诸如厚度320)变化的敏感性，所以组装部件100(图1和图2)可以便于组装半导体裸片310集合，其中半导体裸片310集合各处在垂直方向116中的累积位置误差(即，堆叠312各处半导体裸片在垂直位置中的累积位置误差)小于与半导体裸片310集合和半导体裸片310之间的粘合层322(诸如在150℃在10秒内固化的环氧树脂或胶水)关联的垂直误差的总和。例如，累积的垂直位置误差可以与以下各项关联：半导体裸片310的厚度变化、粘合层322的厚度变化、和/或在至少一些粘合层322中的可选的热扩散材料326(诸如压制石墨纤维)的厚度变化。在一些实施例中，累积的垂直位置误差可以是几微米(诸如小于1μm)，并且可以小至0μm。在示例性实施例中，给定的半导体裸片的垂直位置误差是±10至20μm。在一些实施例中，这可以通过以下来实现：使用组装工具(其可以被耦合到拾取和放置机器)组装芯片封装500(图5)，结合图1和图2中组件部件100上和/或半导体裸片310上的光学对准标记(诸如基准标记)。作为替代或附加地，在一些实施例中，图1和图2中的组装部件100包括机械挡块(诸如利用聚酰亚胺制造的机械挡块)，并且在图5中芯片封装500的组装期间组装工具可以靠着这些机械挡块被向上推，由此便于在水平方向118和/或垂直方向116的期望公差。
在一些实施例中，通过利用提供垂直和/或水平参照相对于组装部件100(图1和图2)校平(level)组装工具，位置误差进一步减小。此外，在图1的一些实施例中，存在与阶梯台阶112对在同一平面中的第三阶梯台阶，但是其从阶梯台阶112对水平偏移。结合阶梯台阶112对，这个第三阶梯台阶可以提供组装工具靠在其上并且组装工具在自校平时可用作参照的三点平面，由此在图5中的斜坡堆叠芯片封装500被组装时提高半导体裸片310的位置精度。
回头参照图5，应当注意的是，为了适应垂直方向116中的机械对准误差，焊料凸块或焊盘(诸如焊盘522-1和/或焊盘522-2)和/或焊料球518的高度和节距可以沿垂直方向116在至少一些半导体裸片310之间变化。例如，距离520(即，焊盘522-1相对于用于半导体裸片510-1的划片线(sawlane)的中心的位置)可以是60μm，并且焊盘522可以各自具有80μm的宽度。此外，焊料球(诸如焊料球518)可以在回流或熔化之前具有120μm的直径，并且在熔化之后具有40和60μm之间的近似厚度。在一些实施例中，两行或更多行焊料球可以刚性地将斜坡部件512耦合到给定的半导体裸片。
图6给出了示出组装好的芯片封装500的顶视图的框图，其中堆叠312(图3)包括四个半导体裸片310。芯片封装500的这个视图示出在一些实施例中焊盘610可以具有非矩形形状。例如，焊盘610可以具有椭圆形形状，诸如80μm宽和120μm长的椭圆形。半导体裸片310和/或斜坡组件512上的这些焊盘形状可以容忍一些水平和/或垂直位置误差。
在一些实施例中，焊盘可以被移动到斜坡部件512的边缘。这可以便于垂直朝向(即，在图5中的角度516可以是0°)。这种构造可以便于存储器模块，其中与输入/输出(I/O)信号线和电力线关联的触点或触垫位于斜坡部件的边缘(而不是沿着“脊柱”)。以这种方式，斜坡部件中的扩散层的数量可以减少。例如，在这种存储器模块中，沿斜坡部件512的边缘可以有60个触点或触垫。
通过在芯片封装500的组装期间允许堆叠过程被参照到图1和图2中的组装部件100(与图3中参照在堆叠312中紧挨着的前一半导体裸片相反)，这种组装部件可以有效地降低与芯片封装500中部件的尺寸和部件的厚度机械变化关联的水平和/或垂直位置误差。例如，半导体裸片310的垂直位置误差可以各自小于±20μm。因而，图1和图2中的组装部件100可以便于芯片封装500的高度准确和高成品率组装。此外，因为这种组件部件还便于高容量和低成本制造技术(诸如拾取和放置机器)的使用，所以它可以大大降低芯片封装500的成本。
此外，组装低成本、高成品率芯片封装的能力可以便于高性能设备。例如，在一些实施例中，斜坡堆叠芯片封装(诸如芯片封装500)被包括在双列直插存储器模块中。例如，在斜坡堆叠芯片封装中可以有高达80个存储器装置(诸如动态随机存取存储器或另一类型的存储器存储装置)。如果需要，则“坏的”或故障的存储设备可以被禁用。因而，可以使用(80个当中的)72个存储器装置。此外，这种构造可以暴露存储器模块中存储器装置的全部带宽，使得在访问存储器装置中的任一个时存在很少或没有等待时间(latency)延迟。
作为替代，双列直插存储器模块可以包括多个场，每个场可以包括斜坡堆叠芯片封装。例如，在双列直插存储器模块中可以存在四个斜坡堆叠芯片封装(其中每个包括9个存储器装置)。
在一些实施例中，这些双列直插存储器模块(其可以包括一个或多个斜坡堆叠芯片封装)当中一个或多个可以被耦合到处理器。例如，处理器可以利用电容耦合信号的电容性接近性通信(PxC)耦合到一个或多个双列直插存储器模块。该处理器又可以利用C4焊料球被安装在基板上。
在一些实施例中，组装工具具有倾斜顺应性和垂直移动的能力，
同时不允许在半导体裸片的平面内的运动。作为替代，可以使用球窝接头(诸如，在杆的端部的硬球体位于杯状物中)。这种球窝接头可以提供允许关于所有三个旋转轴的一些旋转但不允许平移的接头。对于组装工具，杆可以是附连到拾取和放置机器的安装轴，并且杯状物可以放置在拾取表面内，使得枢转点尽可能接近半导体裸片。这种布置可以允许拾取和放置机器的表面倾斜，以接触(meet)组装工具，但这一布置可能不支持平移。应当注意的是，球窝接头在垂直方向可以不具有任何顺应性。但是，球窝接头可以允许沿所有三个旋转轴的旋转，使得组装工具可以绕安装轴旋转。还有另一种可能性是球面支承，它类似于球窝接头，不同之处在于代替在拾取和放置机器的表面上的杯状物中俘获球，拾取和放置机器的整个表面可以在更大的球面内。这个球面可以包括在甚至更大的球面内，这可以允许两个球面相对于彼此旋转。就像对于球窝接头那样，球面支承允许组装工具沿所有三个旋转轴的期望旋转，但不允许不期望的平移。
现在描述组装技术的实施例。图7给出了示出用于利用组装部件100(图1和图2)组装芯片封装的方法700的流程图。在这种方法中，粘合剂施加到斜坡堆叠芯片封装中的半导体裸片的顶表面(操作710)，在该斜坡堆叠芯片封装中，半导体裸片集合布置在垂直堆叠中，其中垂直堆叠中的给定的半导体裸片在半导体裸片集合的平面中从相邻的半导体裸片偏移，以定义阶梯台阶。然后，利用组装工具，第二半导体裸片在第二半导体裸片的顶表面被拾取(操作712)。接下来，第二半导体裸片的底表面被放置在所述半导体裸片的顶表面上的粘合剂上，同时组装工具的垂直位置由组装部件中的给定阶梯限制(操作714)，该组装部件具有布置在斜坡堆叠芯片封装的两侧上的阶梯台阶对，其中该阶梯台阶对中的阶梯提供垂直参照位置。
在方法700的一些实施例中，可以存在附加的或更少的操作。例如，堆叠可以在包括半导体裸片的子集的片段中被组装，其随后被组装成完整的堆叠。而且，斜坡部件可以刚性地机械耦合到所述半导体裸片和第二半导体裸片，其中斜坡部件被定位在垂直堆叠的一侧上，并且其中该斜坡部件大致平行于沿阶梯台阶的方向，该方向在水平方向与垂直方向之间。
此外，将斜坡部件刚性机械耦合到所述半导体裸片和第二半导体裸片可以涉及在斜坡部件和/或所述半导体裸片和第二半导体裸片上熔化焊料。当使焊料回流时，斜坡部件可以被放置在堆叠上或者反过来。这可以允许斜坡部件(或半导体裸片的堆叠)的重量帮助克服焊料的表面张力。
应当注意的是，当将斜坡部件刚性机械耦合到所述半导体裸片和第二半导体裸片时，可以在垂直方向施加压缩力。这可以确保组装好的芯片封装具有期望的高度。在一些实施例中，沿斜坡部件的法线施加压缩力。这些压缩力当中任意一个可以改善堆叠内的热传递，例如，通过填充或减少芯片封装中部件之间的间隙。
此外，图7中操作的次序可以改变，和/或两个或更多个操作可被组合成单个操作。
应当注意的是，组装部件100(图1和图2)和芯片封装500(图5和图6)可以包括更少的部件或附加的部件。例如，在斜坡堆叠芯片封装中的半导体裸片的堆叠中可以存在定义的间断，诸如通过对于斜坡部件上的一个或多个半导体裸片不包括焊盘。而且，虽然这些设备和系统被示为具有多个分立的项，但是这些实施例意在作为可以存在的各种特征的功能描述而不是本文所述实施例的结构示意图。因此，在这些实施例中，两个或更多个部件可以被组合成单个部件，和/或一个或多个部件的位置可以改变。
虽然前述实施例在芯片封装中使用半导体裸片(诸如硅)，但是在其它实施例中，可以使用与半导体不同的材料作为在这些芯片当中的一个或多个芯片中的基板材料。但是，在其中使用硅的实施例中，半导体裸片310(图3-图6)可以利用标准的硅工艺来制作。这些半导体裸片可以提供支持逻辑和/或存储器功能的硅区域。
此外，在图5和图6中，斜坡部件512可以是无源部件，诸如具有金属迹线以便电耦合到半导体裸片310的塑料基板。例如，斜坡部件512可以利用注模塑料来制作。作为替代，斜坡部件512可以是具有光刻定义的电线或信号线的另一种半导体裸片。在斜坡部件512包括半导体裸片的实施例中，可以包括有源设备(诸如限制放大器)以减少信号线之间的串扰。此外，可以利用差分信令来减少在有源或无源斜坡部件512的任意一个当中的串扰。
在一些实施例中，斜坡部件512包括经由焊料球(诸如焊料球518)在半导体裸片310之间往返运送(shuttle)数据和功率信号的晶体管和电线。例如，斜坡部件512可以包括高电压信号。利用降压型稳压器(诸如电容到电容降压型稳压器)以及耦合到半导体裸片310的电容和/或电感器分立部件，这些信号可以被降压以在半导体裸片310上使用。
此外，斜坡部件512可以包括用于存储器的缓冲区或逻辑芯片，和/或到(一个或多个)外部设备和/或(一个或多个)系统的I/O连接器。例如，I/O连接器可以包括以下中的一个或多个以用于耦合到外部设备：球键合、电线键合、边缘连接器和/或PxC连接器。在一些实施例中，这些I/O连接器可以在斜坡部件512的背面，并且斜坡部件512可以包括将I/O连接器耦合到焊盘(诸如焊盘522-2)的一个或多个硅通孔(TSV)。
在一些实施例中，芯片封装500中的斜坡部件512和半导体裸片310安装在可选的基板(诸如印刷电路板或半导体裸片)上。这种可选的基板可以包括球键合、电线键合、边缘连接器和/或PxC连接器以用于耦合到外部设备。如果这些I/O连接器在可选的基板的背面上，则可选的基板可以包括一个或更多TSV。
虽然在前面的实施例中使用焊料球作为斜坡部件512和半导体裸片310的电气和机械耦合的说明，但是在其它实施例中，这些部件可以利用其它技术电气和机械耦合，诸如：微弹簧、微球(在如下所述的球坑构造中)、和/或各向异性膜(诸如各向异性弹性体膜，其有时被称为“各向异性导电膜”)。
在芯片封装中的部件利用电磁耦合的信号的PxC(诸如斜坡部件512和半导体裸片310之间、斜坡部件512和外部设备之间、斜坡部件512和可选的基板之间、可选的基板和半导体裸片310之间和/或可选的基板和外部设备之间的PxC)进行通信的实施例中，PxC可以包括：电容性耦合信号的通信(其被称为“电接近性通信”)、光学耦合信号的通信(其被称为“光学接近性通信”)、电磁耦合信号的通信(其被称为“电磁接近性通信”)、电感耦合信号的通信、和/或导电耦合信号的通信。
一般而言，结果产生的电触点的阻抗可以是导电的和/或电容性的，即，可以具有包括同相分量和/或异相分量的复数阻抗。无论电触点机制(诸如焊料、微弹簧、各向异性层，等等)如何，如果与触点关联的阻抗是导电的，则可以在芯片封装500的部件中使用常规的发送和接收I/O电路。但是，对于具有复数(并且有可能是可变的)阻抗的触点，发送和接收I/O电路可以包括于2009年4月17日递交的、RobertJ.Drost等人的标题为“ReceiveCircuitforConnectorswithVariableComplexImpedance”、代理人案号为SUN09-0285的美国专利申请12/425,871中所描述的一个或多个实施例，该申请的内容通过引用被结合于此。
应当注意的是，当面对较低的半导体芯片成品率或在封装和组装之前广泛测试的高费用时，允许一些返工的封装技术是更成本有效的。因此，在半导体裸片310和斜坡部件512之间的机械和/或电耦合可重新配对的实施例中，可以通过允许返工(诸如更换在组装、测试或老化(burn-in)期间识别出的坏芯片)来增加芯片封装500的成品率。在这方面，可重新配对的机械或电耦合应当被理解为无需返工或加热(诸如利用焊料)就可以重复地(即，两次或更多次)建立和中断的机械或电耦合。在一些实施例中，可重新配对的机械或电耦合涉及被设计为彼此耦合的公部件和母部件(诸如卡扣在一起的部件)。
虽然图5和图6示出了芯片封装500的特定构造，但是在利用或不利用组装部件100(图1和图2)的情况下，可以使用多种技术和构造来实现机械对准和组装。例如，可以利用球坑对准技术(并且更一般地，阳性特征和阴性特征对准技术)来相对于彼此定位半导体裸片310和/或斜坡部件512。特别地，球可以被定位到蚀刻坑中，以相对地对准部件，部件诸如堆叠312中的半导体裸片310(图3)。阳性特征的其它例子包括半球形凸块。但是，可以使用在芯片封装500中的部件上的机械锁定阳性表面特征和阴性表面特征的任意组合来对准和/或组装芯片封装500。
参照图3，如先前在一些实施例中指出的，可选的热扩散材料326(并且更一般地，半导体裸片310之间具有高热导率的中间材料)可以帮助除去在一个或多个半导体裸片310和/或斜坡部件512(图5和图6)上的电路操作期间产生的热量。这种热管理可以包括以下热路径中的任一个：半导体裸片310的平面中的第一热路径；粘合层322的平面中的第二热路径；和/或可选的热扩散材料326的平面中的第三热路径。特别地，可以经由在芯片封装的边缘的热耦合彼此独立地管理与这些热路径关联的热通量。应当注意的是，这种热管理可以包括使用相变冷却、浸渍冷却、和/或冷却板。还应当注意的是，与第一热路径关联的、通过在芯片封装的边缘处的横截面扩散的热通量是标称厚度320的函数。因此，在具有大于或小于半导体裸片310的标称厚度的芯片封装中，热管理可以不同。
应当注意的是，在芯片封装500(图5和图6)的至少一部分周围可以有可选的封装。此外，芯片封装500(图5和图6)中的部件之间的空气间隙可以填充不足，以改善散热。这可以通过减小图5中的角度516来促进，即，半导体裸片310可以朝垂直方向116更倾斜(tip)。
前面的描述是为了使本领域技术人员能够制造和使用本公开内容，并且是在特定申请及其需求的语境下提供的。而且，仅仅是为了说明和描述的目的而给出前面对本公开内容的实施例的描述。它们不是详尽的也不是要将本公开内容限制到所公开的形式。因此，在不背离本公开内容的精神和范围的情况下，对本领域技术人员来说许多修改和变化将是显而易见的，并且本文定义的通用原理可以适用于其它实施例和申请。此外，前述实施例的讨论不是要限制本公开内容。因此，
本公开内容并非意在被局限于所示出的实施例，而是要符合与本文公开的原理和特征一致的最广范围。

Claims (20)

1.一种组装部件，包括：
具有垂直的阶梯堆叠的阶梯台阶对，其中给定的阶梯在阶梯的平面内从相邻的阶梯偏移以定义所述阶梯台阶对，其中所述阶梯台阶对中的阶梯被配置为提供在斜坡堆叠芯片封装的组装期间限制组装工具的垂直位置的垂直参照位置；
其中所述斜坡堆叠芯片封装中的半导体裸片集合布置在垂直堆叠中，其中给定的半导体裸片在所述半导体裸片集合的平面内从相邻的半导体裸片偏移以定义阶梯台阶；及
其中，在所述斜坡堆叠芯片封装的组装期间，当所述阶梯台阶对限制所述组装工具的垂直位置时，所述组装工具机械耦合到所述给定的半导体裸片的顶表面并且所述给定的半导体裸片的底表面机械耦合到所述斜坡堆叠芯片封装。
2.如权利要求1所述的组装部件，其中所述半导体裸片集合包括N个半导体裸片；及
其中所述斜坡堆叠芯片封装中所述半导体裸片集合沿垂直堆叠在垂直方向的位置误差独立于在所述斜坡堆叠芯片封装中的垂直位置。
3.如权利要求2所述的组装部件，其中N大于40。
4.如权利要求1所述的组装部件，其中所述位置误差各自小于±20μm。
5.如权利要求1所述的组装部件，其中所述组装部件便于所述斜坡堆叠芯片封装的组装，其中所述半导体裸片集合沿垂直堆叠在垂直方向上的累积位置误差小于与所述半导体裸片集合和半导体裸片之间的粘合层关联的位置误差的总和。
6.如权利要求5所述的组装部件，其中所述累积位置误差以下之一相关联：半导体裸片的厚度变化和粘合层的厚度变化。
7.如权利要求1所述的组装部件，其中所述给定的半导体裸片包括顶表面上的焊盘和凸块；及
其中所述组装工具在顶表面上除焊盘和凸块所处位置之外的区域中拾取所述给定的半导体裸片。
8.如权利要求1所述的组装部件，其中所述阶梯台阶是所述阶梯台阶对的镜像图像。
9.如权利要求1所述的组装部件，其中所述给定的半导体裸片具有标称厚度；及
其中所述阶梯台阶中给定阶梯的垂直位移大于所述标称厚度。
10.如权利要求1所述的组装部件，其中所述组装部件便于斜坡部件刚性机械耦合到所述斜坡堆叠芯片封装，
其中所述斜坡部件被定位在垂直堆叠的一侧上，及
其中所述斜坡部件大致平行于沿阶梯台阶的方向，所述方向在所述半导体裸片集合的平面中的水平方向与沿垂直堆叠的垂直方向之间。
11.一种用于组装斜坡堆叠芯片封装的方法，其中所述方法包括：
将粘合剂施加到所述斜坡堆叠芯片封装中的半导体裸片的顶表面，在所述斜坡堆叠芯片封装中，半导体裸片集合布置在垂直堆叠中，其中在垂直堆叠中的给定的半导体裸片在所述半导体裸片集合的平面中从相邻的半导体裸片偏移以定义阶梯台阶；
利用组装工具，在第二半导体裸片的顶表面上拾取所述第二半导体裸片；及
将所述第二半导体裸片的底表面放置在所述半导体裸片的顶表面上的粘合剂上，同时所述组装工具的垂直位置由组装部件中的给定阶梯限制，所述组装部件具有布置在所述斜坡堆叠芯片封装的两侧上的阶梯台阶对，其中所述阶梯台阶对中的阶梯提供垂直参照位置。
12.如权利要求11所述的方法，其中对所述半导体裸片集合中的附加半导体裸片重复执行施加操作、拾取操作和放置操作，以组装所述斜坡堆叠芯片封装；及
其中在组装所述斜坡堆叠芯片封装时，所述组装工具的垂直位置由所述阶梯台阶对中的阶梯限制。
13.如权利要求12所述的方法，其中所述半导体裸片集合包括N个半导体裸片；及
其中所述斜坡堆叠芯片封装中所述半导体裸片集合沿垂直堆叠在垂直方向的位置误差独立于在所述斜坡堆叠芯片封装中的垂直位置。
14.如权利要求13所述的方法，其中N大于40。
15.如权利要求13所述的方法，其中所述位置误差各自小于±20μm。
16.如权利要求11所述的方法，其中所述组装部件便于所述斜坡堆叠芯片封装的组装，其中所述半导体裸片集合沿垂直堆叠在垂直方向上的累积位置误差小于与所述半导体裸片集合和半导体裸片之间的粘合层关联的位置误差的总和。
17.如权利要求11所述的方法，其中所述半导体裸片包括顶表面上的焊盘和凸块；及
其中所述组装工具在顶表面上除焊盘和凸块所处位置之外的区域中拾取所述半导体裸片。
18.如权利要求11所述的方法，其中所述阶梯台阶是所述阶梯台阶对的镜像图像。
19.如权利要求11所述的方法，其中所述给定的半导体裸片具有标称厚度；及
其中所述阶梯台阶中给定阶梯的垂直位移大于所述标称厚度。
20.如权利要求11所述的方法，其中所述组装部件便于斜坡式部件刚性机械耦合到所述斜坡堆叠芯片封装，
其中所述斜坡部件被定位在垂直堆叠的一侧上，及
其中所述斜坡部件大致平行于沿阶梯台阶的方向，所述方向在所述半导体裸片集合的平面中的水平方向与沿垂直堆叠的垂直方向之间。
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