TW201526122A - 用於控制層疊晶片的位置之技術 - Google Patents

用於控制層疊晶片的位置之技術 Download PDF

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Publication number
TW201526122A
TW201526122A TW103134753A TW103134753A TW201526122A TW 201526122 A TW201526122 A TW 201526122A TW 103134753 A TW103134753 A TW 103134753A TW 103134753 A TW103134753 A TW 103134753A TW 201526122 A TW201526122 A TW 201526122A
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Taiwan
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assembly
semiconductor die
vertical
semiconductor
package
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TW103134753A
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English (en)
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TWI627682B (zh
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Michael H S Dayringer
R David Hopkins
Alex Chow
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Oracle Int Corp
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Abstract

描述一種組裝組件及使用該組裝組件組裝晶片封裝的一種技術。此晶片封裝包括在垂直方向上以疊層配置的半導體晶粒組，其在水平方向上彼此偏移以在該垂直疊層的一側界定階梯。再者，該晶片封裝可使用該組裝組件組裝。特別係該組裝組件可包括幾乎反映該晶片封裝的該階梯並提供垂直位置參考的一對階梯，該等垂直位置參考在該晶片封裝的組裝期間用於將該半導體晶粒組放置在該垂直疊層中的組裝工具。

Description

用於控制層疊晶片的位置之技術
本揭示發明通常相關於製造半導體晶片封裝的處理。更具體地說，本揭示發明相關於用於組裝晶片封裝的組裝組件及關聯技術，其包括晶片群組在垂直層疊中彼此偏移以界定階梯。
相較於連接至印刷電路板的習知獨立封裝晶片，包括層疊半導體晶片或晶粒的晶片封裝能提供顯著更高的效能。此等晶片封裝也提供特定優點，諸如，下列能力：在層疊中的不同晶片上使用不同處理、組合更高密度邏輯及記憶體、及使用較少電力轉移資料。例如，實作動態隨機存取記憶體(DRAM)之晶片的層疊能在基底晶片中使用高金屬層數、高效能邏輯處理以實作輸入/輸出(I/O)及控制器功能、並能將一組低金屬層數、DRAM特殊化處理晶片用於層疊的其餘部分。以此方式，晶片的組合組可比下列各者具有更佳效能及更低成本：包括使用DRAM製程製造之I/O及控制器功能的單一晶片；包括使用邏輯 製程製造之記憶體電路的單一晶片；及/或企圖使用單一製程產生邏輯及記憶體實體結構二者。
然而，組裝包括層疊半導體晶片的晶片封裝能係困難的。特別係既存組裝技術可消耗時間並可具有低良率(其可增加晶片封裝的成本)。例如，在許多既存組裝技術中，在半導體晶片之層疊上的總垂直位置誤差係與各半導體晶片關聯之垂直位置誤差的和。因此，包括多個半導體晶片之層疊的總垂直位置誤差可變得驚人的大。此可導致嚴格的製造容差以降低個別垂直位置誤差(其能增加半導體晶片的成本)及/或可限制能組裝在層疊中的半導體晶片數(其可限制效能)。
因此，需要用於組裝晶片層疊而沒有上述問題的技術。
本揭示發明的一實施例提供包括具有階之垂直層疊的一對階梯的組裝組件，其中指定階在該等階的平面上從相鄰階偏移以界定該對階梯。該對階梯中的梯提供在半導體晶粒組以垂直層疊配置之斜層疊晶片封裝的組裝期間提供限制組裝工具之垂直位置的垂直基準位置。再者，該斜層疊晶片封裝中的指定半導體晶粒在該半導體晶粒組的平面上從相鄰半導體晶粒偏移以界定階梯。在該斜層疊晶片封裝的組裝期間，在該對階梯限制該組裝工具的垂直位置的同時，將該組裝工具機械耦接至該指定半導體 晶粒的頂表面，並將該指定半導體晶粒的底表面機械耦接至該斜層疊晶片封裝。
須注意該半導體晶粒組可包括N個半導體晶粒(諸如，多於40個半導體晶粒)，且該斜層疊晶片封裝中之該半導體晶粒組在沿著該垂直層疊之垂直方向上的位置誤差可與在該斜層疊晶片封裝中的垂直位置無關。例如，該等位置誤差各者可少於±20μm。另外，該組裝組件可促進該斜層疊晶片封裝的組裝，該斜層疊晶片封裝具有少於與該半導體晶粒組及該等半導體晶粒之間的黏合層關聯之位置誤差的和之在沿著該垂直層疊的垂直方向上之該半導體晶粒組上方的累積位置誤差。該累積位置誤差可與下列一者關聯：該等半導體晶粒的厚度變化及/或該等黏合層的厚度變化。
此外，該指定半導體晶粒可包括在頂表面上的焊墊及焊點凸塊，且該組裝工具可在該頂表面之該等焊墊及焊點凸塊所在位置以外的區域中拾取該指定半導體晶粒。
在部分實施例中，該階梯係該對階梯的鏡像。
須注意該指定半導體晶粒可具有額定厚度，且該階梯中的該指定階的垂直移位可大於該額定厚度。
再者，該組裝組件可促進斜坡組件對該斜層疊晶片封裝的剛性機械耦接。可將該斜坡組件放置在該垂直層疊的一側上，並可幾乎平行於沿著該階梯的方向，其 在該半導體晶粒組之平面的水平方向及沿著該垂直層疊的垂直方向之間。
另一實施例提供用於組裝該斜層疊晶片封裝的方法。在此方法期間，將黏合劑施加至在其中該半導體晶粒組以垂直層疊配置之該斜層疊晶片封裝中的半導體晶粒的頂表面，其中該垂直層疊中的該指定半導體晶粒在該半導體晶粒組的平面上從該相鄰半導體晶粒偏移以界定該階梯。然後，使用組裝工具，在第二半導體晶粒的頂表面上將第二半導體晶粒拾起。其次，將該第二半導體晶粒的底表面放置在該半導體晶粒之該頂表面上的該黏合劑上，同時藉由具有配置在該斜層疊晶片封裝之任一側上的該對階梯之該組裝組件中的指定階限制該組裝工具的該垂直位置，其中該對階梯中的階提供垂直基準位置。
須注意該施加、拾取、及放置操作對該半導體晶粒組中的額外半導體晶粒重複以組裝該斜層疊晶片封裝，且當組裝該斜層疊晶片封裝時，藉由該對階梯中的該等階限制該組裝工具的垂直位置。
100‧‧‧組裝組件
112-1‧‧‧階梯
114、114-1、114-N‧‧‧梯
116‧‧‧垂直方向
118‧‧‧水平方向
120、314‧‧‧偏移值
122‧‧‧垂直位移
308‧‧‧組裝工具
310、310-1‧‧‧半導體晶粒
312‧‧‧層疊
320‧‧‧厚度
322‧‧‧黏合層
324‧‧‧額定厚度
326‧‧‧散熱材料
328-1‧‧‧翼
410、500‧‧‧晶片封裝
512‧‧‧斜坡組件
514‧‧‧方向
516‧‧‧角
518‧‧‧焊球
520‧‧‧距離
522-1、522-2、610‧‧‧焊墊
700‧‧‧方法
圖1係描繪根據本揭示發明的實施例之用於組裝晶片封裝的組裝組件之頂視圖的方塊圖。
圖2係描繪根據本揭示發明的實施例之圖1的組裝組件之側視圖的方塊圖。
圖3係描繪根據本揭示發明的實施例之使用 圖1及2的組裝組件之晶片封裝的組裝之側視圖的方塊圖。
圖4係描繪根據本揭示發明的實施例之使用圖1及2的組裝組件之晶片封裝的組裝之前視圖的圖式。
圖5係描繪根據本揭示發明的實施例之經組裝晶片封裝的側視圖的方塊圖。
圖6係描繪根據本揭示發明的實施例之經組裝晶片封裝的頂視圖的方塊圖。
圖7係描繪根據本揭示發明的實施例之使用圖1及2的組裝組件組裝晶片封裝之方法的流程圖。
須注意在該等圖式各處，相似參考數字參考至對應部分。再者，相同部分的多個實例可能以藉由破折號與實例數字分隔的共同前置數字指定。
描述一種組裝組件及使用該組裝組件組裝晶片封裝的一種方法的實施例。此晶片封裝包括在垂直方向上以疊層配置的半導體晶粒組，其在水平方向上彼此偏移以在該垂直疊層的一側界定階梯。再者，該晶片封裝包括放置在該垂直層疊之一側上的斜坡組件，其幾乎平行於沿著該階梯的方向。此晶片封裝可使用該組裝組件組裝。特別係該組裝組件可包括幾乎反映該晶片封裝的該階梯並提供垂直位置參考的一對階梯，該等垂直位置參考在該晶片封裝的組裝期間用於將該半導體晶粒組放置在該垂直疊層 中的組裝工具。
藉由促進晶片封裝的組裝，組裝組件及組裝技術可致能高效能晶片封裝的低成本、高通量製造(諸如，具有高帶寬互連的晶片封裝)。特別係此等實施例可在晶片封裝的組裝期間促進降低機器誤差，及更容忍在晶片封裝中之組件的尺寸及位置上之機械變化的晶片封裝。例如，使用此等實施例，該組半導體晶粒可用少於與半導體晶粒及半導體晶粒間之黏合層關聯的垂直位置誤差(其有時稱為「垂直誤差」)之層疊上之總垂直位置誤差組裝在晶片封裝中。此可藉由獨立地參考將晶片封裝中的各半導體晶粒放置至組裝組件的組裝工具而實現(取代在組裝期間將層疊中的指定半導體晶粒機械地參考至緊接在前的半導體晶粒)。因此，組裝組件及關聯組裝技術可防止個別垂直位置誤差混合。
現在描述組裝組件及晶片封裝的實施例。圖1呈現描繪能在晶片封裝(諸如，圖5及6中的晶片封裝500，其有時稱為「斜層疊晶片封裝」)的組裝期間用於放置及固定半導體晶粒(或晶片)之組裝組件100(其有時稱為「製造夾具」)的頂視圖的方塊圖。此組裝組件包括一對階梯112，其可使用研磨機製造。此等階梯可在正受組裝之斜層疊晶片封裝的任一側上。再者，指定階梯(諸如，階梯112-1)包括在垂直方向116上的一系列梯114(圖2)。須注意在梯114-1之後的各梯與在梯114序列中之緊接在前的梯以偏移值120的關聯一值在水平方向118上偏 移。此外，偏移值120各者可對梯114的序列具有幾乎不變的值或可隨梯114的序列變化(亦即，該對階梯112中之不同梯114的偏移值可不同)。
另外，如圖2所示，其呈現描繪組裝組件100之側視圖的方塊圖，與梯114之序列關聯的垂直位移122(梯114-1或梯114-n之垂直位移以外的垂直位移)各者可具有幾乎不變的值或可隨梯114的序列變化(亦即，階梯112中之不同梯114的垂直位移可不同)。
如圖3所示，其呈現描繪使用此組裝組件之晶片封裝的組裝之側視圖的方塊圖，該對階梯可組態成與放置一組半導體晶粒310(例如，50個半導體晶粒310)的組裝工具308相配，使得該組半導體晶粒310在垂直方向116上配置在層疊312中。須注意垂直方向116實質垂直於層疊312中的半導體晶粒310-1(且因此，具有水平區域118)。另外，在半導體晶粒310-1之後的各半導體晶粒可與層疊312中之緊接在前的半導體晶粒以偏移值314的關聯一者在水平方向118上偏移，因此將階梯界定在層疊312的一側。此等偏移值可對該組半導體晶粒310具有幾乎不變的值或隨該組半導體晶粒310改變(亦即，階梯112-1中之不同梯的偏移值可不同)。
在晶片封裝的組裝期間，在該對階梯限制與指定梯114對相配之組裝工具308的垂直位置的同時(圖1及2)，將組裝工具308機械地耦接至指定半導體晶粒(例如，該指定半導體晶粒可用真空保持在適當位置)的頂表 面，並將指定半導體晶粒的底表面機械地耦接至晶片封裝(例如，使用黏合劑，諸如，膠)。與將指定半導體晶粒的底表面使用為基準的既存組裝技術不同，藉由將頂表面使用為基準，此組裝技術可對能在層疊312中導致位置誤差的半導體晶粒310之厚度上的變化(諸如，與不均勻薄化關聯之在厚度320上的變化)較不敏感。特別係在該對階梯中的指定梯對及該頂表面確保指定半導體晶粒的底表面在正確位置上。
須注意該指定半導體晶粒可包括在頂表面上的焊墊及焊點凸塊。因此，因為會損壞焊墊及焊點凸塊，可能不能藉由將半導體晶粒310面向下的放置在層疊312上而組裝晶片封裝(雖然此配置也會對半導體晶粒310的厚度變化較不敏感)。取而代之的，組裝工具308可在該頂表面之該等焊墊及焊點凸塊所在位置以外的區域中拾取該指定半導體晶粒。另外，組裝工具308可確保指定半導體晶粒不接觸該對階梯。特別係組裝工具308可將半導體晶粒310懸垂在一或多個邊緣上。此等所謂的「翼」(諸如翼328-1)可係能靠著該對階梯中的梯放置的剛性結構。此等梯的作用如同控制組裝工具308之位置，且因此控制指定半導體晶粒之頂表面的剛性止動器。此描繪於圖4中，其呈現描繪用於晶片封裝410的組裝處理之前視圖的圖式。在圖4中，須注意可能故意將間隙留在以黏合層322(諸如，膠)填充之半導體晶粒310之間，且其可能容許在半導體晶粒310之厚度上的變化，使得其不影響最終 放置精確度或位置誤差。然而，因為此半導體晶粒可停放在保持該對階梯的夾具上，此組裝技術可對層疊312中的半導體晶粒310-1的厚度敏感。此項挑戰的一個解決方案係將「虛擬」晶粒用為半導體晶粒310-1，其會容許犧牲層疊312中的第一位置而不浪費層疊312中的實際半導體晶粒310。在此情形中，可調整層疊312的總高度，使得層疊312包括相同數量的實際半導體晶粒310。
當放置額外半導體晶粒310時，組裝工具308可沿著該對階梯各者上下移動，每次在水平方向上以該偏移停留在新的一組共平面梯上。在將半導體晶粒放置在層疊312中之前，黏合層可沈積在層疊312中的先前半導體晶粒的頂表面上。須注意，與既存組裝技術相反，當組裝晶片封裝時，此等黏合層可僅需要設定一次。
如圖5所示，其呈現描繪經組裝晶片封裝500之側視圖的方塊圖，組裝組件100(圖1及2)可促進晶片封裝500的組裝，其中：將高帶寬斜坡組件512剛性地機械及電耦接至半導體晶粒310，因此促進半導體晶粒310之間的通訊並供應電力至半導體晶粒310；將斜坡組件512放置在層疊312的一側上(圖3)；並斜坡組件512幾乎平行於沿著階梯112-1(圖3)的方向514(以角度516)，其在水平方向118及垂直方向116之間。
參考回圖3，為促進組裝，該對階梯可幾乎係階梯112-1的鏡像。再者，該組半導體晶粒310中的指定半導體晶粒可具有額定厚度320，且在梯114之序列中的 指定梯的垂直位移(圖1及2)可大於額定厚度320(或其可大於任何半導體晶粒310的最大厚度)。然而，須注意在部分實施例中，層疊312中的至少部分半導體晶粒310的厚度可不同(例如，厚度可在層疊312上變化)。
在範例實施例中，垂直位移122(圖2)各者可係160μm對150±5μm的額定厚度320。(然而，在其他實施例中，厚度320可在30及250μm之間，諸如，90μm)。相對於厚度320的此額外垂直位移可容許黏合層322中的黏合劑在組裝期間散開。須注意針對150μm的額定厚度320，角516(圖5)可在15及20°之間。通常，額定厚度320部分地相依於層疊312中的半導體晶粒310的數量。另外，須注意黏合層322的額定厚度324可係10μm。然而，在其他實施例中，黏合層322的厚度可沿著層疊312中的垂直方向116改變。(須注意黏合層322可對層疊312中的垂直位置誤差提供容差)。
另外，在該對階梯112中之指定梯的偏移值(圖1及2)可相同於或大於階梯112-1中的關聯偏移值。通常，偏移值120(圖1及2)及偏移值314可基於圖5中的方向514(或角516)及用於將斜坡組件512(圖5)剛性地機械耦接至該組半導體晶粒310之焊料(諸如，圖5中的焊球518)的額定厚度決定。須注意焊料的厚度在層疊上可幾乎係固定的或可在層疊上變化(亦即，沿著垂直方向116)。
因為組裝組件100(圖1及2)降低晶片封裝對 半導體晶粒310之厚度(諸如，厚度320)變化的靈敏度，組裝組件100(圖1及2)可用少於與該組半導體晶粒310及半導體晶粒310之間的黏合層322(諸如，在150C以10s固化的環氧樹脂或膠)關聯之垂直誤差的和之該組半導體晶粒310在垂直方向116上的累積位置誤差(亦即，層疊312上方之半導體晶粒之垂直位置中的累積位置誤差)促進該組半導體晶粒310的組裝。例如，累積垂直位置誤差可與下列各者關聯：半導體晶粒310的厚度變化、黏合層322的厚度變化、及/或在至少部分黏合層322中之選擇性散熱材料326(諸如，壓製石墨纖維)的厚度變化。在部分實施例中，累積垂直位置誤差可係數微米(諸如，少於1μm)，且可小至0μm。在範例實施例中，指定半導體晶粒的垂直位置誤差係±10至20μm。在部分實施例中，此可藉由使用組裝工具(其可耦接至取放機器)以將晶片封裝500(圖5)連同光學調正標示(諸如，基準標示)組裝在圖1及2中的組裝組件100及/或半導體晶粒310上而完成。或者或另外地，在部分實施例中，圖1及2中的組裝組件100包括機械止動器，諸如，使用聚醯亞胺製造的機械止動器，且在圖5中之晶片封裝500的組裝期間，可靠著此等機械止動器將該組裝工具推高，因此促進在水平方向118及/或垂直方向116上的期望容差。
在部分實施例中，位置誤差更藉由使用提供垂直及/或水平基準的區域定位系統使組裝工具相對於組裝組件100(圖1及2)對準而更減少。此外，在圖1的部 分實施例中，有與該對階梯112在相同平面中的第三階梯，但其水平地自該對階梯112偏移。結合該對階梯112，當組裝圖5中的斜層疊晶片封裝500時，此第三階梯可提供將組裝工具停放於其上且當組裝工具自對準時可將其使用為基準的三點平面，從而改善半導體晶粒310的位置精確性。
參考回圖5，須注意為容納垂直方向116上的機械對準誤差，焊點凸塊或焊墊(諸如，焊墊522-1及/或焊墊522-2)及/或焊球518的高度及間距可沿著垂直方向116在至少部分的半導體晶粒310之間改變。例如，距離520(亦即，焊墊522-1相對於半導體晶粒510-1之鋸道中心的位置)可係60μm且焊墊522各者可具有80μm寬度。此外，在回流或熔解之前，焊球(諸如，焊球518)可具有120μm的直徑，且在熔解之後，具有約在40及60μm之間的厚度。在部分實施例中，二或多列的焊球可將斜坡組件512剛性地耦接至指定半導體晶粒。
圖6呈現描繪在其中層疊312(圖3)包括四個半導體晶粒310的經組裝晶片封裝500之頂視圖的方塊圖。晶片封裝500的此視圖描繪在部分實施例中，焊墊610可具有非矩形形狀。例如，焊墊610可具有框形，諸如，80μm寬及120μm長的框。半導體晶粒310及/或斜坡組件512上的此等焊墊形狀可容許一些水平及/或垂直位置誤差。
在部分實施例中，能將焊墊移至斜坡組件512 的邊緣。此可促進垂直定向(亦即，圖5中的角516可係0°)。此組態可促進在其中與輸入/輸出(I/O)訊號線及電源線關聯的接點及焊墊在斜坡組件之邊緣的記憶體模組(取代在「脊」下)。以此方式，可減少斜坡組件中的許多擴散層。例如，在此記憶體模組中，沿著斜坡組件512的邊緣可有60個接點或焊墊。
藉由容許層疊處理在晶片封裝500的組裝期間參考至圖1及2中的組裝組件100(與圖3中的層疊312中之緊接在前的半導體晶粒相對)，此組裝組件能有效降低與在晶片封裝500中的組件之尺寸及厚度上的機械變化關聯的水平及/或垂直位置誤差。例如，半導體晶粒310的各垂直位置誤差可少於±20μm。因此，圖1及2中的組裝組件100可促進晶片封裝500的高精確性及高良率組裝。此外，因為此組裝組件也促進高容量及低成本製造技術的使用(諸如，取放機器)，其能大幅降低晶片封裝500的成本。
另外，組裝低成本、高良率晶片封裝的能力可促進高效能裝置。例如，在部分實施例中，將斜層疊晶片封裝(諸如，晶片封裝500)包括在雙行記憶體模組中。例如，可有多達80個記憶體裝置(諸如，動態隨機存取記憶體或其他種類的記憶體儲存裝置)在斜層疊晶片封裝中。若有需要，可將「損壞」或故障記憶體裝置除能。因此，可使用(80個中的)72個記憶體裝置。此外，此組態可揭出記憶體模組中之記憶體裝置的所有帶寬，使得在存 取任何此等記憶體裝置時有些許或沒有潛伏延遲。
或者，該雙行記憶體模組可包括各者能包括斜層疊晶片封裝的多個域。例如，在雙行記憶體模式中可有四個斜層疊晶片封裝(各者包括九個記憶體裝置)。
在部分實施例中，可將一或多個此等雙行記憶體模組(其可包括一或多個斜層疊晶片封裝)耦接至處理器。例如，處理器可使用電容性耦合訊號的電容鄰近通訊(PxC)耦接至一或多個雙行記憶體模組。處理器可使用C4焊球相應地載置在基板上。
在部分實施例中，該組裝工具具有傾斜順應性及垂直移動的能力，同時不容許在半導體晶粒之平面中的動作。或者，可使用球式接頭(諸如，在固定於杯中之桿的端部上的硬球體)。此球式接頭可提供容許繞著所有三個旋轉軸的特定旋轉，但不容許平移的接頭。針對該組裝工具，該桿可係附接至取放機器的載置軸，且該杯可放置在拾取表面內側，使得該旋轉點儘可能接近半導體晶粒。此配置可容許取放機器的表面傾斜以與組裝工具相配，但其可不支援平移。須注意該球式接頭在垂直方向上不會具有任何順應性。然而，該球式接頭可容許沿著所有三個旋轉軸旋轉，使得組裝工具能繞著載置軸旋轉。另一可能性係球形軸承，其與球式接頭相似，除了以取放機器的整體表面可在較大的球形表面內側取代將球限制在取放機器之表面上的小杯內側。此球形表面可包括在更大的球形表面內側，其可容許二球形表面相對於彼此旋轉。與球 式接頭一樣，球形軸承容許沿著所有三個旋轉軸的期望旋轉，但不容許不受期望的組裝工具的平移。
現在描述組裝技術的實施例。圖7呈現描繪使用組裝組件100(圖1及2)組裝晶片封裝之方法700的流程圖。在此方法期間，將黏合劑施加至在其中半導體晶粒組以垂直層疊配置之斜層疊晶片封裝中的半導體晶粒的頂表面(操作710)，其中垂直層疊中的指定半導體晶粒在半導體晶粒組的平面上從相鄰半導體晶粒偏移以界定階梯。然後，使用組裝工具，在第二半導體晶粒的頂表面上將第二半導體晶粒拾起(操作712)。其次，將第二半導體晶粒的底表面放置在半導體晶粒之頂表面上的黏合劑上，同時藉由具有配置在斜層疊晶片封裝之任一側上的一對階梯之組裝組件中的指定階限制組裝工具的垂直位置(操作714)，其中該對階梯中的階提供垂直基準位置。
在方法700的部分實施例中，可能有額外或較少操作。例如，層疊可用包括半導體晶粒之次集的片組裝，將彼等循序組合至完整層疊中。再者，斜坡組件可剛性地機械耦接至半導體晶粒及第二半導體晶粒，其中該斜坡組件位於該垂直層疊的一側上，且其中該斜坡組件幾乎平行於沿著階梯的方向，其在水平方向及垂直方向之間。
此外，將斜坡組件剛性地機械耦接至半導體晶粒及第二半導體晶粒可包含將焊料熔解在：斜坡組件及/或半導體晶粒及第二半導體晶粒上。當回流焊料時，可將斜坡組件放置在層疊上或反之亦然。此可容許斜坡組件 (或半導體晶粒的層疊)協助克服焊料的表面張力。
須注意，當將斜坡組件剛性地機械耦接至半導體晶粒及第二半導體晶粒時，可將壓縮力施加在垂直方向上。此可確保經組裝晶片封裝具有期望高度。在部分實施例中，壓縮力係沿著斜坡組件的垂直方向施加。此等壓縮力的任一者可改善層疊內的熱轉移，例如，藉由填充或減少晶片封裝中之組件間的間隙。
另外，圖7中的操作次序可能改變，及/或將二或多個操作組合成單一操作。
須注意組裝組件100(圖1及2)及晶片封裝500(圖5及6)可包括較少組件或額外組件。例如，可有界定在斜層疊晶片封裝中之半導體晶粒的層疊中的中斷，諸如，藉由不包括用於斜坡組件上之一或多個半導體晶粒的焊墊。再者，雖然將此等裝置及系統說明成具有多個離散項目，將此等實施例視為係可能存在之各種特性的功能描述而非本文描述之實施例的結構概要。因此，在此等實施例中，可能將二或多個組件組合入單一組件中及/或可能改變一或多個組件的位置。
雖然上述實施例在晶片封裝中使用半導體晶 粒(諸如，矽)，在其他實施例中，可能將半導體以外的不同材料使用為一或多個此等晶片中的基材材料。然而，在使用矽的實施例中，半導體晶粒310(圖3-6)可能使用標準矽處理製造。此等半導體晶粒可能提供支援邏輯及/或記憶體功能的矽區域。
另外，在圖5及6中，斜坡組件512可係被動組件，諸如，具有金屬軌以電耦接至半導體晶粒310的塑膠基板。例如，斜坡組件512可使用注入成型塑膠製造。或者，斜坡組件512可係具有光微影界定之佈線或訊號線的另一半導體晶粒。在斜坡組件512包括半導體晶粒的實施例中，可包括主動裝置、諸如，限制放大器，以降低訊號線間的串音。另外，串音可使用差動發訊在主動或被動斜坡組件512的任一者中降低。
在部分實施例中，斜坡組件512包括經由焊球(諸如，焊球518)在半導體晶粒310中接送資料及電力訊號的電晶體及佈線。例如，斜坡組件512可包括高壓訊號。此等訊號可使用下列各者針對使用在半導體晶粒310上而步降：步降穩壓器(諸如，電容器-至-電容器步降穩壓器)，以及電容器及/或電感器離散組件以耦接至半導體晶粒310。
另外，斜坡組件512可包括用於記憶體的緩衝器或邏輯，及/或至外部裝置(等)及/或系統(等)的I/O連接器。例如，I/O連接器可包括一或多個：用於耦接至外部裝置的球式接合器、佈線接合器、邊緣連接器、及/或PxC連接器。在部分實施例中，此等I/O連接器可在斜坡組件512的背表面上，且斜坡組件512可包括將I/O連接器耦接至焊墊，諸如，焊墊522-2。的一或多個貫矽導孔(TSV)。
在部分實施例中，將晶片封裝500中的斜坡 組件512及半導體晶粒310載置在選擇性基板上(諸如，印刷電路板或半導體晶粒)。此選擇性基板可包括：用於耦接至外部裝置的球式接合器、佈線接合器、邊緣連接器、及/或PxC連接器。若此等I/O連接器在選擇性基板的背表面上，該選擇性基板可包括一或多個TSV。
在焊球使用在作為斜坡組件512及半導體晶粒310的電及機械耦接之說明的上述實施例中的同時，在其他實施例中，此等組件可使用其他技術電及/或機械地耦接，諸如：微彈簧、微球體(在下文描述的球在孔中組態)、及/或各向異性膜(諸如，各向異性彈性膜，其有時稱為「各向異性導電膜」)。
在晶片封裝中的組件使用電磁性耦合訊號的PxC(諸如，在下列各者之間的PxC：斜坡組件512及半導體晶粒310、斜坡組件512及外部裝置、斜坡組件512及選擇性基板、選擇性基板及半導體晶粒310、及/或選擇性基板及外部裝置)通訊的實施例中，該PxC可包括：電容性耦合訊號的通訊(其稱為「電鄰近通訊」)、光學性耦合訊號的通訊(其稱為「光學鄰近通訊」)、電磁性耦合訊號的通訊(其稱為「電磁鄰近通訊」)、電感性耦合訊號的通訊、及/或導電性耦合訊號的通訊。
通常，所產生之電接頭的阻抗可係導電性及/或電容性的，亦即，可具有包括同相分量及/或異相分量的複變阻抗。與電接點機制(諸如，焊劑、微彈簧、各向異性層等)無關，若與該等接點關聯的阻抗係導電性的， 可能將習知傳輸及接收I/O電路使用在晶片封裝500中的組件中。然而，針對具有複變(且可能可變)阻抗的接點，該傳輸及接收I/O電路可能包括描述在於2009年4月17日由Robert J.Drost等提出申請之代理人案號第SUN09-0285號的U.S.專利申請案案號第12/425,871號，發明名稱為「用於具有可變複變阻抗之接點的接收電路」的實施例中，該專利之教示全文以提及之方式併入本文中。
須注意，當面對較低半導體晶粒良率或封裝及組裝前之廣泛測試的高費用時，容許特定反修的封裝技術係更有成本效益的。因此，在半導體晶粒310及斜坡組件512之間的機械及/或電耦接可重配對的實施例中，晶片封裝500的良率可能藉由容許反修(諸如，置換在組裝、測試、或燒入期間識別出的壞晶片)而增加。關於此問題，應將可重配對機械或電耦合理解為不需要反修或加熱(諸如，使用焊劑)而可重複地(亦即，二或多次)建立及中斷的機械或電耦合。在部分實施例中，可重配對機械或電耦合包含設計成彼此耦合的凹凸組件(諸如，扣合在一起的組件)。
在圖5及6描繪晶片封裝500之特別組態的同時，許多技術及組態可用於使用或不使用組裝組件100(圖1及2)實作機械對準及組裝。例如，可能使用球在坑中對準技術(且更通常地說，正特性在負特性中的對準技術)將半導體晶粒310及/或斜坡組件512彼此相對地定位。特別係可將球定位在蝕刻坑中以相對地對準組件，如 在層疊312中的半導體晶粒310(圖3)。正特徵的其他範例包括半球型凸塊。然而，將晶片封裝500中之組件上的正及負表面特徵機械地鎖定的任何組合可用於對準及/或組裝晶片封裝500。
參考圖3，如先前在部分實施例中提及的，選擇性散熱材料326(且，更一般而言，在具有高熱導性的半導體晶粒310之間的中間材料)可協助將在一或多個半導體晶粒310及/或斜坡組件512(圖5及6)上之電路的操作期間產生的熱移除。此熱管理可包括任何下列熱路徑：在半導體晶粒310之平面中的第一熱路徑；在黏合層322之平面中的第二熱路徑；及/或在選擇性散熱材料326之平面中的第三熱路徑。特別係與此等熱路徑關聯的熱通量可經由在晶片封裝之邊緣的熱耦接而彼此無關地管理。須注意此熱管理可包括使用下列各者：相變冷卻、浸潤冷卻、及/或冷卻板。也須注意與在晶片封裝之邊緣擴散通過橫剖面區域的第一熱路徑關聯之熱通量係額定厚度320的函數。因此，熱管理可在具有更大或更小的半導體晶粒310之額定厚度的晶片封裝中不同。
須注意可有在晶片封裝500(圖5及6)之至少一部分周圍的選擇性包封。另外，可不將在晶片封裝500(圖5及6)中的組件之間的空氣間隙充滿，以改善熱移除。此可藉由減少圖5中的角516而促進，亦即，半導體晶粒310可更朝向垂直方向116傾斜。
將以上描述視為致能任何熟悉本發明之人士 製造及使用本揭示發明，並將其提供在特定應用及其必要條件的上下文中。再者，已僅針對說明及描述之目的於上文呈現本揭示發明之實施例的描述。不將彼等視為係徹底揭示或將本揭示發明限制在已揭示之形式。因此，許多修改及變化對熟悉本技術的從業人士將係明顯的，並可能將本文界定的通用原理施用至其他實施例及應用而不脫離本揭示發明的精神及範圍。此外，上述實施例的討論未意圖限制本揭示發明。因此，本揭示發明無意受限於已顯示的該等實施例，而待給予與本文所揭示之該等原理及特性符合的最廣寬範圍。
116‧‧‧垂直方向
118‧‧‧水平方向
310-1、310-2、310-N‧‧‧半導體晶粒
322‧‧‧黏合層
500‧‧‧晶片封裝
512‧‧‧斜坡組件
514‧‧‧方向
516‧‧‧角
518‧‧‧焊球
520‧‧‧距離
522-1、522-2‧‧‧焊墊

Claims (20)

  1. 一種組裝組件，包含：具有階之垂直層疊的一對階梯，其中指定階在該等階的平面中從相鄰階偏移以界定該對階梯，其中在該對階梯中的該等階組態成在斜層疊晶片封裝的組裝期間提供限制組裝工具之垂直位置的垂直基準位置；其中該斜層疊晶片封裝中的半導體晶粒組係以垂直層疊配置，其中指定半導體晶粒在該半導體晶粒組的平面中從相鄰半導體晶粒偏移以界定階梯；且其中，在該斜層疊晶片封裝的組裝期間，在該對階梯限制該組裝工具的垂直位置的同時，將該組裝工具機械耦接至該指定半導體晶粒的頂表面，並將該指定半導體晶粒的底表面機械耦接至該斜層疊晶片封裝。
  2. 如申請專利範圍第1項的組裝組件，其中該半導體晶粒組包括N個半導體晶粒；且其中該斜層疊晶片封裝中之該半導體晶粒組在沿著該垂直層疊之垂直方向上的位置誤差與在該斜層疊晶片封裝中的垂直位置無關。
  3. 如申請專利範圍第2項的組裝組件，其中，N大於40。
  4. 如申請專利範圍第1項的組裝組件，其中該等位置誤差各者少於±20μm。
  5. 如申請專利範圍第1項的組裝組件，其中該組裝組件促進該斜層疊晶片封裝的組裝，該斜層疊晶片封裝具有 少於與該半導體晶粒組及該等半導體晶粒之間的黏合層關聯之位置誤差的和之在沿著該垂直層疊的垂直方向上之該半導體晶粒組上方的累積位置誤差。
  6. 如申請專利範圍第5項的組裝組件，其中該累積位置誤差與下列一者關聯：該等半導體晶粒的厚度變化，及該等黏合層的厚度變化。
  7. 如申請專利範圍第1項的組裝組件，其中該指定半導體晶粒包括在該頂表面上的焊墊及焊點凸塊；且其中該組裝工具在該頂表面之該等焊墊及焊點凸塊所在位置以外的區域中拾取該指定半導體晶粒。
  8. 如申請專利範圍第1項的組裝組件，其中該階梯係該對階梯的鏡像。
  9. 如申請專利範圍第1項的組裝組件，其中該指定半導體晶粒具有額定厚度；且其中該階梯中的該指定階的垂直移位大於該額定厚度。
  10. 如申請專利範圍第1項的組裝組件，其中該組裝組件促進斜坡組件對該斜層疊晶片封裝的剛性機械耦接，其中將該斜坡組件放置在該垂直層疊的一側上，且其中該斜坡組件幾乎平行於沿著該階梯的方向，其在該半導體晶粒組之平面的水平方向及沿著該垂直層疊的垂直方向之間。
  11. 一種用於組裝斜層疊晶片封裝的方法，其中該方法包含： 將黏合劑施加至在其中半導體晶粒組以垂直層疊配置之該斜層疊晶片封裝中的半導體晶粒的頂表面，其中該垂直層疊中的指定半導體晶粒在該半導體晶粒組的平面上從相鄰半導體晶粒偏移以界定階梯；使用組裝工具，在第二半導體晶粒之頂表面上拾取該第二半導體晶粒；且將該第二半導體晶粒的底表面放置在該半導體晶粒之該頂表面上的該黏合劑上，同時藉由具有配置在該斜層疊晶片封裝之任一側上的一對階梯之組裝組件中的指定階限制該組裝工具的該垂直位置，其中該對階梯中的階提供垂直基準位置。
  12. 如申請專利範圍第11項的方法，其中該施加、拾取、及放置操作對該半導體晶粒組中的額外半導體晶粒重複以組裝該斜層疊晶片封裝；且其中當組裝該斜層疊晶片封裝時，藉由該對階梯中的該等階限制該組裝工具的垂直位置。
  13. 如申請專利範圍第12項的方法，其中該半導體晶粒組包括N個半導體晶粒；且其中該斜層疊晶片封裝中之該半導體晶粒組在沿著該垂直層疊之垂直方向上的位置誤差與在該斜層疊晶片封裝中的位置無關。
  14. 如申請專利範圍第13項的方法，其中，N大於40。
  15. 如申請專利範圍第13項的方法，其中該等位置誤 差各者少於±20μm。
  16. 如申請專利範圍第11項的方法，其中該組裝組件促進該斜層疊晶片封裝的組裝，該斜層疊晶片封裝具有少於與該半導體晶粒組及該等半導體晶粒之間的黏合層關聯之位置誤差的和之在沿著該垂直層疊的垂直方向上之該半導體晶粒組上方的累積位置誤差。
  17. 如申請專利範圍第11項的方法，其中該半導體晶粒包括在該頂表面上的焊墊及焊點凸塊；且其中該組裝工具在該頂表面之該等焊墊及焊點凸塊所在位置以外的區域中拾取該半導體晶粒。
  18. 如申請專利範圍第11項的方法，其中該階梯係該對階梯的鏡像。
  19. 如申請專利範圍第11項的方法，其中該指定半導體晶粒具有額定厚度；且其中該階梯中的該指定階的垂直移位大於該額定厚度。
  20. 如申請專利範圍第11項的方法，其中該組裝組件促進斜坡組件對該斜層疊晶片封裝的剛性機械耦接，其中將該斜坡組件放置在該垂直層疊的一側上，且其中該斜坡組件幾乎平行於沿著該階梯的方向，其在該半導體晶粒組之平面的水平方向及沿著該垂直層疊的垂直方向之間。
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