JP6534386B2 - スタック化されたダイの位置を制御するための技術 - Google Patents
スタック化されたダイの位置を制御するための技術 Download PDFInfo
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- JP6534386B2 JP6534386B2 JP2016522774A JP2016522774A JP6534386B2 JP 6534386 B2 JP6534386 B2 JP 6534386B2 JP 2016522774 A JP2016522774 A JP 2016522774A JP 2016522774 A JP2016522774 A JP 2016522774A JP 6534386 B2 JP6534386 B2 JP 6534386B2
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- semiconductor die
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Description
分野
本開示は、概して、半導体チップパッケージを製造するプロセスに関する。より具体的には、本開示は、組立コンポーネント、および、階段状テラスを規定するために垂直スタックにおいて互いにオフセットされたチップの群を含むチップパッケージを組立てるための関連の技術に関する。
スタック化された半導体チップまたはダイを含むチップパッケージは、プリント回路基板に接続された従来の個別にパッケージ化されたチップに比べて、非常に高い性能を提供することができる。これらのチップパッケージは、スタック内における異なるチップに対して異なるプロセスを使用することができること、高密度のロジックとメモリとを組み合わせることができること、および、より少ない電力でデータを転送することができることなどの特定の利点も提供する。例えば、ダイナミックランダムアクセスメモリ(DRAM)を実装するチップのスタックは、入出力(I/O)およびコントローラ機能を実現するためにベースチップ内において高位の金属層カウント(high-metal-layer-count)で高性能のロジックプロセスを使用することができ、残余のスタックのために、より低位の金属層カウント(lower metal-layer-count)でDRAM専用のプロセスチップが使用され得る。このように、組み合わせられた一組のチップは、DRAMプロセスを用いて製造されたI/Oおよびコントローラの機能を含む単一のチップ、ロジックプロセスを用いて製造されたメモリ回路を含む単一のチップ、および/または、ロジックおよびメモリ双方の物理構造を製造するために単一のプロセスを使用しようと試みることよりも、良好な性能でかつ低コストを有し得る。
本開示の一実施例は、組立コンポーネントを提供し、当該組立コンポーネントは、段の垂直スタックを有する一対の階段状テラスを含み、垂直スタックでは、一対の階段状テラスを規定するために、所与の段が段の平面における隣接する段からオフセットされる。一対の階段状テラスにおける段は、一組の半導体ダイが垂直スタック内に配置される傾斜スタックチップパッケージの組立て中に組立ツールの垂直位置を制約する垂直基準位置を与える。さらに、傾斜スタックチップパッケージ内の所与の半導体ダイは、階段状テラスを規定するために、一組の半導体ダイの平面における隣接する半導体ダイからオフセットされる。一対の階段状テラスが組立ツールの垂直位置を制約する傾斜スタックチップパッケージの組立て中に、組立ツールは、所与の半導体ダイの上面に機械的に結合され、所与の半導体ダイの底面は、傾斜スタックチップパッケージに機械的に結合される。
所与の半導体ダイは、公称厚みを有し得て、階段状テラスにおける所与の段の垂直方向のずれは、公称厚みよりも大きくてもよいことに注目されたい。
組立コンポーネントおよび当該組立コンポーネントを用いてチップパッケージを組立てるための方法の実施例について説明する。このチップパッケージは、垂直方向にスタック内に配置される一組の半導体ダイを含み、当該一組の半導体ダイは、垂直スタックの一方の側に階段状テラス(stepped terrace)を規定するために水平方向に互いにオフセットされている。さらに、チップパッケージは、階段状テラスに沿った方向にほぼ平行な垂直スタックの一方の側に位置決めされた傾斜コンポーネントを含む。このチップパッケージは、組立コンポーネントを用いて組立てられ得る。特に、組立コンポーネントは、一対の階段状テラスを含み得て、当該一対の階段状テラスは、チップパッケージの階段状テラスをほぼ反映し、チップパッケージの組立て中に一組の半導体ダイを垂直スタック内に位置決めする組立ツールに対して垂直位置基準を与える。
Claims (15)
- 組立コンポーネントであって、段の垂直スタックを有する一対の階段状テラスを備え、前記垂直スタックでは、前記一対の階段状テラスを規定するために、所与の段が前記段の平面における隣接する段からオフセットされ、前記一対の階段状テラスにおける前記段は、傾斜スタックチップパッケージの組立て中に組立ツールの垂直基準位置を与えるように構成され、
前記傾斜スタックチップパッケージ内の一組の半導体ダイは、前記垂直スタック内に配置され、前記垂直スタックでは、階段状テラスを規定するために、所与の半導体ダイが前記一組の半導体ダイの平面における隣接する半導体ダイからオフセットされ、
前記組立ツールは、前記所与の半導体ダイの上面に機械的に結合され、前記階段状テラスの段の上に載置可能な翼部を有し、前記組立コンポーネントに関連する前記所与の半導体ダイの上面の垂直位置は、前記組立ツールおよび前記翼部によって制約される、組立コンポーネント。 - 前記一組の半導体ダイは、N個の半導体ダイを含み、
前記垂直スタックに沿った垂直方向の前記傾斜スタックチップパッケージ内の前記一組の半導体ダイの位置誤差は、前記傾斜スタックチップパッケージにおける垂直位置から独立している、請求項1に記載の組立コンポーネント。 - Nは40よりも大きい、請求項2に記載の組立コンポーネント。
- 前記位置誤差は、各々±20μm未満である、請求項2または3に記載の組立コンポーネント。
- 前記組立コンポーネントは、前記垂直スタックに沿った垂直方向の前記一組の半導体ダイにわたる累積位置誤差が、前記一組の半導体ダイおよび前記半導体ダイ間の接着層に関連付けられる位置誤差の合計未満であることにより、前記傾斜スタックチップパッケージの組立てを容易にする、請求項1〜4のいずれか1項に記載の組立コンポーネント。
- 前記累積位置誤差は、前記半導体ダイの厚みのばらつきおよび前記接着層の厚みのばらつきのうちの1つに関連付けられる、請求項5に記載の組立コンポーネント。
- 前記所与の半導体ダイは、前記上面上にはんだパッドおよびバンプを含み、
前記組立ツールは、前記はんだパッドおよび前記バンプが位置する領域以外の前記上面の領域において前記所与の半導体ダイを持ち上げる、請求項1〜6のいずれか1項に記載の組立コンポーネント。 - 前記階段状テラスは、前記一対の階段状テラスの鏡像である、請求項1〜7のいずれか1項に記載の組立コンポーネント。
- 前記所与の半導体ダイは、公称厚みを有し、
前記階段状テラスにおける前記所与の段の垂直方向のずれは、前記公称厚みよりも大きい、請求項1〜8のいずれか1項に記載の組立コンポーネント。 - 前記組立コンポーネントは、前記傾斜スタックチップパッケージに対する傾斜コンポーネントの固定的な機械的結合を容易にし、
前記傾斜コンポーネントは、前記垂直スタックの一方の側に位置決めされ、
前記傾斜コンポーネントは、前記一組の半導体ダイの前記平面における水平方向と前記垂直スタックに沿った垂直方向との間である前記階段状テラスに沿った方向にほぼ平行である、請求項1〜9のいずれか1項に記載の組立コンポーネント。 - 傾斜スタックチップパッケージを組立てるための方法であって、
一組の半導体ダイが垂直スタック内に配置される前記傾斜スタックチップパッケージにおける半導体ダイの上面に接着剤を適用するステップを備え、前記垂直スタック内の所与の半導体ダイは、階段状テラスを規定するために前記一組の半導体ダイの平面における隣接する半導体ダイからオフセットされ、前記方法はさらに、
組立ツールを用いて、第2の半導体ダイの上面上で前記第2の半導体ダイを持ち上げるステップと、
前記傾斜スタックチップパッケージの両側に配置される一対の階段状テラスを有する組立コンポーネントにおける所与の段によって前記組立ツールの垂直位置を制約しつつ、前記第2の半導体ダイの底面を前記半導体ダイの前記上面上の前記接着剤の上に設置するステップとを備え、前記一対の階段状テラスにおける段は、前記組立ツールの垂直基準位置を与え、前記組立ツールは前記第2の半導体ダイの上面に機械的に結合され、前記階段状テラスの段の上に載置可能な翼部を有し、前記組立コンポーネントに関連する前記第2の半導体ダイの上面の垂直位置は、前記組立ツールおよび前記翼部によって制約される方法。 - 前記適用するステップ、持ち上げるステップおよび設置するステップは、前記傾斜スタックチップパッケージを組立てるために前記一組の半導体ダイにおけるさらなる半導体ダイについて繰返され、
前記組立ツールの垂直位置は、前記傾斜スタックチップパッケージが組立てられる際に前記一対の階段状テラスにおける前記段によって制約される、請求項11に記載の方法。 - 前記一組の半導体ダイは、N個の半導体ダイを含み、
前記垂直スタックに沿った垂直方向の前記傾斜スタックチップパッケージ内の前記一組の半導体ダイの位置誤差は、前記傾斜スタックチップパッケージにおける位置から独立している、請求項12に記載の方法。 - 前記組立コンポーネントは、前記垂直スタックに沿った垂直方向の前記一組の半導体ダイにわたる累積位置誤差が、前記一組の半導体ダイおよび前記半導体ダイ間の接着層に関連付けられる位置誤差の合計未満であることにより、前記傾斜スタックチップパッケージの組立てを容易にする、請求項11〜13のいずれか1項に記載の方法。
- 前記半導体ダイは、前記上面上にはんだパッドおよびバンプを含み、
前記組立ツールは、前記はんだパッドおよび前記バンプが位置する領域以外の前記上面の領域において前記半導体ダイを持ち上げる、請求項11〜14のいずれか1項に記載の方法。
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