CN117712067A - 使用高密度互连桥接器的2xd模块的组件 - Google Patents

使用高密度互连桥接器的2xd模块的组件 Download PDF

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Publication number
CN117712067A
CN117712067A CN202311726120.5A CN202311726120A CN117712067A CN 117712067 A CN117712067 A CN 117712067A CN 202311726120 A CN202311726120 A CN 202311726120A CN 117712067 A CN117712067 A CN 117712067A
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China
Prior art keywords
die
bridge
layer
chip module
molding layer
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CN202311726120.5A
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English (en)
Inventor
B·魏达斯
A·沃尔特
G·塞德曼
T·瓦格纳
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Intel Corp
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Intel Corp
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Publication of CN117712067A publication Critical patent/CN117712067A/zh
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Abstract

本文公开的实施例包括电子封装和形成这种封装的方法。在实施例中，电子封装包括模制层和嵌入在模制层中的第一管芯。在实施例中，第一管芯包括具有第一间距的第一焊盘和具有第二间距的第二焊盘。在实施例中，电子封装还包括嵌入在模制层中的第二管芯，其中第二管芯包括具有第一间距的第三焊盘和具有第二间距的第四焊盘。在实施例中，桥接器管芯嵌入在模制层中，并且桥接器管芯将第二焊盘电耦合到第四焊盘。

Description

使用高密度互连桥接器的2XD模块的组件
本申请是申请日为2021年10月26日、申请号为202111252319.X、发明名称为“使用高密度互连桥接器的2XD模块的组件”的申请的分案申请。
技术领域
本公开的实施例涉及电子封装，并且更具体而言，涉及一种具有高密度互连桥接器的多芯片封装。
背景技术
向多管芯模块的发展导致需要先进的互连架构以便容纳多个管芯。在一种类型的架构中，多个管芯附接到在多个管芯之间提供电耦合的插入件。然而，插入件的面积必须至少与若干管芯的面积之和一样大，并且包括附加的组装和布线开销。插入件面积的增长增加了成本并带来了制造问题。
在另一方法中，在封装衬底中提供嵌入式桥接器。桥接器提供高密度布线以便将多个管芯电耦合在一起。然而，由于需要多个桥接器管芯，因此存在获得所有桥接器管芯的适当对准的问题。由于其中嵌入桥接器管芯的封装衬底的翘曲，也使得对准变得困难。随着封装所需的桥接器管芯的数量增加，对准问题变成越来越困难的设计挑战。
附图说明
图1是根据实施例的多芯片模块的截面图，该多芯片模块包括嵌入在模制层中以将第一管芯耦合到第二管芯的桥接器。
图2A是根据实施例的在导电柱之上包括焊球的多芯片模块的截面图。
图2B是根据实施例的附接到封装衬底的多芯片模块的截面图。
图2C是根据实施例的具有多个管芯和将管芯连接在一起的桥接器管芯的多芯片模块的平面图。
图2D是根据实施例的具有耦合到板的多芯片模块的电子系统的截面图。
图2E是根据实施例的具有通过插入件耦合到封装衬底的多芯片模块的电子系统的截面图。
图3A是根据实施例的在导电柱之上具有再分布层的多芯片模块的截面图。
图3B是根据实施例的耦合到封装衬底的多芯片模块的截面图。
图3C是根据实施例的具有耦合到板的多芯片模块的电子系统的截面图。
图4A-4D是示出根据实施例的用于组装多芯片模块的过程的截面图。
图5A-5D是示出根据实施例的用于组装具有桥接器管芯和部件管芯的多芯片模块的过程的截面图。
图6A-6F是示出根据实施例的用于组装具有至少部分嵌入在模制层中的焊球的多芯片模块的过程的截面图。
图7A-7F是示出根据实施例的用于组装具有多层管芯的多芯片模块的过程的截面图。
图7G-7J是示出根据另外实施例的用于组装多芯片模块的过程的截面图。
图8A-8F是示出根据实施例的用于组装具有薄管芯和薄桥接器管芯的多芯片模块的过程的截面图。
图9A-9D是示出根据实施例的能够适应管芯偏移的互连架构的平面图。
图10A-10D是根据实施例的适应管芯未对准的桥接器管芯架构的平面图。
图11是根据实施例构建的计算设备的示意图。
具体实施方式
本文描述了根据各种实施例的具有高密度互连桥接器的多芯片封装。在以下描述中，将使用本领域技术人员通常采用的术语来描述说明性实施方式的各个方面，以向本领域其他技术人员传达其工作的实质。然而，对于本领域技术人员而言显而易见的是，本发明可以仅利用所描述的方面中的一些方面来实施。为了解释的目的，阐述了具体的数字、材料和配置，以便提供对说明性实施方式的透彻理解。然而，对于本领域技术人员而言显而易见的是，可以在没有这些具体细节的情况下实施本发明。在其他实例中，省略或简化了公知的特征，以免使说明性实施方式难以理解。
将以最有助于理解本发明的方式将各种操作依次描述为多个分立的操作，然而，描述的顺序不应被解释为暗示这些操作必须是顺序相关的。特别地，这些操作不需要以所呈现的顺序来执行。
如上所述，当前的多芯片架构(例如，插入件和嵌入式桥接器)具有导致工程困难和成本增加的显著限制。因此，本文公开的实施例包括使用改进的工艺组装的多芯片模块。本文描述的多芯片模块包括第一管芯、第二管芯、以及将第一管芯电耦合到第二管芯的桥接器管芯。第一管芯、第二管芯和桥接器管芯嵌入在模制层中。特别地，通过将管芯组装在一起同时由尺寸稳定的载体支撑，使得多个管芯之间的对准更容易。因此，在组装期间基本上不存在翘曲或平面度问题。在将管芯耦合在一起之后，将多个管芯嵌入在模制层中。
这种多芯片模块为各种封装架构提供了灵活性。在一个实施例中，多芯片模块可以通过焊球连接到封装衬底。在一些实施例中，多芯片模块可以连接到在多芯片模块和封装衬底之间的插入件。在又一实施例中，多芯片模块可以直接连接到板，例如印刷电路板(PCB)。
实施例还可以允许通过在模制层的表面之上提供再分布层来改进布线灵活性。再分布层可以允许间距扩展，以便允许与诸如封装衬底、插入件或板的其他部件的更容易的组装。再分布层还可以包括电源网格(power supply mesh)和/或热改进过孔(例如，虚设焊盘)。
本文公开的实施例还允许多个多芯片模块的堆叠。可以通过使用穿过基础管芯和/或桥接器管芯的穿硅过孔(TSV)来实现堆叠能力。堆叠模块使得多芯片模块的容量和性能增加，同时保持较小的占用面积。
另外，实施例包括实现基础管芯与桥接器管芯的对准的灵活性的焊盘设计。例如，基础管芯上的焊盘可以是细长的并且相对于基础管芯的边缘成角度。因此，即使当基础管芯未对准时，也可以移位桥接器管芯以便允许两个基础管芯的成功耦合。在其他实施例中，可以在组装设施中提供具有不同互连图案的多个桥接器管芯。具有最紧密地匹配基础管芯之间的未对准的互连图案的桥接器管芯可以用于组装中。
现在参考图1，示出了根据实施例的多芯片模块120的截面图。在实施例中，多芯片模块120可以包括第一基础管芯125A和第二基础管芯125B。第一基础管芯125A和第二基础管芯125B可以包括任何类型的管芯，例如但不限于处理器、图形处理器、现场可编程门阵列(FPGA)、存储器管芯等。第一基础管芯125A和第二基础管芯125B可以包括第一焊盘122和第二焊盘124。在第一基础管芯125A上，第一焊盘122可以具有第一间距P1，并且第二焊盘124可以具有第二间距P2。在一些实施例中，第二间距P2小于第一间距P1。较小间距P2允许所附接的桥接器管芯127中的高密度布线。在实施例中，第一间距P1可以是约55μm或更大，并且第二间距P2可以小于55μm。例如，第二间距可以是约20μm或更小。在第二基础管芯125B上，第一焊盘122可以具有第三间距P3，并且第二焊盘124可以具有小于第三间距P3的第四间距P4。实施例中，第一间距P1可以基本上等于第三间距P3，或者第一间距P1可以不同于第三间距P3。在实施例中，第二间距P2可以基本上等于第四间距P4，或者第二间距P2可以不同于第四间距P4。
在实施例中，第一基础管芯125A上的第二焊盘124接近于第一基础管芯125A的紧邻第二基础管芯125B的边缘，并且第二基础管芯125B上的第二焊盘124接近于第二基础管芯125B的紧邻第一基础管芯125A的边缘。跨越在第一基础管芯125A与第二基础管芯125B之间的桥接器管芯127连接到第二焊盘124。在所示的实施例中，桥接器管芯127上的桥接器焊盘128通过焊料129耦合到第二焊盘124。然而，应理解，可以使用任何互连架构来将桥接器焊盘128耦合到第二焊盘124。例如，铜与铜的键合可以用于形成连接。
在实施例中，桥接器管芯127包括硅或另一种半导体材料。桥接器管芯127可以是无源桥接器或有源桥接器。桥接器管芯127包括尺寸稳定的衬底，其允许用于将第一基础管芯125A电耦合到第二基础管芯125B的高密度布线。
在实施例中，第一焊盘122可以由导电柱123接触。例如，导电柱可以包括铜柱等。导电柱123的高度可以被选择为使得导电柱123的底表面与桥接器管芯127的底表面基本共面。如将在以下处理流程中描述的，可以使用抛光和/或研磨工艺来提供桥接器管芯127与导电柱123之间的共面性。虽然在图1中示出导电柱123，但是应理解，其他互连架构可以用于连接到第一焊盘122。例如，可以使用焊球，如将在下面更详细地描述的。
在实施例中，多芯片模块120可以嵌入在模制层121中。模制层121可以是任何适当的模制化合物，例如环氧树脂等。在实施例中，模制层121可以具有与第一基础管芯125A和第二基础管芯125B的背侧表面基本上共面的第一表面。模制层121还可以具有与桥接器管芯127和导电柱123的表面基本上共面的第二表面。
在实施例中，用于组装多芯片模块120的工艺可以允许基础管芯125A和125B中的一个或两者以及桥接器管芯127显著变薄。如下文将更详细描述的，可以减薄基础管芯125A和125B和/或桥接器管芯127以使得其具有小于约100μm、小于约50μm或小于约30μm的厚度。这是对通常具有大约700μm或更大的管芯厚度的现有架构的显著改进。
现在参考图2A，示出了根据另外实施例的多芯片模块220的截面图。在实施例中，多芯片模块220包括嵌入有第一基础管芯225A、第二基础管芯225B和桥接器管芯227的模制层221。桥接器管芯227可以将第一基础管芯225A电耦合到第二基础管芯225B。例如，包括第二焊盘224、焊料229和桥接器焊盘228的互连将桥接器管芯227连接到基础管芯225A和225B。在实施例中，基础管芯225A和225B的第一焊盘222由导电柱223覆盖。在实施例中，导电柱223可以由焊球231覆盖。焊球231允许连接到电子系统中的其他结构，如将在下面描述的。
现在参考图2B，示出了根据实施例的具有多芯片模块220的电子系统200的截面图。在实施例中，多芯片模块220可以基本上类似于图2A中的多芯片模块220。在实施例中，多芯片模块220可以通过焊球231连接到板232。板232可以是PCB等。即，多芯片模块220可以直接耦合到板而没有居间封装衬底。
现在参考图2C，示出了根据实施例的电子系统200的平面图。如图所示，在板232之上提供多个基础管芯225A-225D。在实施例中，提供多个桥接器管芯227以将多个基础管芯225A-225D连接在一起。桥接器管芯227和多个基础管芯225A-225D可以嵌入在模制层221中。
现在参考图2D，示出了根据另外实施例的电子系统200的截面图。如图2D所示，多芯片模块220通过焊球231等附接到封装衬底230。例如，焊球231可以用铜柱凸块、LGA和焊膏印刷来代替，仅列举几例。封装衬底230可以包括嵌入在电介质材料中的多个导电布线层(未示出)。例如，导电布线层可以包括提供从封装衬底230的顶表面到封装衬底的底表面的电耦合的焊盘、迹线、过孔等。如图所示，封装衬底230可以耦合到板232，例如PCB。虽然示出了焊球233将封装衬底230连接到板232，但是应理解，可以使用任何互连架构，例如插座等。
现在参考图2E，示出了根据另外实施例的电子系统200的截面图。在实施例中，图2E中的电子系统200可以基本上类似于图2D中的电子系统200，其中加入了插入件234。在实施例中，焊球231可以耦合到插入件234而不是封装衬底230。插入件234可以包括导电布线(未示出)。导电布线可以提供间距转换，以便将互连扩展到与封装衬底架构更兼容的间距。例如，插入件234可以通过焊料凸块235耦合到封装衬底230。
现在参考图3A，示出了根据另外实施例的多芯片模块320的截面图。在实施例中，多芯片模块320可以基本上类似于图2A中的多芯片模块220，其中在模制层321和焊球331之间加入了再分布层326。即，多芯片模块320可以包括通过桥接器管芯327电耦合在一起的第一基础管芯325A和第二基础管芯325B。
在实施例中，第一焊盘322通过导电柱323耦合到模制层321的表面。在实施例中，导电柱323可以通过再分布层326中的导电布线电耦合到焊球331。虽然示出了再分布层326，但是应理解，在一些实施例中再分布层326可以用层压衬底代替。再分布层326允许间距扩展，以允许与电子系统的其他部件更容易地集成。另外，再分布层可以提供用于电源网格和/或热改进过孔(例如，虚设焊盘)的定位。虽然示出了单个再分布层326，但是应理解，可以在多芯片模块320中提供任何数量的再分布层。
现在参考图3B，示出了根据实施例的具有多芯片模块320的电子系统300的截面图。在实施例中，多芯片模块320通过焊球331耦合到板332。板332可以包括PCB等。即，具有再分布层326的多芯片模块320可以直接耦合到板332而没有居间封装衬底。
现在参考图3C，示出了根据另外实施例的电子系统300的截面图。如图3C所示，具有再分布层326的多芯片模块320通过焊球331附接到封装衬底330。封装衬底330可以包括嵌入在电介质材料中的多个导电布线层(未示出)。例如，导电布线层可以包括提供从封装衬底330的顶表面到封装衬底的底表面的电耦合的焊盘、迹线、过孔等。如图所示，封装衬底330可以耦合到板332，例如PCB。虽然示出焊球333将封装衬底330连接到板332，但是应理解，可以使用任何互连架构，例如插座等。
现在参考图4A-4D，示出了根据实施例的描绘用于形成多芯片模块的过程的一系列截面图。在实施例中，图4A-4D中组装的多芯片模块可以用于上述电子系统200/300中的一个或多个中。
现在参考图4A，示出了根据实施例的在载体450上的一对基础管芯425A和425B的截面图。第一基础管芯425A和第二基础管芯425A可以包括第一焊盘422和第二焊盘424。第一焊盘422可以具有大于第二焊盘424的第二间距的第一间距。在实施例中，可以在第一焊盘422之上提供诸如导电柱423的互连。例如，导电柱423可以包括铜。
在实施例中，载体450是具有高硬度的尺寸稳定的材料。载体450的一个目的是提供不易于翘曲的基底。因此，可以严格控制第一基础管芯425A、第二基础管芯425B与后续加入的桥接器管芯427之间的对准。在实施例中，载体450可以是玻璃或金属材料。在一些实施例中，载体可以包括硅。在所示的实施例中，第一基础管芯425A和第二基础管芯425B直接接触载体450。然而，应理解，临时粘合剂可以将基础管芯425A和425B固定到载体450。
现在参考图4B，示出了根据实施例的在将桥接器管芯427附接到基础管芯425A和425B之后的结构的截面图。在实施例中，可以使用倒装芯片安装等来附接桥接器管芯427。例如，焊料429可以将第二焊盘424固定到桥接器焊盘428。在其他实施例中，桥接器焊盘428可以使用铜与铜键合等直接连接到第二焊盘424。
在实施例中，桥接器管芯427提供第一基础管芯425A与第二基础管芯425B之间的高密度布线。例如，桥接器管芯427可以包括诸如硅的半导体衬底。桥接器管芯427上的细线和间距迹线(未示出)可以将第一基础管芯425A之上的桥接器焊盘428连接到第二基础管芯425B之上的桥接器焊盘428。
现在参考图4C，示出了根据实施例的在载体450之上设置模制层421之后的结构的截面图。在实施例中，模制层421可以用包覆成型工艺形成。模制层421可以包括环氧树脂等。
现在参考图4D，示出了根据实施例的在使模制层421凹陷之后的结构的截面图。在实施例中，利用研磨工艺等使模制层421凹陷。可以使模制层421凹陷以暴露导电柱423的表面和桥接器管芯427的背侧表面。在实施例中，研磨工艺可以包括减小桥接器管芯427和/或导电柱423的厚度。在实施例中，导电柱423的表面451、桥接器管芯427的表面452和模制层421的表面453可以基本上彼此共面。
在用以暴露桥接器管芯427和导电柱423的凹陷工艺之后，可去除载体450。在其他实施例中，在释放载体450之前，可以在表面451、452、453之上形成再分布层。或者，可以在去除载体450之前或之后将焊球附接到导电柱423。在去除载体450之后，可以将多芯片模块集成到电子系统(例如，上文所描述的电子系统)中。
现在参考图5A-5D，示出了根据另外实施例的描绘用于形成多芯片模块的过程的一系列截面图。图5A-5D中的多芯片模块还可以包括嵌入在模制层中并连接到第一基础管芯和第二基础管芯之一的附加部件。在实施例中，图5A-5D中组装的多芯片模块可以用于上述电子系统200/300中的一个或多个中。
现在参考图5A，示出了根据实施例的第一基础管芯525A和第二基础管芯525B附接到其上的载体550的截面图。第一基础管芯525A和第二基础管芯525B可以包括第一焊盘522和第二焊盘524。第一焊盘522可以具有大于第二焊盘524的第二间距的第一间距。在实施例中，可以在第一焊盘522之上提供诸如导电柱523的互连。例如，导电柱523可以包括铜。
在实施例中，第一基础管芯525A和第二基础管芯525B中的一个或两者可以包括第三焊盘517。第三焊盘517可以具有小于第一间距的第三间距。在一些实施例中，第三间距可以基本上类似于第二焊盘524的第二间距。第三焊盘517可以用于将附加部件(在图5A中未示出)连接到第一基础管芯525A。
在实施例中，载体550是具有高硬度的尺寸稳定的材料。载体550的一个目的是提供不易于翘曲的基底。因此，可以严格控制第一基础管芯525A、第二基础管芯525B与随后加入的桥接器管芯527之间的对准。在实施例中，载体550可以是玻璃或金属材料。在一些实施例中，载体可以包括硅。在所示的实施例中，第一基础管芯525A和第二基础管芯525B直接接触载体550。然而，应理解，临时粘合剂可以将基础管芯525A和525B固定到载体550。
现在参考图5B，示出了根据实施例的在桥接器管芯527和部件515附接到基础管芯525A和525B之后的结构的截面图。在实施例中，可以使用倒装芯片安装等附接桥接器管芯527。例如，焊料529可以将第二焊盘524固定到桥接器焊盘528。在其他实施例中，可以使用铜与铜键合等将桥接器焊盘528直接连接到第二焊盘524。在实施例中，部件515的厚度和桥接器管芯527的厚度可以基本上相同，或者部件515的厚度可以不同于桥接器管芯527的厚度。基础管芯525A和525B和/或其铜柱的厚度的差异可以容易地通过焊料和/或桥接器管芯的铜柱的厚度的变化来补偿。
在实施例中，桥接器管芯527提供第一基础管芯525A与第二基础管芯525B之间的高密度布线。例如，桥接器管芯527可以包括诸如硅的半导体衬底。桥接器管芯527上的细线和间距迹线(未示出)可以将第一基础管芯525A之上的桥接器焊盘528连接到第二基础管芯525B之上的桥接器焊盘528。
在实施例中，部件515连接到第三焊盘517。例如，可以利用倒装芯片工艺来附接部件515。第三焊盘517可以通过焊料518等耦合到部件焊盘519。或者，可以使用第三焊盘517和部件焊盘519之间的铜与铜连接。在实施例中，部件515可以是用于第一基础管芯525A的操作的任何分立部件。例如，部件515可以包括滤波器、无源器件(例如，电容器、电感器等)等和/或有源器件(例如，电压调节器、SRAM、存储器等)。
现在参考图5C，示出了根据实施例的在将模制层521设置在载体550之上之后的结构的截面图。在实施例中，模制层521可以利用包覆成型工艺形成。模制层521可以包括环氧树脂等。
现在参考图5D，示出了根据实施例的在使模制层521凹陷之后的结构的截面图。在实施例中，利用研磨工艺等使模制层521凹陷。可以使模制层521凹陷以暴露导电柱523的表面、桥接器管芯527的背侧表面和部件515的背侧表面。在实施例中，研磨工艺可以包括减小桥接器管芯527、部件515和/或导电柱523的厚度。在实施例中，导电柱523的表面551、桥接器管芯527的表面552、部件515的表面554以及模制层521的表面553可以基本上彼此共面。
在用以暴露桥接器管芯527、部件515和导电柱523的凹陷工艺之后，可以去除载体550。在其他实施例中，可以在释放载体550之前在表面551、552、553、554之上形成再分布层。或者，可以在去除载体550之前或之后将焊球附接到导电柱523。在去除载体550之后，可以将多芯片模块集成到电子系统(例如，上文所描述的电子系统)中。
现在参考图6A-6F，示出了根据另外实施例的描绘用于组装多芯片模块的过程的一系列截面图。在图6A-6F所示的实施例中，用接触第一焊盘的部分嵌入的焊球代替导电柱。在实施例中，图6A-6F中组装的多芯片模块可以用于上述电子系统200/300中的一个或多个中。
现在参考图6A，示出了根据实施例的载体650上的一对基础管芯625A和625B的截面图。第一基础管芯625A和第二基础管芯625B可以包括第一焊盘622和第二焊盘624。第一焊盘622可以具有大于第二焊盘624的第二间距的第一间距。
在实施例中，载体650是具有高硬度的尺寸稳定的材料。载体650的一个目的是提供不易于翘曲的基底。因此，可以严格控制第一基础管芯625A、第二基础管芯625B和随后加入的桥接器管芯627之间的对准。在实施例中，载体650可以是玻璃或金属材料。在一些实施例中，载体可以包括硅。在所示的实施例中，第一基础管芯625A和第二基础管芯625B直接接触载体650。然而，应理解，临时粘合剂可以将基础管芯625A和625B固定到载体650。
现在参考图6B，示出了根据实施例的在将桥接器管芯627附接到基础管芯具625A和625B之后的结构的截面图。在实施例中，可以使用倒装芯片安装等来附接桥接器管芯627。例如，焊料629可以将第二焊盘624固定到桥接器焊盘628。在其他实施例中，可以使用铜与铜键合等将桥接器焊盘628直接连接到第二焊盘624。
在实施例中，桥接器管芯627在第一基础管芯625A和第二基础管芯625B之间提供高密度布线。例如，桥接器管芯627可以包括诸如硅的半导体衬底。桥接器管芯627上的细线和间距迹线(未示出)可以将第一基础管芯625A之上的桥接器焊盘628连接到第二基础管芯625B之上的桥接器焊盘628。
现在参考图6C，示出了根据实施例的在将模制层621设置在载体650之上之后的结构的截面图。在实施例中，模制层621可以用包覆成型工艺形成。模制层621可以包括环氧树脂等。
现在参考图6D，示出了根据实施例的在使模制层621凹陷之后的结构的截面图。在实施例中，利用研磨工艺等使模制层621凹陷。可以使模制层621凹陷以暴露桥接器管芯627的背侧表面。在实施例中，研磨工艺可以包括减小桥接器管芯627的厚度。在实施例中，桥接器管芯627的表面652与模制层621的表面653可以基本上彼此共面。
现在参考图6E，示出了根据实施例的在将开口612形成到模制层621中之后的结构的横截面图。在实施例中，开口612暴露第一焊盘622的表面。开口612可以用激光钻孔工艺等形成。
现在参考图6F，示出了根据实施例的在将焊球613放置在开口612中之后的结构的截面图。在实施例中，焊球613可以至少部分地嵌入在模制层621中。即，焊球613的部分可以由模制层621围绕，并且可以使焊球613的部分暴露。
在施加焊球613之后，可以去除载体650。在去除载体650之后，可以将多芯片模块集成到电子系统(例如，上文所描述的电子系统)中。
现在参考图7A-7F，示出了根据实施例的描绘用于形成具有堆叠管芯的多芯片模块的过程的一系列截面图。如图7A-7F中所示，通过包括穿过桥接器管芯和/或基础管芯的TSV而使得堆叠式架构成为可能。在实施例中，图7A-7F中组装的多芯片模块可以用于上述电子系统200/300中的一个或多个中。
现在参考图7A，示出了根据实施例的载体750上的一对基础管芯725A和725B的截面图。第一基础管芯725A和第二基础管芯725B可以包括第一焊盘722和第二焊盘724。第一焊盘722可以具有大于第二焊盘724的第二间距的第一间距。在实施例中，可以在第一焊盘722之上提供诸如导电柱723的互连。例如，导电柱723可以包括铜。
在实施例中，载体750是具有高硬度的尺寸稳定的材料。载体750的一个目的是提供不易于翘曲的基底。因此，可以严格控制第一基础管芯725A、第二基础管芯725B与随后加入的桥接器管芯727之间的对准。在实施例中，载体750可以是玻璃或金属材料。在一些实施例中，载体可以包括硅。在所示的实施例中，第一基础管芯725A和第二基础管芯725B直接接触载体750。然而，应理解，临时粘合剂可以将基础管芯725A和725B固定到载体750。
现在参考图7B，示出了根据实施例的在将桥接器管芯727附接到基础管芯725A和725B之后的结构的截面图。在实施例中，可以使用倒装芯片安装等来附接桥接器管芯727。例如，焊料729可以将第二焊盘724固定到桥接器焊盘728。在其他实施例中，桥接器焊盘728可以使用铜与铜键合等直接连接到第二焊盘724。
在实施例中，桥接器管芯727在第一基础管芯725A和第二基础管芯725B之间提供高密度布线。例如，桥接器管芯727可以包括诸如硅的半导体衬底。桥接器管芯727上的细线和间距迹线(未示出)可以将第一基础管芯725A之上的桥接器焊盘728连接到第二基础管芯725B之上的桥接器焊盘728。在实施例中，桥接器管芯727可以包括TSV 714。TSV 714可以部分地穿过桥接器管芯727的厚度。
现在参考图7C，示出了根据实施例的在将模制层721设置在载体750之上之后的结构的截面图。在实施例中，模制层721可以用包覆成型工艺形成。模制层721可以包括环氧树脂等。
现在参考图7D，示出了根据实施例的在使模制层721凹陷之后的结构的截面图。在实施例中，利用研磨工艺等使模制层721凹陷。可以使模制层721凹陷以暴露导电柱723的表面和桥接器管芯727的背侧表面。在TSV 714不完全穿过图7C中的桥接器管芯727的厚度的一些实施例中，研磨工艺可以用于暴露TSV 714。在实施例中，研磨工艺可以包括减小桥接器管芯727和/或导电柱723的厚度。在实施例中，导电柱723的表面751、桥接器管芯727的表面752以及模制层721的表面753可以基本上彼此共面。
现在参考图7E，示出了根据实施例的在堆叠工艺期间的结构的截面图。如图所示，将第一多芯片模块720A翻转以在模制层721的底表面上提供桥接器管芯727。在从第一基础管芯725A和第二基础管芯725B去除载体750之后，第一多芯片模块720A可以类似于图7D中的结构。
在实施例中，第一多芯片模块720A附接到第二多芯片模块720B，如箭头所示。在实施例中，除了第一管芯725A和第二管芯725B具有TSV 708之外，第二多芯片模块720B可以基本上类似于第一多芯片模块720A。
现在参考图7F，示出了根据实施例的在将第一多芯片模块720A附接到第二多芯片模块720B之后的结构的截面图。在实施例中，可以在第一多芯片模块720A和第二多芯片模块720B之间提供背侧金属化和焊料(未示出)，以在两层之间提供电耦合。
现在参考图7G，示出了根据实施例的与图7B中的结构类似的结构的截面图。图7G中的结构与图7B中的结构的不同之处在于具有较薄的桥接器管芯727。在特定实施例中，桥接器管芯727可以具有导致顶表面在导电柱723的顶表面下方的厚度。
现在参考图7H，示出了根据实施例的在将模制层721设置在载体750之上之后的结构的截面图。在实施例中，模制层721可以用包覆成型工艺形成。模制层721可以包括环氧树脂等。
现在参考图7I，示出了根据实施例的在使模制层721凹陷之后的结构的截面图。在实施例中，利用研磨工艺等使模制层721凹陷。可以使模制层721凹陷以暴露导电柱723的表面。在实施例中，桥接器管芯727仍然可以嵌入在模制层721中。
现在参考图7J，示出了根据实施例的在使模制层721凹陷以在桥接器管芯727之上形成开口795之后的结构的截面图。在实施例中，开口795可以用激光烧蚀工艺等形成。在形成开口795之后，处理可以以基本上类似于关于图7E-7F描述的那些操作的操作继续，此处将不再重复。
现在参考图8A-8F，示出了根据实施例的描绘用于形成具有薄基础管芯和薄桥接器管芯的多芯片模块的过程的一系列截面图。特别地，本文描述的实施例提供了一种可以实现大约为30μm或更小的管芯厚度的工艺。在实施例中，图8A-8F中组装的多芯片模块可以用于上述电子系统200/300中的一个或多个中。
现在参考图8A，示出了根据实施例的载体850上的一对基础管芯825A和825B的截面图。第一基础管芯825A和第二基础管芯825B可以包括第一焊盘822和第二焊盘824。第一焊盘822可以具有大于第二焊盘824的第二间距的第一间距。在实施例中，可以在第一焊盘822之上提供诸如导电柱823的互连。例如，导电柱823可以包括铜。
在实施例中，载体850是具有高硬度的尺寸稳定的材料。载体850的一个目的是提供不易于翘曲的基底。因此，可以严格控制第一基础管芯825A、第二基础管芯825B和桥接器管芯827之间的对准。在实施例中，载体850可以是玻璃或金属材料。在一些实施例中，载体可以包括硅。在所示的实施例中，第一基础管芯825A和第二基础管芯825B直接接触载体850。然而，应理解，临时粘合剂可以将基础管芯825A和825B固定到载体850。
在实施例中，在第一基础管芯825A和第二基础管芯825B之上提供桥接器管芯827。桥接器管芯827提供第一基础管芯825A与第二基础管芯825B之间的电连接。在实施例中，可以在第一基础管芯825A、第二基础管芯825B和桥接器管芯827之上提供模制层821。
现在参考图8B，示出了根据实施例的在使模制层凹陷之后的结构的截面图。在实施例中，使模制层821凹陷还可以使导电柱823和桥接器管芯827凹陷。由于载体850的存在，该结构得到支撑并且能够被积极地减薄。例如，桥接器管芯827可以具有约100微米或更小、约50微米或更小、或约30微米或更小的厚度T1。
现在参考图8C，示出了根据实施例的在导电柱823上提供焊球831之后的结构的截面图。可以用任何适当的工艺来施加焊球831。
现在参考图8D，示出了根据实施例的在其被转移到第二载体860之后的结构的截面图。在实施例中，将该结构从第一载体850释放并翻转，使得焊球831面向第二载体860。在实施例中，该结构通过临时粘合层861粘附到第二载体860。
现在参考图8E，示出了根据实施例的在第二凹陷工艺之后的结构的截面图。在实施例中，第二凹陷工艺可以是研磨工艺，其凹陷第一基础管芯825A和第二基础管芯825B的厚度。例如，第一基础管芯825A和第二基础管芯825B可以具有第二厚度T2。在实施例中，第二厚度T2可以约为100μm或更小、约为50μm或更小、或约为30μm或更小。在实施例中，模制层821的背侧表面862可以与第一基础管芯825A和第二管芯825B的背侧表面863和864基本上共面。在凹陷之后，可以将增强层(未示出)(例如，胶带、散热器等)施加到背侧表面862、863、864以补偿由于模块的薄度而引起的翘曲。
现在参考图8F，示出了根据实施例的在去除第二载体860之后的结构的截面图。然后，可以将所得的多芯片模块820集成到电子系统(例如，上述电子系统)中。
现在参考图9A-9D，示出了根据实施例的基础管芯925A和925B的平面图。特别地，示出了第二焊盘924的结构。如将描述的，第二焊盘924的架构被形成为允许补偿基础管芯925A与925B之间的未对准。
现在参看图9A，示出了根据实施例的第一基础管芯925A和第二基础管芯925B的平面图。在实施例中，第一基础管芯925A上的第二焊盘924A和第二基础管芯925B上的第二焊盘924B可以是细长的。例如，第二焊盘924A和924B的长度可以大于第二焊盘924A和924B的宽度。在实施例中，第二焊盘924A和924B的长度方向可以相对于基础管芯925A和925B的边缘成角度。例如，第二焊盘924A可以处于第一角度θA，并且第二焊盘924B可以处于第二角度θB。在实施例中，第一角度θA可以是第二角度θB的镜像。当第一基础管芯925A与第二基础管芯925B完美对准时，桥接器管芯(未示出)上的互连970可以在其中点处着陆在第二焊盘924A和924B上。
现在参考图9B，示出了根据实施例的未对准的第一基础管芯925A和第二基础管芯925B的平面图。如图所示，第二基础管芯925B在垂直Y方向上移位。为了在第二焊盘924A和924B之间进行连接，将桥接器管芯(未示出)上的互连970移位到偏移位置970’，如箭头所示。
现参看图9C，示出了根据实施例的未对准的第一基础管芯925A和第二基础管芯925B的平面图。如图所示，第二基础管芯925B在水平X方向上移位。为了在第二焊盘924A和924B之间进行连接，将互连970垂直移位到位置970’，如箭头所示。
现参看图9D，示出了根据实施例的未对准的第一基础管芯925A和第二基础管芯925B的平面图。如图所示，第二基础管芯925B在水平X方向和垂直Y方向上移位。为了在焊盘924A和924B之间进行连接，桥接器管芯927可以具有成角度的互连970。或者，互连970可以正交于桥接器管芯927的边缘，并且桥接器管芯927本身可以旋转。
现在参考图10A和10B，示出了根据实施例的桥接器管芯1027的平面图。在实施例中，组装设施可以具有多个不同的桥接器管芯1027架构。每个架构可以解决基础管芯的不同未对准。例如，在图10A中，示出了具有彼此对准并且通过水平互连1070连接的桥接器焊盘1028A和1028B的桥接器管芯1027。这种桥接器管芯1027可以适于在基础管芯之间不存在未对准的情况。在图10B中，桥接器焊盘1028A和1028B未对准，并且通过成角度θ的互连1070连接。这种桥接器管芯1027可以适于在基础管芯之间在Y方向上存在未对准的情况。在附接基础管芯之后，可以确定存在特定的未对准并且可以选择适当的桥接器管芯1027。
在又一实施例中，桥接器管芯1027选项可以具有非一致的互连1070的长度。图10C中示出了这样的实施例。如图所示，互连1070A比互连1070B长。这种构造可以解决基础管芯1025中的一个或两个基础管芯的旋转和/或在一个以上的方向上的位移。
在图10D中单独示出了桥接器管芯1027。如图所示，桥接器管芯1027具有多个互连1070。互连1070A-D具有不一致的长度。例如，互连1070A是最短的长度，而互连1070D是最长的长度。
图11示出了根据本发明的一种实施方式的计算设备1100。计算设备1100容纳板1102。板1102可以包括多个部件，包括但不限于处理器1104和至少一个通信芯片1106。处理器1104物理地且电气地耦合到板1102。在一些实施方式中，至少一个通信芯片1106也物理地且电气地耦合到板1102。在另外的实施方式中，通信芯片1106是处理器1104的部分。
这些其他部件包括但不限于易失性存储器(例如，DRAM)、非易失性存储器(例如，ROM)、闪速存储器、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)设备、罗盘、加速度计、陀螺仪、扬声器、相机和大容量存储设备(例如，硬盘驱动器、光盘(CD)、数字多功能盘(DVD)等)。
通信芯片1106实现用于来往于计算设备1100传输数据的无线通信。术语“无线”和其派生词可以用于描述可以通过使用经调制的电磁辐射经由非固态介质来传递数据的电路、设备、系统、方法、技术、通信信道等。该术语并不意味着相关联的设备不包含任何导线，尽管在一些实施例中它们可以不包含。通信芯片1106可以实现多种无线标准或协议中的任何一种，包括但不限于Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE802.16系列)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其派生物、以及被指定为3G、4G、5G及之后的任何其他无线协议。计算设备1100可以包括多个通信芯片1106。例如，第一通信芯片1106可以专用于诸如Wi-Fi和蓝牙的较短距离的无线通信，并且第二通信芯片1106可以专用于诸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等的较长距离的无线通信。
计算设备1100的处理器1104包括封装在处理器1104内的集成电路管芯。在本发明的一些实施方式中，根据本文所述的实施例，处理器的集成电路管芯可以是具有通过桥接器管芯电耦合的一对基础管芯的多芯片模块的部分。术语“处理器”可以指处理来自寄存器和/或存储器的电子数据以将该电子数据转换为可以存储在寄存器和/或存储器中的其他电子数据的任何设备或设备的部分。
通信芯片1106也包括封装在通信芯片1106内的集成电路管芯。根据本发明的另一实施方式，根据本文所述的实施例，通信芯片的集成电路管芯可以是具有通过桥接器管芯电耦合的一对基础管芯的多芯片模块的部分。
以上对本发明的所示实施方式的描述(包括摘要中所描述的内容)不旨在是详尽无遗的或将本发明限于所公开的精确形式。虽然为了说明的目的本文描述了本发明的具体实施方式和示例，但是如相关领域的技术人员将认识到的，在本发明的范围内各种等同修改是可能的。
根据以上详细描述，可以对本发明进行这些修改。在所附权利要求中使用的术语不应被解释为将本发明限于在说明书和权利要求中公开的具体实施方式。相反，本发明的范围完全由所附权利要求确定，权利要求将根据权利要求解释的既定原则来解释。
示例1：一种电子封装，包括：模制层；第一管芯，嵌入在模制层中，其中第一管芯包括具有第一间距的第一焊盘和具有第二间距的第二焊盘；第二管芯，嵌入在模制层中，其中第二管芯包括具有第一间距的第三焊盘和具有第二间距的第四焊盘；以及桥接器管芯，嵌入在模制层中，其中桥接器管芯将第二焊盘电耦合到第四焊盘。
示例2：根据示例1所述的电子封装，其中第一管芯和第二管芯的背侧表面与模制层的表面基本上共面。
示例3：根据示例1或示例2所述的电子封装，其中桥接器管芯的背侧表面与模制层的表面基本上共面。
示例4：根据示例1-3所述的电子封装，还包括在第一焊盘和第三焊盘之上的导电互连。
示例5：根据示例4所述的电子封装，其中桥接器管芯的背侧表面与导电互连的表面基本上共面。
示例6：根据示例4所述的电子封装，还包括：在模制层之上并且连接到导电互连的再分布层。
示例7：根据示例1-6的所述电子封装，还包括：在第一管芯上的第五焊盘，其中第五焊盘具有小于第一间距的第三间距；以及附接到第五焊盘的第三管芯，其中第三管芯的背侧表面与桥接器管芯的背侧表面基本上共面。
示例8：根据示例1-7所述的电子封装，还包括：在第一焊盘和第三焊盘之上的焊球，其中焊球至少部分地嵌入在模制层中。
示例9：根据示例1-8所述的电子封装，还包括：穿过桥接器管芯的穿衬底过孔。
示例10：根据示例1-9所述的电子封装，其中第一管芯、第二管芯和桥接器管芯中的一个或多个的厚度为大约30μm或更小。
示例11：根据示例1-10所述的电子封装，其中第二焊盘是细长的并且相对于第一管芯的边缘成非正交的第一角度，并且其中第四焊盘是细长的并且相对于第二管芯的边缘成非正交的第二角度。
示例12：根据示例1-11所述的电子封装，还包括：第三管芯；第四管芯；以及多个桥接器管芯，其中多个桥接器管芯中的每一个将第一管芯、第二管芯、第三管芯和第四管芯中的两个耦合在一起。
示例13：一种电子封装，包括：多管芯模块，所述多管芯模块包括：模制层；第一管芯，嵌入在模制层中；第二管芯，嵌入在模制层中；以及桥接器件管芯，嵌入在模制层中，其中桥接器管芯将第一管芯电耦合到第二管芯；以及封装衬底，耦合到多管芯模块。
示例14：根据示例13所述的电子封装，其中多管芯模块通过互连耦合到封装衬底。
示例15：根据示例14所述的电子封装，其中封装衬底耦合到板。
示例16：根据示例13-15所述的电子封装，还包括：有源插入件、无源插入件、或多管芯模块与封装衬底之间的管芯。
示例17：根据示例16所述的电子封装，其中封装衬底耦合到板。
示例18：根据示例13-17所述的电子封装，还包括：在模制层之上的再分布层。
示例19：根据示例18所述的电子封装，其中封装衬底耦合到板。
示例20：一种电子系统，包括：板；以及多管芯模块，耦合到板，其中多管芯模块包括：模制层；第一管芯，嵌入在模制层中；第二管芯，嵌入在模制层中；以及桥接器管芯，嵌入在模制层中，其中桥接器管芯将第一管芯电耦合到第二管芯。
示例21：根据示例20所述的电子系统，还包括：在多管芯模块与板之间的封装衬底。
示例22：根据示例20或示例21所述的电子系统，还包括：在第一管芯和第二管芯上的导电柱。
示例23：根据示例22所述的电子系统，其中焊球在导电柱上。
示例24：根据示例22所述的电子系统，其中再分布层在导电柱上，并且其中焊球在再分布层上。
示例25：根据示例20-24所述的电子系统，还包括：在多芯片模块之上的第二多芯片模块。

Claims (20)

1.一种多芯片模块，包括：
再分布层；
桥接器管芯，具有顶侧和底侧，所述底侧在所述再分布层上并且与所述再分布层接触，并且所述桥接器管芯具有在所述顶侧和所述底侧之间的第一侧壁和第二侧壁，所述第一侧壁与所述第二侧壁横向相反，并且所述桥接器管芯在所述顶侧上具有桥接器焊盘，并且在所述桥接器焊盘上具有焊料；
模制层，在所述再分布层上且与所述再分布层接触并与所述桥接器管芯的所述第一侧壁和所述第二侧壁横向相邻，所述模制层具有与所述桥接器管芯的所述底侧处于相同水平的最底部表面；
第一导电柱，在所述模制层中并且与所述桥接器管芯的所述第一侧壁横向间隔开，所述第一导电柱具有在所述桥接器管芯的所述桥接器焊盘的最上表面之上的最上表面，并且所述第一导电柱电耦合到所述再分布层；
第二导电柱，在所述模制层中并且与所述桥接器管芯的所述第二侧壁横向间隔开，所述第二导电柱具有在所述桥接器管芯的所述桥接器焊盘的所述最上表面之上的最上表面，并且所述第二导电柱电耦合到所述再分布层；
第一管芯，在所述桥接器管芯上方并且在所述第一导电柱上方，所述第一管芯耦合到所述第一导电柱并且耦合到所述桥接器管芯的所述桥接器焊盘的第一部分；
第二管芯，在所述桥接器管芯上方并且在所述第二导电柱上方，所述第二管芯与所述第一管芯横向间隔开，并且所述第二管芯耦合到所述第二导电柱并耦合到所述桥接器管芯的所述桥接器焊盘的第二部分，所述再分布层横向延伸超过所述第一管芯的外侧以及所述第二管芯的外侧；以及
多个焊球，在所述再分布层下方并且耦合到所述再分布层，所述多个焊球在所述第一导电柱下方，在所述桥接器管芯下方，并且在所述第二导电柱下方。
2.根据权利要求1所述的多芯片模块，其中，所述模制层与所述桥接器管芯的所述第一侧壁和所述第二侧壁直接接触。
3.根据权利要求1所述的多芯片模块，其中，所述模制层具有在所述桥接器管芯的所述顶侧之上的最上表面。
4.根据权利要求1所述的多芯片模块，其中，所述模制层的所述最上表面处于与所述第一管芯的最上表面相同的水平，并且处于与所述第二管芯的最上表面相同的水平。
5.根据权利要求1所述的多芯片模块，其中，所述再分布层具有与所述模制层的边缘垂直对准的边缘。
6.根据权利要求5所述的多芯片模块，其中，所述再分布层具有与所述模制层的第二边缘垂直对准的第二边缘，所述再分布层的所述第二边缘与所述再分布层的所述边缘横向相反，并且所述模制层的所述第二边缘与所述模制层的所述边缘横向相反。
7.根据权利要求1所述的多芯片模块，其中，所述多个焊球的一部分在所述第一管芯和所述第二管芯的占用区域之外。
8.一种多芯片模块，包括：
用于间距扩展和集成的层；
第一管芯，在用于间距扩展和集成的所述层上方并且与用于间距扩展和集成的所述层接触，所述第一管芯具有第一桥接器焊盘和第二桥接器焊盘以及在所述第一桥接器焊盘和所述第二桥接器焊盘上的焊料；
模制层，在用于间距扩展和集成的所述层上方且与用于间距扩展和集成的所述层接触并与所述第一管芯的第一侧壁和第二侧壁横向相邻，所述模制层具有与所述第一管芯的底侧相同水平的最底部表面；
第一导电柱，在所述模制层中并且与所述第一管芯的所述第一侧壁横向间隔开，所述第一导电柱具有在所述第一桥接器焊盘和所述第二桥接器焊盘的最上表面之上的最上表面，并且所述第一导电柱电耦合到用于间距扩展和集成的所述层；
第二导电柱，在所述模制层中并且与所述第一管芯的所述第二侧壁横向间隔开，所述第二导电柱具有在所述第一桥接器焊盘和所述第二桥接器焊盘的所述最上表面之上的最上表面，并且所述第二导电柱电耦合到用于间距扩展和集成的所述层；
第二管芯，在所述第一管芯上方并且在所述第一导电柱上方，所述第二管芯耦合到所述第一导电柱并耦合到所述第一桥接器焊盘；
第三管芯，在所述第一管芯上方并且在所述第二导电柱上方，所述第三管芯与所述第一管芯横向间隔开，并且所述第三管芯耦合到所述第二导电柱并耦合到所述第二桥接器焊盘，用于间距扩展和集成的所述层横向延伸超过所述第二管芯的外侧以及所述第三管芯的外侧；以及
在所述第一导电柱下方的第一焊球，在所述第一管芯下方的第二焊球，以及在所述第二导电柱下方的第三焊球。
9.根据权利要求8所述的多芯片模块，其中，所述模制层与所述第一管芯的所述第一侧壁和所述第二侧壁直接接触。
10.根据权利要求8所述的多芯片模块，其中，所述模制层具有在所述第一管芯的所述顶侧之上的最上表面。
11.根据权利要求8所述的多芯片模块，其中，所述模制层的所述最上表面处于与所述第二管芯的最上表面相同的水平，并且处于与所述第三管芯的最上表面相同的水平。
12.根据权利要求8所述的多芯片模块，其中，用于间距扩展和集成的所述层具有与所述模制层的第一边缘垂直对准的第一边缘，并且其中，用于间距扩展和集成的所述层具有与所述模制层的第二边缘垂直对准的第二边缘，用于间距扩展和集成的所述层的所述第二边缘与用于间距扩展和集成的所述层的所述第一边缘横向相反，并且所述模制层的所述第二边缘与所述模制层的所述第一边缘横向相反。
13.根据权利要求8所述的多芯片模块，还包括在所述第二管芯和所述第三管芯的占用区域之外的第四焊球。
14.一种多芯片模块，包括：
再分布层；
桥接器管芯，具有顶侧和底侧，所述底侧在所述再分布层上并且与所述再分布层接触，并且所述桥接器管芯具有在所述顶侧和所述底侧之间的第一侧壁和第二侧壁，所述第一侧壁与所述第二侧壁横向相反，并且所述桥接器管芯在所述顶侧上具有桥接器焊盘，并且在所述桥接器焊盘上具有焊料；
模制层，在所述再分布层上且与所述再分布层接触并与所述桥接器管芯的所述第一侧壁和所述第二侧壁横向相邻，所述模制层具有与所述桥接器管芯的所述底侧处于相同水平的最底部表面；
导电柱，在所述模制层中并且与所述桥接器管芯的所述第一侧壁横向间隔开并且与所述桥接器管芯的所述第二侧壁横向间隔开，所述导电柱具有在所述桥接器焊盘的最上表面之上的最上表面，并且所述导电柱电耦合到所述再分布层；
第一管芯，在所述桥接器管芯上方并且在所述导电柱的第一部分上方，所述第一管芯耦合到所述导电柱的所述第一部分并且耦合到所述桥接器焊盘的第一部分；
第二管芯，在所述桥接器管芯上方并且在所述导电柱的第二部分上方，所述第二管芯与所述第一管芯横向间隔开，并且所述第二管芯耦合到所述导电柱的所述第二部分并耦合到所述桥接器焊盘的第二部分，所述再分布层横向延伸超过所述第一管芯的外侧以及所述第二管芯的外侧；以及
焊球，在所述再分布层下方并且耦合到所述再分布层，所述焊球在所述导电柱下方，并且在所述桥接器管芯下方。
15.根据权利要求14所述的多芯片模块，其中，所述模制层与所述桥接器管芯的所述第一侧壁和所述第二侧壁直接接触。
16.根据权利要求14所述的多芯片模块，其中，所述模制层具有在所述桥接器管芯的所述顶侧之上的最上表面。
17.根据权利要求14所述的多芯片模块，其中，所述模制层的所述最上表面处于与所述第一管芯的最上表面相同的水平，并且处于与所述第二管芯的最上表面相同的水平。
18.根据权利要求14所述的多芯片模块，其中，所述再分布层具有与所述模制层的边缘垂直对准的边缘。
19.根据权利要求14所述的多芯片模块，其中，所述再分布层具有与所述模制层的第二边缘垂直对准的第二边缘，所述再分布层的所述第二边缘与所述再分布层的所述边缘横向相反，并且所述模制层的所述第二边缘与所述模制层的所述边缘横向相反。
20.根据权利要求14所述的多芯片模块，其中，所述焊球的一部分在所述第一管芯和所述第二管芯的占用区域之外。
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