TW202418502A - 用於ｉｃ晶片的異質嵌套中介層封裝 - Google Patents

用於ｉｃ晶片的異質嵌套中介層封裝 Download PDF

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TW202418502A
TW202418502A TW112150203A TW112150203A TW202418502A TW 202418502 A TW202418502 A TW 202418502A TW 112150203 A TW112150203 A TW 112150203A TW 112150203 A TW112150203 A TW 112150203A TW 202418502 A TW202418502 A TW 202418502A
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Taiwan
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interposer
die
bump
mold layer
nested
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TW112150203A
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English (en)
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迪班卓 馬里克
拉文德納斯 馬哈加
羅伯特 杉克曼
蕭納 力芙
斯里尼斯 佩安巴恩
巴拉梅 彭梅查
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美商英特爾股份有限公司
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Publication of TW202418502A publication Critical patent/TW202418502A/zh

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Abstract

本文揭露的實施例包含電子封裝及製造電子封裝的方法。在一實施例中，電子封裝包括：中介層，其中空腔穿過中介層，以及在空腔中的嵌套組件。在一實施例中，電子封裝還包括藉由第一互連耦接到中介層並且藉由第二互連耦接到嵌套組件的晶粒。在一實施例中，第一和第二互連包括第一凸塊、在第一凸塊之上的凸塊墊以及在凸塊墊之上的第二凸塊。

Description

用於ＩＣ晶片的異質嵌套中介層封裝
本發明的實施例涉及電子封裝，且更具體地，涉及帶有附接到中介層的一或多個晶粒以及嵌入在中介層的空腔中的一或多個組件的多晶片封裝架構。
對於提高性能和降低外型尺寸的需求推動封裝架構向多晶片整合架構發展。多晶片整合允許將在不同製程節點上製造的晶粒實現為單個電子封裝。然而，當前的多晶片架構會導致較大的外形尺寸，因而不適用於某些使用案例，或為使用者所不想要的。
及
依據多個實施例，本文描述具有異質嵌套中介層封裝的多晶片封裝架構以及形成這種電子封裝的方法。在以下的描述中，將使用本領域技術人員通常使用的用詞來描述說明性實施方式的各種態樣，以便將其工作的本質傳達給本領域其他技術人員。然而，對於本領域技術人員顯而易見的是，本發明可以僅帶有所描述的一些態樣來實現。為了解釋之目的，提出了具體的數字、材料以及配置，以便提供對說明性實施方式的徹底瞭解。然而，對於本領域技術人員顯而易見的是，本發明可以不具有特定的細節而仍能夠實現。在其他情況下，省略或簡化眾所周知的特徵，以免模糊說明性的實施方式。
各種操作將被描述為多個分開地操作，依序以理解本發明最有幫助的方式描述，然而，描述的順序不應被解釋為意味這些操作必需是依序的。特別是，這些操作不需要按照所呈現的順序實施。
如上所述，當前的封裝解決方案開始使用多晶粒架構。然而，在單個封裝中包含多個晶粒並非沒有問題。現有的多晶粒架構除了覆蓋區較大之外，此類系統還有低良率及低可靠性的問題。特別地，當使用傳統的封裝基板時，由於翹曲和其他對準問題，晶粒之間的互連是困難的。因此，本文揭露的實施例包含利用異質嵌套中介層的電子封裝。
異質嵌套中介層，例如本文所述的中介層，包含具有一或多個空腔的中介層。嵌套組件可設置在空腔中。一或多個晶粒可以藉由互連連接到中介層和嵌套組件。在一實施例中，互連包含與上方及下方的凸塊(例如，焊料凸塊)對接的凸塊墊。凸塊墊的使用允許中介層或嵌套組件與晶粒之間進行自對準。因此，即使當使用細間距互連時(例如，當嵌套組件是兩個晶粒之間的架橋時)，實施例也能夠有高產量和高可靠性。
現在參考圖1A，示出依據一實施例的電子封裝100的截面圖。在一實施例中，電子封裝100可以包括中介層130和嵌套組件140。嵌套組件140設置於穿過中介層130的空腔135內。嵌套組件140被稱為「嵌套」，因為組件140被放置在空腔135中。即，嵌套組件140被中介層130的部分圍繞。在所示的實施例中，中介層130中顯示為單一空腔135。然而，應當理解，取決於裝置，可使用任何數量的空腔135。以下更詳細地提供多個空腔135的範例。在所示的實施例中，顯示在空腔135中的單一嵌套組件140。然而，應當理解，任何數量的嵌套組件140可被設置於單一空腔135中。以下更詳細地提供單一空腔135中的多個嵌套組件140的範例。
在一實施例中，中介層130可以是任何合適的基板材料。舉例而言，中介層130可以包括玻璃、陶瓷、半導體材料(例如，高或低電阻率的矽，III-V半導體等)、有機基板(高密度互連(high density interconnect；HDI)基板、嵌入式跡線基板(embedded trace substrate；ETS)、高密度封裝(high density package；HDP)基板、模製基板等)。在一些實施例中，中介層130是被動裝置。即，中介層130可以僅包含被動組件(例如，跡線、通孔等)。舉例而言，中介層130可包括通孔134，通孔134在中介層130下方的墊133與中介層130上方的墊136之間提供連接。在其他實施例中，中介層130可以是主動中介層。即，中介層130可包括主動裝置(例如，電晶體等)。
在一實施例中，嵌套組件140可以是主動或被動組件。舉例而言，主動嵌套組件140可以包括邏輯裝置、類比/RF裝置、I/O電路、記憶體裝置、電壓調節器、感測器等。被動嵌套組件140可以包括高密度多晶粒互連架橋晶粒、電容器、電感器、電阻器、熱電冷卻器、高速連接器等。在所示的實施例中，嵌套組件140包括主動表面141。雖然被稱為「主動」表面141，但是應當理解，主動表面141可以包括完全被動特徵。在一實施例中，嵌套組件140可以包括貫穿組件通孔(through component via；TCV)144。TCV 144可以將主動表面141電性耦接到嵌套組件140的背側上的墊143。
在一實施例中，中介層130和嵌套組件140可以藉由底部填充材料131及/或模具層132嵌入。在一實施例中，中介層130的墊133和嵌套組件140的墊143可以藉由設置在穿過模具層132的部分的開口中的凸塊137接觸。在一實施例中，凸塊137可以被稱為「封裝側凸塊」(package side bump；PSB)。PSB可以與封裝基板(圖未示)接合。
在一實施例中，電子封裝100更包括一或多個嵌入在模具層122中的晶粒120。在一實施例中，晶粒120的主動表面121可以電性耦接到中介層130和嵌套組件140。舉例而言，互連181提供晶粒120與中介層130之間的電性連接，並且互連182提供晶粒120與嵌套組件140之間的電性連接。在一實施例中，互連181可以具有與互連182不同的間距。舉例而言，互連182可以具有比互連181小的間距。在所示的實施例中，嵌套組件140是架橋，架橋在兩個晶粒120之間提供電性連接。
現在參考圖1B，示出依據一實施例的電子封裝100的放大部分180。部分180更清楚說明互連181和182的架構。如圖所示，互連181和182實質上彼此相似，除了互連182的寬度小於互連181的寬度。在一實施例中，互連包括凸塊墊184。凸塊墊184可以是導電材料，例如銅。凸塊183可設置於凸塊墊184之上，並且凸塊185可設置於凸塊墊184下方。凸塊183、185可以是焊料凸塊等。在一實施例中，凸塊183可以與晶粒120的墊123接合。凸塊185可以與中介層130的墊136或與嵌套組件140的墊146接合。
凸塊墊184的使用增進晶粒120與中介層130之間以及晶粒120與嵌套組件140之間的對準。這是因為晶粒120藉由焊料凸塊183而與凸塊墊184自對準，並且中介層130和嵌套組件140藉由焊料凸塊185而與凸塊墊184自對準。即，凸塊墊184提供定位給所有自對準的組件。由於晶粒120、中介層130和嵌套組件140自對準相同的特徵，因此晶粒120精確對準中介層130和嵌套組件140。
現在參考圖2A，示出依據另一實施例的電子封裝200的截面圖。在一實施例中，電子封裝200可以與圖1A中的電子封裝100實質上相似，除了在中介層230中提供複數個嵌套組件240之外。如圖所示，第一嵌套組件240 A位於中介層230的第一空腔235 A中，第二嵌套組件240 B位於第二空腔235 B中。在一實施例中，第一空腔235 A可以橫跨兩個晶粒220之間。即，第一空腔可以部分地在兩個晶粒220的覆蓋區內。因此，兩個晶粒220皆可存取第一嵌套組件240 A。舉例而言，第一嵌套組件240 A可以是將晶粒220電性耦接在一起的架橋。在一實施例中，第二空腔235 B可以完全在晶粒220之一者的覆蓋區內。在這樣的實施例中，第二嵌套組件240 B可能僅其中一個晶粒220可存取。
現在參考圖2B，示出依據另一實施例的電子封裝200的截面圖。在一實施例中，圖2B中的電子封裝200可以與圖2A中的電子封裝200實質上相似，除了第一嵌套組件240 A不包含TCV 244之外。在一些實施例中，第一嵌套組件240 A可以包括虛設球237'。即，在一些實施例中，虛設球237'可以不電性連接到封裝200的電路，而僅用作機械支撐，而球237提供機械支撐並且電性連接到封裝200的電路。在這樣的實施例中，嵌套組件240 A可以經由嵌套組件240 A的上側間接地穿過晶粒220從封裝基板(圖未示)供應電源或信號。
現在參考圖2C，示出依據一實施例的電子封裝200的截面圖。在一實施例中，圖2C中的電子封裝200可以與圖2A中的電子封裝200實質上相似，除了第二嵌套組件240 B面向不同的方向之外。舉例而言，第二嵌套組件240 B可具有背向晶粒220的主動表面241。
現在參考圖2D，示出依據另一實施例的電子封裝200的截面圖。在一實施例中，圖2C中的電子封裝200可以與圖2A中的電子封裝200實質上相似，除了位於第二空腔235 B中的第二嵌套組件240 B的堆疊之外。在一實施例中，第二嵌套組件240 B的堆疊可以包括記憶體晶粒或任何其他可堆疊組件的堆疊。
現在參考圖2E，示出依據一實施例的電子封裝200的截面圖。在一實施例中，電子封裝件200可以包括中介層230、中介層230中的空腔235中的嵌套組件240以及附接到嵌套組件240和中介層230的一或多個晶粒220。在一實施例中，嵌套組件240及/或中介層230可以包括一或多個再分配層251、252。舉例而言，再分配層251可以在嵌套組件240和中介層230上方(即，面對晶粒220)，並且再分配層252可以在嵌套組件240和中介層230下方。儘管在嵌套組件240和中介層230兩者上都顯示再分配層251、252，但應當理解，在一些實施例中，再分配層251、252可以僅在嵌套組件240及中介層230之一上。此外，儘管在嵌套組件240和中介層230的頂表面和底表面上都顯示再分配層251、252，但應當理解，在一些實施例中，再分配層251或再分配層252可以僅在嵌套組件240及/或中介層230之一表面上。
現在參考圖2F，示出依據另一實施例的電子封裝200的截面圖。在一實施例中，電子封裝200可以與圖2E中的電子封裝200實質上相似，除了再分配層253和再分配層254設置於不同的位置。舉例而言，再分配層253可位於凸塊285與凸塊283之間及/或再分配層254可以位於中介層230的墊233及嵌套組件240的墊243下方。在再分配層253位於凸塊285與凸塊283之間的情況下，應當理解，凸塊墊可以被整合到再分配層254中。儘管在圖2F中的顯示再分配層253及254位於兩個位置，但應當理解，在一些實施例中，可以僅使用一再分配層253或254。在圖2E及2F中，示出各種再分配層251~254。然而，應當理解，實施例可以包含任何數量的再分配層251~254或其組合，或在圖2E及2F中未示出的其他位置中的再分配層。
現在參考圖3A，示出依據一實施例的電子封裝300的平面圖。在一實施例中，電子封裝300包括具有多個空腔335 A~E的中介層330。在一實施例中，複數個嵌套組件340設置於空腔335中。在一些實施例中，空腔335中的至少一個包括複數個嵌套組件340。舉例而言，兩個嵌套組件340設置於空腔335 B中。在一實施例中，空腔335可完全在晶粒320的覆蓋區內(由虛線表示)、在一個以上的晶粒320的覆蓋區內及/或部分在單一晶粒320的覆蓋區內。舉例而言，空腔335 A和335 B完全在晶粒320 A的覆蓋區內，空腔335 C在晶粒320 A和320 B的覆蓋區內，空腔335 E在晶粒320 A和320 C的覆蓋區內，並且空腔335 D部分在晶粒320 B的覆蓋區內。
現在參考圖3B，示出依據一實施例的圖3A中的電子封裝300沿線B-B’的截面示意圖。在所示的實施例中，中介層330顯示為在空腔335 A、335 C和335 D內具有嵌套組件340。中介層330和嵌套組件340可以藉由包括凸塊墊384的層的互連電性耦接到晶粒320 A和320 B。為簡單起見，示意性地示出晶粒320 A、320 B與中介層330和嵌套組件340之間的凸塊墊384。然而，應當理解，凸塊墊384可以是互連的一部分，該互連實質上相似於以上關於圖1B描述的互連181和182。在一實施例中，中介層330和嵌套組件340的底表面可以電性耦接到封裝側凸塊337。
現在參考圖3C，示出依據一實施例的圖3A中的電子封裝300沿線C-C’的截面示意圖。在所示的實施例中，中介層330顯示為在空腔335 B和335 E內具有嵌套組件340。中介層330和嵌套組件340可以藉由包括凸塊墊384的層的互連電性耦接到晶粒320 A和320 B。為簡單起見，示意性地示出晶粒320 A、320 B與中介層330和嵌套組件340之間的凸塊墊384。然而，應當理解，凸塊墊384可以是互連的一部分，該互連實質上相似於以上關於圖1B描述的互連181和182。在一實施例中，中介層330和嵌套組件340的底表面可以電性耦接到封裝側凸塊337。
現在參考圖4，示出依據一實施例的電子封裝400的平面圖。在一個實施例中，電子封裝400可以包括複數個中介層430 A~D。每個中介層430可以是任何形狀。舉例而言，中介層430顯示為是直線的。中介層430可以佈置成使得中介層430的側壁定義空腔435。在一實施例中，一或多個嵌套組件440可以設置於空腔435中。在一實施例中，可在中介層430和嵌套組件440上方提供一或多個晶粒420(以虛線表示)。每個晶粒420可以在一或多個中介層430之上延伸。
在一實施例中，每個中介層430可以彼此實質上相似。舉例而言，每個中介層430可以是被動中介層430或主動中介層430。在其他實施例中，中介層430可以不全部相同。舉例而言，一或多個中介層430可以是主動中介層430，並且一或多個中介層430可以是被動中介層。
現在參考圖5A-5M，示出依據一實施例的描述用於形成具有異質嵌套中介層的電子封裝的製程的一系列截面圖。
現在參考圖5A，示出依據一實施例的具有凸塊585的第一載體591的截面圖。在一實施例中，第一載體591可以是任何合適的載體基板，例如玻璃等。在一實施例中，導電層512可以藉由黏著劑511黏附到第一載體591。可以在導電層512之上形成複數個凸塊墊584。舉例而言，凸塊墊584可以藉由微影定義的抗蝕層(圖未示)和電鍍製程(例如，電鍍)形成。據此，由於凸塊墊584是藉由單一圖案化製程形成的，因此凸塊墊584相對於彼此的對準將是極好的。在一實施例中，凸塊墊584可以包含不同尺寸的凸塊墊584，以便適應不同的特徵。舉例而言，較大的凸塊墊584可以容納中介層，而較小的凸塊墊584可以容納嵌套組件。在一實施例中，可以將凸塊585設置在每個凸塊墊584的頂表面之上。舉例而言，凸塊585可以是焊料凸塊等。
現在參考圖5B，示出依據一實施例的在將中介層530和嵌套組件540附接到凸塊墊584之後的截面圖。在一實施例中，中介層530可以包括將中介層530的第一表面上的墊533連接到中介層530的第二表面上的墊536的通孔534。在一實施例中，嵌套組件540可以被設置在中介層的空腔535內。在一實施例中，嵌套組件540可以具有主動表面541和貫穿組件通孔544。在所示的實施例中，主動表面541面對第一載體591。然而，應當理解，在其他實施例中，主動表面541可以背對第一載體591。在其他實施例中，嵌套組件540可以不具有貫穿組件通孔544。嵌套組件可以在第一表面上具有墊543，且在第二表面上具有墊546。
在一實施例中，嵌套組件540的墊546和中介層530的墊536可以電性耦接至凸塊墊584。由於墊546和536藉由凸塊585耦接至凸塊墊584，因此它們與凸塊墊584自對準。如此一來，嵌套組件540和中介層530之間的對準具有彼此之間極好的對準。在一實施例中，可以先附接嵌套組件540，接著附接中介層530，或是可以先附接中介層530，接著附接嵌套組件540。
在所示的實施例中，在第一載體591上顯示單一中介層530和嵌套組件540。然而，應當理解，第一載體591可以是面板級、子面板級、晶圓級等的載體，在其上實質上平行地製造了複數個電子封裝。
現在參考圖5C，示出依據一實施例的在中介層530和嵌套組件540周圍設置底部填充材料531之後的截面圖。底部填充材料531可以藉由任何合適的製程來施配。
現在參考圖5D，示出依據一實施例的在嵌套組件540和中介層530之上設置模具層532之後的截面圖。據此，嵌套組件540和中介層530可以藉由底部填充材料531和模具層532的組合而實質上嵌入。模具層532可以是構建膜、阻焊劑疊合層或模塑料。在一些實施例中，可以將模具層532平坦化(例如，利用化學機械研磨(chemical mechanical polishing；CMP)製程)。在一實施例中，模具層532可以是與底部填充材料531不同的材料。因此，在一些實施例中，底部填充材料531和模具層532之間的接縫可能是可見的。
現在參考圖5E，示出依據一實施例的在將第二載體592附接到模具層532之後的截面圖。在一實施例中，第二載體592可以藉由黏著劑513等附接到模具層532。第二載體592可以是玻璃載體或任何其他合適的載體基板。
現在參考圖5F，示出依據一實施例的在移除第一載體591之後的截面圖。如圖所示，移除第一載體591和黏著劑511導致導電層512被暴露。
現在參考圖5G，示出依據一實施例的在移除導電層512之後的截面圖。在一實施例中，可以藉由磨光法、蝕刻製程或任何其他合適的製程來移除導電層512。移除導電層512使凸塊墊584的表面暴露。
現在參考圖5H，示出依據一實施例的在組件被翻轉之後的截面圖。此時，將凸塊墊584定向成使得暴露的表面面向上。
現在參考圖5I，示出依據一實施例的在將晶粒520附接到中介層530和嵌套組件540之後的截面圖。在一實施例中，晶粒520包括面向凸塊墊584的主動表面521。在一實施例中，嵌套組件540可以是將晶粒520電性耦接在一起的架橋。
在一實施例中，晶粒520可以藉由凸塊583電性耦接到凸塊墊584。舉例而言，凸塊583可以是焊料凸塊。如圖所示，凸塊墊584的相對表面被凸塊583、585覆蓋。這在晶粒520與中介層530之間提供了互連，互連包括墊523、凸塊583、凸塊墊584、凸塊585及墊536，並且在晶粒520與嵌套組件540之間提供了互連，互連包括墊523、凸塊583、凸塊墊584、凸塊585及墊546。由於使用焊料凸塊，因此晶粒520與凸塊墊584自對準。因此，晶粒520、中介層530和嵌套組件540全部自對準至單個特徵(即，凸塊墊584)。這在晶粒520與中介層530與嵌套組件540之間提供了極好的對準。
現在參考圖5J，示出依據一實施例的在晶粒520之上設置模具層522之後的截面圖。在一個實施例中，模具層522也可以包括底部填充材料(圖未示)。在一實施例中，模具層522可以是凹陷的(例如，藉由CMP製程等)以便暴露晶粒520的背側表面。
現在參考圖5K，示出依據一實施例的在移除第二載體592之後的截面圖。在一實施例中，第二載體592的移除暴露了模具層532在組件的封裝側上的部分。
現在參考圖5L，示出依據一實施例的在將開口596形成到模具層532中以分別暴露中介層530的封裝側墊533和543以及嵌套組件540之後的截面圖。在一實施例中，開口596可以藉由雷射鑽孔製程或光微影製程形成。
現在參考圖5M，示出依據一實施例的在將凸塊537設置在開口596中之後的截面圖。凸塊537可以被稱為封裝側凸塊(package side bump；PSB)，因為它們將與封裝基板(圖未示)對接。然而，應當理解，可以使用其他互連架構(例如，LGA、PGA、PoINT、eWLB等)代替所示的BGA架構中的凸塊537。在一實施例中，可以在PSB 537形成之後(或之前)，將個別的電子封裝與面板級組件分離。
現在參考圖6，示出依據一實施例的電子系統670的截面圖。在一實施例中，電子系統670可包括板材671(例如，印刷電路板(printed circuit board；PCB)，板材671藉由互連672耦接到封裝基板673。互連672顯示為焊料凸塊。然而，應當理解，可以使用任何互連架構。在一實施例中，電子系統670可以包括電子封裝600，電子封裝600藉由封裝側凸塊637耦接到封裝基板673。
電子封裝600可以與上述電子封裝實質上相似。舉例而言，電子封裝可以包括中介層630和一或多個嵌套組件640。一或多個晶粒620可以藉由互連電性耦接到中介層630和嵌套組件640，互連包括在相對表面上具有凸塊683、685的凸塊墊684。在一實施例中，底部填充材料674可以圍繞封裝側凸塊637。
圖7說明依據本發明之一實施方式的計算裝置700。計算裝置700容置板材702。板材702可包含數個組件，包含但不限於處理器704以及至少一通訊晶片706。處理器704物理性及電性耦接至板材702。在一些實施方式中，至少一通訊晶片706也物理性及電性耦接至板材702。在進一步的實施方式中，通訊晶片706是處理器704的部分。
這些其他組件包含，但不限於，揮發性記憶體(例如，DRAM)、非揮發性記憶體(例如，ROM)、快閃記憶體、圖形處理器、數位信號處理器、密碼處理器、晶片組、天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池、音頻編解碼器、視訊編解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、加速器、陀螺儀、揚聲器、相機以及大量儲存裝置(例如硬碟機、光碟(CD)、數位光碟(DVD)等)。
通訊晶片706使得用於至計算裝置700或來自計算裝置700之資料傳送之無線通訊能夠實現。用詞「無線」及其衍生物可用於描述電路、裝置、系統、方法、技術、通訊通道等，其可藉由使用穿過非固體介質的調變電磁輻射來傳遞資料。此用詞並不意味著關聯的裝置不包含任何電線，儘管在某些實施例中可能沒有。通訊晶片706可實現任何數目的無線標準或協定，包含但不限於Wi-Fi(IEEE 802.11家族)、WiMAX(IEEE 802.16家族)、IEEE 802.20、長期演進(long term evolution；LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙、及其衍生物，以及任何其他指定用作3G、4G、5G及在此之後之技術的無線協定。計算裝置700可包含複數個通訊晶片706。舉例而言，第一通訊晶片706可專用於較短範圍的無線通訊，例如Wi-Fi和藍牙，而第二通訊晶片706可專用於較長範圍的無線通訊，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他。
計算裝置700的處理器704包含封裝在處理器704內的積體電路晶粒。在本發明的一些實施方式中，處理器的積體電路晶粒可以被封裝在電子系統中，電子系統包括具有中介層和嵌套組件的多晶片封裝，中介層和嵌套組件藉由包括凸塊墊的互連耦接到一或多個晶粒，凸塊墊在凸塊墊相對表面上具有凸塊，依據本文所述的實施例。用詞「處理器」可以指處理來自暫存器及/或記憶體的電子資料以便將該電子資料轉變成其他可儲存在暫存器及/或記憶體中的電子資料的任何裝置或裝置的部分。
通訊晶片706還包含封裝在通訊晶片706內的積體電路晶粒。依據本發明的其他實施方式，通訊晶片的積體電路晶粒可以被封裝在電子系統中，電子系統包括具有中介層和嵌套組件的多晶片封裝，中介層和嵌套組件藉由包括凸塊墊的互連耦接到一或多個晶粒，凸塊墊在凸塊墊相對表面上具有凸塊，依據本文所述的實施例。
以上說明本發明的實施方式的描述，包含在摘要中的描述，並非意圖耗盡或限制本發明至所揭露的精確態樣。本文所描述的本發明的精確的實施方式及範例用於說明目地，因而相關領域具有通常知識者將認可，各種等同的修改可以落入本發明之範圍。
可以根據以上詳細描述對本發明進行這些修改。以下申請專利範圍中使用的術語不應當被理解為限制本發明在說明書和申請專利範圍中所揭露的具體實施方式。相反的，本發明的範圍完全是由以下申請專利範圍來判斷，並且是依據申請專利範圍解釋的既定原則來理解。
範例1：一種電子封裝，包括：中介層，其中，空腔穿過該中介層；在該空腔中的嵌套組件；以及藉由第一互連耦接到該中介層且藉由第二互連耦接到該嵌套組件的晶粒，其中，該第一互連和該第二互連包括：第一凸塊；在該第一凸塊之上的凸塊墊；以及在該凸塊墊之上的第二凸塊。
範例2：如範例1之電子封裝，其中，該第一互連的該凸塊墊與該第二互連的該凸塊墊實質上共面。
範例3：如範例1或範例2之電子封裝，其中，該嵌套組件和該中介層嵌入在底部填充層和第一模具層中。
範例4：如範例3之電子封裝，其中，該晶粒被嵌入第二模具層中。
範例5：如範例1~4之電子封裝，其中，該空腔完全在該晶粒的覆蓋區內。
範例6：如範例1~4之電子封裝，其中，該空腔的第一部分在該晶粒的覆蓋區內，並且其中，該空腔的第二部分在該晶粒的該覆蓋區外。
範例7：如範例1~6之電子封裝，其中，貫穿組件通孔延伸通過該嵌套組件。
範例8：如範例1~7之電子封裝，其中，該嵌套組件是被動組件。
範例9：如範例1~7之電子封裝，其中，該嵌套組件是主動組件。
範例10：如範例1~9之電子封裝，更包括：第二晶粒，其中，該第二晶粒藉由第三互連耦接到該嵌套組件，該第三互連包括：第一凸塊；在該第一凸塊之上的凸塊墊；以及在該凸塊墊之上的第二凸塊。
範例11：如範例10之電子封裝，其中，該嵌套組件將該第一晶粒電性耦接到該第二晶粒。
範例12：如範例1~11之電子封裝，更包括：在該空腔中的第二嵌套組件。
範例13：如範例1~12之電子封裝，其中，該嵌套組件的主動表面背對該晶粒。
範例14：如範例1~13之電子封裝，其中，該嵌套組件包括複數個堆疊晶粒。
範例15：如範例1~14之電子封裝，其中，該中介層包括複數個離散中介層基板，其中，該等離散中介層基板的邊緣定義該空腔。
範例16：如範例1~15之電子封裝，其中，該中介層包括玻璃、陶瓷、矽或有機材料。
範例17：如範例1~16之電子封裝，更包括一或多個再分配層，其中該一或多個再分配層位於該中介層的頂表面之上、該中介層的底表面之上、該嵌套組件的頂表面之上、該嵌套組件的底表面之上、嵌入該中介層及該嵌套組件的模具層之上及/或該第一凸塊與該第二凸塊之間。
範例18：一種電子系統，包括：板材；封裝基板，電性耦接到該板材；中介層，電性耦接到該封裝基板，其中，該中介層包括空腔；在該空腔中的嵌套組件，其中該嵌套組件電性耦接到該封裝基板；第一晶粒，藉由互連電性耦接到該中介層和該嵌套組件；以及第二晶粒，藉由該互連電性耦接到該中介層和該嵌套組件，其中，該互連包括：第一凸塊；在該第一凸塊之上的凸塊墊；以及在該凸塊墊之上的第二凸塊。
範例19：如範例18之電子系統，其中，該嵌套組件將該第一晶粒電性耦接到該第二晶粒。
範例20：如範例18或19之電子系統，其中，該嵌套組件是被動組件。
範例21：如範例18或19之電子系統，其中，該嵌套組件是主動組件。
範例22：如範例18~21之電子系統，其中，該嵌套組件包括複數個堆疊晶粒。
範例23：一種形成電子封裝的方法，包括：在第一載體上形成第一凸塊墊和第二凸塊墊，其中，第一凸塊設置在該第一凸塊墊和該第二凸塊墊之上；將中介層附接到該第一凸塊墊，其中，該中介層包括空腔；將嵌套組件附接到該第二凸塊墊，其中，該嵌套組件在該中介層的該空腔內；在該中介層和該嵌套組件之上施加模具層；將第二載體附接到該模具層；移除該第一載體；暴露該第一凸塊墊和該第二凸塊墊之與該第一凸塊相反的表面；以及藉由第二凸塊將晶粒附接到該第一凸塊墊和該第二凸塊墊。
範例24：如範例23之方法，更包括：在該晶粒之上施加第二模具層；以及移除該第二載體。
範例25：如範例24之方法，更包括：將互連附接到該中介層和該嵌套組件。
100:電子封裝 120:晶粒 121:主動表面 122:模具層 123:墊 130:中介層 131:底部填充材料 132:模具層 133:墊 134:通孔 135:空腔 136:墊 137:凸塊 140:嵌套組件 141:主動表面 143:墊 144:貫穿組件通孔 146:墊 180:部分 181:互連 182:互連 183:凸塊 184:凸塊墊 185:凸塊 200:電子封裝
[圖1A]是依據一實施例的包括異質嵌套中介層的電子封裝的截面圖。 [圖1B]是圖1A的放大部分，其更清楚地說明依據一實施例的晶粒與中介層之間以及晶粒與嵌套組件之間的互連。 [圖2A]是依據一實施例的具有包括複數個嵌套組件的異質嵌套中介層的電子封裝的截面圖。 [圖2B]是依據一實施例的具有包括至少一個嵌套組件的異質嵌套中介層的電子封裝的截面圖，該至少一個嵌套組件不包含貫穿組件通孔。 [圖2C]是依據一實施例的具有包括至少一個嵌套組件的異質嵌套中介層的電子封裝的截面圖，該至少一個嵌套組件背向電子封裝中的晶粒。 [圖2D]是依據一實施例的具有包括空腔中的複數個堆疊組件的異質嵌套中介層的電子封裝的截面圖。 [圖2E]是依據一實施例的具有包括位於中介層和嵌套組件之上的再分配層的異質嵌套中介層的電子封裝的截面圖。 [圖2F]是依據一實施例的具有包括再分配層的異質嵌套中介層的電子封裝的截面圖。 [圖3A]是依據一實施例的具有異質嵌套中介層的電子封裝的平面圖。 [圖3B]是依據一實施例的圖3A中的電子封裝沿線B-B’的截面圖。 [圖3C]是依據一實施例的圖3A中的電子封裝沿線C-C’的截面圖。 [圖4]是依據一實施例的具有包括複數個中介層基板的異質嵌套中介層的電子封裝的平面圖。 [圖5A]是依據一實施例的設置在載體之上的複數個凸塊墊的截面圖。 [圖5B]是依據一實施例的在將中介層和嵌套組件附接到凸塊墊之後的截面圖。 [圖5C]是依據一實施例的在中介層和嵌套組件周圍設置底部填充物之後的截面圖。 [圖5D]是依據一實施例的在中介層和嵌套組件之上設置模具層之後的截面圖。 [圖5E]是依據一實施例的在將第二載體附接到模具層之後的截面圖。 [圖5F]是依據一實施例的在移除第一載體之後的截面圖。 [圖5G]是依據一實施例的在暴露凸塊墊之後的截面圖。 [圖5H]是依據一實施例的在結構被翻轉使得凸塊墊面向上之後的截面圖。 [圖5I]是依據一實施例的在將晶粒附接到凸塊墊之後的截面圖。 [圖5J]是依據一實施例的在晶粒周圍設置模具層之後的截面圖。 [圖5K]是依據一實施例的在移除第二載體之後的截面圖。 [圖5L]是依據一實施例的在形成穿過模具層的開口以暴露嵌套組件和中介層的墊之後的截面圖。 [圖5M]是依據一實施例的在封裝側凸塊設置在開口中之後的截面圖。 [圖6]是依據一實施例的包括異質嵌套中介層的電子系統的截面圖。 [圖7]是依據一實施例構建的計算裝置的示意圖。
100:電子封裝
120:晶粒
121:主動表面
122:模具層
130:中介層
131:底部填充材料
132:模具層
133:墊
134:通孔
135:空腔
137:凸塊
140:嵌套組件
141:主動表面
143:墊
144:貫穿組件通孔
180:部分
181:互連
182:互連

Claims (20)

  1. 一種電子封裝，包括： 中介層，包括矽，該中介層包括通孔，該通孔提供該中介層底部上的墊與該中介層頂部上的再分配層之間的連接； 在該中介層之上的第一晶粒，該第一晶粒藉由第一互連耦接到該中介層的該再分配層； 在該中介層之上並與該第一晶粒橫向間隔開的第二晶粒，該第二晶粒藉由第二互連耦接至該中介層的該再分配層； 第一模具層在該第一晶粒與該中介層之間以及在該第二晶粒與該中介層之間，該第一模具層橫向在該第一晶粒與該第二晶粒之間並與該第一晶粒和該第二晶粒接觸，並且該第一模具層與該第一互連接觸，並且與該第二互連接觸； 該中介層的該底部上的該墊上的凸塊以及該中介層的通孔垂直下方的凸塊，該凸塊垂直位於該第一晶粒下方並垂直位於該第二晶粒下方；以及 第二模具層在該中介層下方並與該中介層的一側接觸，該第二模具層與該凸塊以及該中介層的該底部上的該墊接觸。
  2. 如請求項1之電子封裝，其中，該第一模具層的最上表面與該第一晶粒的最上表面處於同一水平。
  3. 如請求項2之電子封裝，其中，該第一模具層的該最上表面與該第二晶粒的最上表面處於同一水平。
  4. 如請求項1之電子封裝，其中，該第二模具層與該中介層的第二側接觸，該第二側與該側橫向相對。
  5. 如請求項4之電子封裝，其中，該第二模具層不接觸該中介層的整個該側，並且不接觸該中介層的整個該第二側。
  6. 如請求項1之電子封裝，其中，該第二模具層的邊緣與該第一模具層的邊緣垂直對齊。
  7. 如請求項1之電子封裝，更包括： 該中介層與該第一模具層之間的底部填充材料。
  8. 一種製造電子封裝的方法，該方法包括： 將第一晶粒耦接至具有第一互連的中介層的再分配層，該中介層包括通孔，該通孔提供該中介層底部上的墊與該中介層頂部上的該再分配層之間的連接； 以第二互連將第二晶粒耦接至該中介層的該再分配層； 形成第一模具層在該第一晶粒與該中介層之間以及在該第二晶粒與該中介層之間，該第一模具層橫向在該第一晶粒與該第二晶粒之間並與該第一晶粒和該第二晶粒接觸，並且該第一模具層與該第一互連接觸，並且與該第二互連接觸； 形成該中介層的該底部上的該墊上的凸塊以及該中介層的通孔垂直下方的凸塊，該凸塊垂直位於該第一晶粒下方並垂直位於該第二晶粒下方；以及 形成第二模具層在該中介層下方並與該中介層的一側接觸，該第二模具層與該凸塊以及該中介層的該底部上的該墊接觸。
  9. 如請求項8之方法，其中，該第一模具層的最上表面與該第一晶粒的最上表面處於同一水平。
  10. 如請求項9之方法，其中，該第一模具層的該最上表面與該第二晶粒的最上表面處於同一水平。
  11. 如請求項8之方法，其中，該第二模具層與該中介層的第二側接觸，該第二側與該側橫向相對。
  12. 如請求項11之方法，其中，該第二模具層不接觸該中介層的整個該側，並且不接觸該中介層的整個該第二側。
  13. 如請求項8之方法，其中，該第二模具層的邊緣與該第一模具層的邊緣垂直對齊。
  14. 如請求項8之方法，更包括： 形成底部填充材料在該中介層與該第一模具層之間。
  15. 一種電子系統，包括： 板材； 封裝基板，耦接至該板材；以及 耦接到該封裝基板的電子封裝，該電子封裝包括： 中介層，包括矽，該中介層包括通孔，該通孔提供該中介層底部上的墊與該中介層頂部上的再分配層之間的連接； 在該中介層之上的第一晶粒，該第一晶粒藉由第一互連耦接到該中介層的再分配層； 在該中介層之上並與該第一晶粒橫向間隔開的第二晶粒，該第二晶粒藉由第二互連耦接至該中介層的該再分配層； 第一模具層在該第一晶粒與該中介層之間以及在該第二晶粒與該中介層之間，該第一模具層橫向在該第一晶粒與該第二晶粒之間並與該第一晶粒和該第二晶粒接觸，並且該第一模具層與該第一互連接觸，並且與該第二互連接觸； 該中介層的該底部上的該墊上的凸塊以及該中介層的通孔垂直下方的凸塊，該凸塊垂直位於該第一晶粒下方並垂直位於該第二晶粒下方；以及 第二模具層在該中介層下方並與該中介層的一側接觸，該第二模具層與該凸塊以及該中介層的該底部上的該墊接觸。
  16. 如請求項15之電子系統，更包括： 耦接到該板材的電池。
  17. 如請求項15之電子系統，更包括： 耦接到該板材的相機。
  18. 如請求項15之電子系統，更包括： 耦接到該板材的顯示器。
  19. 如請求項15之電子系統，更包括： 耦接到該板材的GPS。
  20. 如請求項15之電子系統，更包括： 耦接到該板材的通訊晶片。
TW112150203A 2019-06-11 2020-05-07 用於ｉｃ晶片的異質嵌套中介層封裝 TW202418502A (zh)

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