CN111916430A - 具有硅上腔桥的分解的管芯互连 - Google Patents
具有硅上腔桥的分解的管芯互连 Download PDFInfo
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- CN111916430A CN111916430A CN202010210659.5A CN202010210659A CN111916430A CN 111916430 A CN111916430 A CN 111916430A CN 202010210659 A CN202010210659 A CN 202010210659A CN 111916430 A CN111916430 A CN 111916430A
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Abstract
实施例公开了具有管芯组件的电子封装以及形成这种电子封装的方法。在实施例中,管芯组件包括:第一管芯;第二管芯,与第一管芯在横向上相邻。在实施例中,第一管芯和第二管芯均包括:第一半导体层;绝缘体层,在第一半导体层上方;第二半导体层,在绝缘体层上方。在实施例中,穿过第二半导体层设置腔。在实施例中,管芯组件还包括:桥接衬底,将第一管芯电耦合到第二管芯,其中,桥位于第一管芯的腔和第二管芯的腔中。
Description
技术领域
本公开内容的实施例涉及电子封装,更具体而言,涉及具有利用硅上腔桥互连的分解的管芯的电子封装。
背景技术
随着半导体工业中对性能需求的不断提高,与使用单个单片管芯相反,也存在对管芯分解的需求。管芯的分解需要将多个管芯连接在一起,以使它们作为一个管芯运行。然而,多个管芯的互连具有挑战性。特别地,封装衬底制造技术目前不能提供足够精细的线/间距能力以在封装衬底上制造互连。已经提出了几种解决方案以满足所需的线/间距分辨率。
一种这样的解决方案是使用嵌入式多管芯互连桥(EMIB)。EMIB架构包括将桥接衬底嵌入到封装衬底中。桥接衬底可以耦合在管芯之间并且提供所需的精细线/间距迹线。然而,将桥接衬底嵌入封装衬底中并非没有问题。例如,桥接衬底的存在要求从封装衬底去除两到三层铜以容纳EMIB管芯。去除这些铜层会切割Vccin馈入电源层。这会对负载线(LL)产生不利影响,从而迫使增加封装层数以保持足够的性能。另外,EMIB管芯阻挡封装底部的连接盘侧电容器(LSC)与硅管芯之间的过孔拼接(via stitching)。
提供分解的管芯的互连的另一个提议的解决方案是使用3D管芯堆叠架构。然而,由于管芯堆叠在基础管芯上方,因此这种解决方案增加了Z高度。此外,3D管芯堆叠架构的实施成本高昂,并且具有很高的设计复杂度。此外,3D管芯堆叠依赖于穿衬底过孔(TSV)来连接到管芯。这限制了功率传送路径并引入了损耗。
附图说明
图1A是根据实施例的具有用于容纳桥接衬底的管芯上腔的管芯组件的截面图。
图1B是根据另一实施例的具有用于容纳桥接衬底的管芯上腔的管芯组件的截面图。
图2A是根据实施例的具有包括用于容纳桥接衬底的管芯上腔的管芯组件的电子封装的截面图。
图2B是根据实施例的具有通过放置在管芯上腔中的桥接衬底互连的一对管芯的电子封装的平面图。
图2C是根据实施例的具有通过跨过管芯的整个宽度的桥互连的一对管芯的电子封装的平面图。
图2D是根据实施例的具有通过放置在不同管芯上腔中的多个桥接衬底互连的多个管芯的电子封装的平面图。
图2E是根据实施例的具有通过单个桥接衬底互连的多个管芯的电子封装的平面图。
图3A是根据实施例的包括第一半导体层、绝缘体层和第二半导体层的管芯的截面图。
图3B是根据实施例的在第一半导体层上制造有源表面之后的管芯的截面图。
图3C是根据实施例的在形成穿过第二半导体层的腔之后的管芯的截面图。
图3D是根据实施例的在将第一管芯和第二管芯安装到载体上以使管芯上腔彼此对准之后的截面图。
图3E是根据实施例的在将桥接衬底放置在腔中并附接到第一管芯和第二管芯之后的截面图。
图3F是根据实施例的在用腔填充材料填充腔并且将管芯组件从载体转移到封装衬底之后的截面图。
图4A是根据实施例的具有管芯组件的电子封装的截面图,该管芯组件具有带有载体的薄桥接衬底。
图4B是根据实施例的当紫外(UV)光传播通过桥接衬底载体时的电子封装的截面图。
图4C是根据实施例的在去除桥接衬底载体之后的电子封装的截面图。
图4D是根据实施例的在设置腔填充材料以嵌入桥接衬底之后的电子封装的截面图。
图5是根据实施例的包括通过管芯上腔中的桥接衬底电耦合在一起的多个管芯的电子系统的截面图。
图6是根据实施例构建的计算设备的示意图。
具体实施方式
根据各种实施例,本文描述的是具有通过硅上腔桥互连的分解的管芯的电子封装。在以下说明中,将使用本领域技术人员通常用于向本领域中其他技术人员传达其工作的实质的术语来说明示例性实施方式的多个方面。但对于本领域技术人员来说,显然,本发明的实践可以仅借助某些所述的方面。为了解释,阐述了特定数量、材料和配置以便提供对示例性实施方式的透彻理解。但对于本领域技术人员来说,显然,本发明的实践可以无需这些特定细节。在其他情况下,省略或简化了公知的特征,以避免使得示例性实施方式难以理解。
以最有助于理解本发明的方式将各种操作描述为依次的多个分离操作,但描述的顺序不应解释为暗示这些操作必定是顺序相关的。具体而言,这些操作不必按照所呈现的顺序执行。
如上所述,互连架构是实现管芯分解所需的关键设计考虑因素。已经提出了使用EMIB和3D管芯堆叠,但是如上所述,两种架构都受到限制。因此,本文公开的实施例包括利用从封装衬底去除的桥接衬底的互连架构。由于不需要去除铜层,因此从封装衬底去除桥接衬底允许实现直接Vccin馈电路径。因此,改善了负载线。代替位于封装衬底中,本文公开的实施例包括将桥接衬底放置在腔中,该腔形成在被连接在一起的管芯的背面表面中。此外,由于将桥接衬底设置在腔中,因此电子封装的Z高度不会如3D管芯堆叠中的情况一样增加。
现在参考图1A,示出了根据实施例的管芯组件100的截面图。管芯组件100可以包括第一管芯110A和第二管芯110B。在实施例中,第一管芯110A和第二管芯110B中的每一个包括第一半导体层112、绝缘层114和第二半导体层116。例如,第一管芯110A和第二管芯110B可以被称为绝缘体上硅(SOI)管芯。然而,应当理解,第一半导体层112可以是任何半导体材料。例如,第一半导体层112可以包括硅、III-V族半导体材料等。在一些实施例中,第二半导体层116可以包括与第一半导体层112相同的半导体材料。在其他实施例中,第二半导体层116可以包括与第一半导体层112不同的半导体材料。在实施例中,绝缘体层114可以包括氧化硅或任何其他合适的绝缘材料。在实施例中,第二半导体层116的厚度可以大约等于或大于第一半导体层112的厚度。为第二半导体层116提供更大的厚度改善了管芯组件100的结构完整性。
在实施例中,第一管芯110A可以与第二管芯110B基本相似。例如,第一管芯110A和第二管芯110B都可以是处理器管芯。在其他实施例中,第一管芯110A可以是与第二管芯110B不同类型的管芯。例如,第一管芯110A可以是处理器管芯,第二管芯110B可以是存储器管芯、图形处理器管芯、通信管芯或任何其他类型的管芯。
在实施例中,腔111可以穿过第二半导体层116设置。腔111可以沿着第一管芯110A和第二管芯110B的边缘定位。腔111可以暴露绝缘层114的部分。如图所示,第一管芯110A中的腔111可以与第二管芯110B中的腔111对准。因此,可以在第二半导体层116之间提供第一间隙G1。第一间隙G1可以大于在第一半导体层112之间的第二间隙G2。
在实施例中,第一半导体层112可以包括有源层118。有源层118可以包括晶体管、导电布线等(如虚线所示)。导电凸块119可以设置在有源层118上方。导电凸块119可以是适合于第一级互连(FLI)的任何合适的凸块或互连结构。在实施例中,有源层118可以通过穿衬底过孔(TSV)117电耦合到腔111的底表面。TSV 117可以穿过第一半导体层112并且穿过绝缘体层114。
在实施例中,桥接衬底120可以位于第一间隙G1中。即,桥接衬底120可以在第一管芯110A中的腔111与第二管芯110B中的腔111之间延伸。将桥接衬底120定位在腔111中隐藏了桥接衬底120的厚度,使得管芯组件100的Z高度没有增加。例如,桥接衬底120的顶表面可以与第二半导体层116的顶表面基本上共面。然而,应当理解,在一些实施例中,桥接衬底120的顶表面可以在第二半导体层116的顶表面上方。
桥接衬底120可以通过TSV 117电耦合到有源层118。例如,桥接衬底120可以通过凸块122和/或球123电耦合到TSV 117。在实施例中,桥接衬底120在第一管芯110A和第二管芯110B之间提供电耦合。例如,桥接衬底120可以包括用于将第一管芯110A电耦合到第二管芯110B的多个迹线(未示出)。桥接衬底120可以是硅衬底。因此,可以使用硅工艺来提供具有精细的线/间距尺寸(例如2μm/2μm)的迹线。
在一些实施例中,桥接衬底120可以是无源部件。在其他实施例中,桥接衬底120可以是有源部件。例如,除了用于将第一管芯110A电耦合到第二管芯110B的迹线之外,桥接衬底120还可以包括晶体管等。
现在参考图1B,示出了根据另一实施例的管芯组件100的截面图。图1B中的管芯组件100可以与图1A中的管芯组件100基本相似,不同之处在于桥接衬底120的厚度减小。特别地,桥接衬底120的厚度可以小于第二半导体层116的厚度。因此,实施例可以包括顶表面在第一管芯110A的顶表面和第二管芯110B的顶表面下方的桥接衬底120。
现在参考图2A,示出了根据实施例的具有管芯组件200的电子封装240的截面图。在实施例中,管芯组件200可以电耦合到封装衬底242。管芯组件200可以基本上类似于以上关于图1A描述的管芯组件100。例如,第一管芯210A和第二管芯210B可以在横向上彼此相邻,并且通过桥接衬底220电耦合在一起。桥接衬底220通过第二半导体层216放置在腔211中。第一管芯210A和第二管芯210B可以包括具有有源区218的第一半导体层212、在第一半导体层212上方的绝缘层214以及在绝缘层214上方的第二半导体层216。在实施例中,桥接衬底220可以通过凸块222、球223和TSV 217电耦合到有源区218。在实施例中,可以将底部填充材料243设置在管芯组件200周围和下方。例如,底部填充材料243可以围绕电耦合到封装衬底242的凸块219。
现在参考图2B,示出了根据实施例的电子封装240的平面图。如图所示,第一管芯210A和第二管芯210B在横向上彼此相邻并位于封装衬底242上方。在实施例中,示出了第一管芯210A和第二管芯210B的最顶层(即,第二半导体层216)。在实施例中,可以穿过第二半导体层216形成腔211。腔211暴露绝缘层214的一部分。如图所示,腔211沿着第一管芯210A和第二管芯210B的边缘并且是彼此对准。桥接衬底220在腔211中的绝缘层214的暴露部分上方。如图所示,桥接衬底220跨过第一管芯210A和第二管芯210B之间的第二间隙G2延伸。
现在参考图2C,示出了根据实施例的电子封装240的平面图。在实施例中,电子封装240可以与图2B所示的电子封装240基本相似,不同之处在于桥接衬底220的宽度基本上等于第一管芯210A和第二管芯210B的宽度。在这样的实施例中,腔211也可以沿着第一管芯210A和第二管芯210B的整个宽度延伸。即,腔211可以仅具有单个竖直侧壁。
现在参考图2D,示出了根据另一实施例的电子封装240的平面图。如图所示,电子封装240可以包括在横向上彼此相邻的多个管芯210A-D。尽管示出了四个管芯210A-D,但是应当理解,电子封装可以包括任何数量的管芯210。在实施例中,每个管芯210A-D可以通过桥接衬底220A-D电耦合到相邻的管芯210A-D。特别地,每个管芯210A-D具有多于一个的腔211,以便容纳多于一个的桥接衬底220。例如,第一管芯210A通过第一桥接衬底220A电耦合到第二管芯210B,并且第一管芯210A还通过第四桥接衬底220D电耦合到第四管芯210D。
现在参考图2E,示出了根据另一实施例的电子封装240的平面图。在实施例中,电子封装240可以包括多个管芯210A-D。每个管芯210A-D可以与单个桥接衬底220互连。即,桥接衬底220可以放置在形成于每个管芯210A-D的一部分中的腔211中。
现在参考图3A-3F,示出了根据实施例的描绘用于形成电子封装的过程的一系列截面图。
现在参考图3A,示出了根据实施例的第一管芯310A的截面图。在实施例中,第一管芯310A包括第一半导体层312和第二半导体层316。绝缘层314可以将第一半导体层312与第二半导体层316分开。第一管芯310A可以被称为SOI管芯。在实施例中,第一半导体层312可以包括与第二半导体层316相同的半导体材料。在其他实施例中,第一半导体层312可以包括与第二半导体层316不同的半导体材料。在一个具体实施例中,第一半导体层312包括硅或III-V族半导体。在图3A所示的图示中,为简单起见,仅示出了单个第一管芯310A。然而,应当理解,第一管芯310A可以是包括多个管芯310的较大衬底(例如,晶圆)的一部分。
现在参考图3B,示出了根据实施例的在第一半导体层312上方形成有源区318之后的第一管芯310A的截面图。在实施例中,有源区318可以包括晶体管和/或布线(如虚线所示)。在实施例中,TSV 317也可以形成在第一管芯310A中。TSV 317可以延伸穿过第一半导体层312和绝缘层314。TSV 317可以电耦合到有源区318(例如,晶体管和/或布线)。可以通过本领域技术人员已知的标准半导体制造操作来实现有源区318和TSV 317的形成。
现在参考图3C,示出了根据实施例的在第一管芯310A中形成腔311之后的截面图。图3C所示的第一管芯310A相对于图3B所示的第一管芯310A翻转。即,第二半导体层316面朝上。在实施例中,可以通过光刻工艺形成腔311。例如,掩模层315可以设置在第二半导体层316的一部分表面上方。将第二半导体层316的暴露部分蚀刻掉以形成腔311。例如,蚀刻工艺可以包括反应离子蚀刻(RIE)或任何其他合适的蚀刻工艺。腔311暴露绝缘层314和TSV317的一部分。在实施例中,凸块319也可以设置在有源表面318上方。可以在形成腔311之前或之后设置凸块319。在形成腔311之后,可以将第一管芯310A从晶圆分割(singulated)。
现在参考图3D,示出了根据实施例的在将第一管芯310A和第二管芯310B附接到载体351之后的截面图。第一管芯310A和第二管芯310B可以通过粘合剂313等附接到载体351。在实施例中,第二管芯310B可以利用与制造第一管芯310A基本相同的处理操作来形成。在一些实施例中,可以在同一晶圆上制造第一管芯310A和第二管芯310B。在其他实施例中,可以在不同的晶圆上制造第一管芯310A和第二管芯310B。例如,第一管芯310A可以是处理器管芯,第二管芯310B可以是存储器管芯、图形管芯、通信管芯或任何其他管芯。
在实施例中,第一管芯310A可以与第二管芯310B在横向上相邻地定位并且彼此间隔开一定间隙。例如,第一间隙G1可以将第一管芯310A的第二导电层316与第二管芯310B的第二导电层316分开。第二间隙G2可以将第一管芯310A的第一半导体层312与第二管芯310B的第一半导体层312分开。在实施例中,第二间隙G2小于第一间隙G1。
现在参考图3E,示出了根据实施例的在将桥接衬底320附接到第一管芯310A和第二管芯310B之后的截面图。在实施例中,将桥接衬底320放置在腔311中。桥接衬底320通过凸块322和球323电耦合到TSV 317。
参考图3F,示出了根据实施例的在将管芯组件转移到封装衬底342以提供电子封装340之后的截面图。可以使用凸块319将管芯组件安装到封装衬底342。可以在第一管芯310A和第二管芯310B的下方和周围设置底部填充材料343。在实施例中,也可以将桥接衬底320嵌入模制材料325中。例如,模制材料325可以是环氧树脂等。尽管上面的处理流程包括在安装到封装衬底342之前将管芯组件安装到载体351,但是实施例不限于这样的处理流程。例如,可以省略载体351的使用,并且可以将第一管芯310A和第二管芯310B安装到封装衬底342。在这样的实施例中,可以在将第一管芯310A和第二管芯310B固定到封装衬底342之后,将桥接衬底320附接到第一管芯310A和第二管芯310B。
现在参考图4A-4D,示出了根据实施例的用于将电子封装440与薄桥接衬底420进行组装的过程的一系列截面图。
现在参考图4A,示出了根据实施例的具有通过凸块419附接到封装衬底442的第一管芯410A和第二管芯410B的电子封装440的截面图。在实施例中,第一管芯410A和第二管芯410B可以与上述管芯基本相似。例如,它们可以包括第一半导体层412、绝缘层414和第二半导体层416。有源区418可以耦合到向上延伸到腔的底表面的TSV 417。
在实施例中,可以将桥接衬底420放置在腔中并且在第一管芯410A和第二管芯410B之间提供电耦合。例如,凸块422和球423可以将桥接衬底420电耦合到TSV417。在特定实施例中,桥接衬底420的厚度可以小于第二半导体层416的厚度。使用薄桥接衬底420防止了桥接衬底420的一部分在第二半导体层416的顶表面上方延伸。然而,薄衬底比较厚衬底更易碎。因此,薄桥接衬底420可能需要附加的层和处理,以便将桥接衬底420附接到电子封装440。
为了提供薄桥接衬底420到电子封装440中的可靠集成,可以将桥接衬底420附接到载体428。在实施例中,可以将载体428通过粘合剂427附接到桥接衬底420。载体428具有的厚度和刚度可以足以允许桥接衬底420结合到第一管芯410A和第二管芯410B。例如,载体428的顶表面可以在第一管芯410A和第二管芯410B的第二半导体层416的顶表面上方延伸。
现在参考图4B,示出了根据实施例的在用于将载体428与桥接衬底420分离的过程期间的电子封装440的截面图。如图所示,电磁辐射445可以通过载体428传播以与粘合剂427相互作用。例如,载体428可以是可透射紫外线(UV)辐射的材料,例如玻璃。在实施例中,粘合剂427可以是通过紫外线(UV)辐射溶解的粘合剂,以便从桥接衬底420释放载体428。
现在参考图4C,示出了根据实施例的在从桥接衬底420去除载体428之后的电子封装440的截面图。在实施例中,在去除载体428之后,桥接衬底420保留在腔中。特别地,由于桥接衬底420是薄衬底,所以桥接衬底420的顶表面在第一管芯410A和第二管芯410B的顶表面下方。
现在参考图4D,示出了根据实施例的在将填充材料425设置在腔中之后的截面图。在实施例中,填充材料425完全嵌入桥接衬底420。即,桥接衬底420的侧壁和顶表面可以被填充材料425覆盖。在实施例中,填充材料425可以是任何合适的材料,例如环氧树脂等。
现在参考图5,示出了根据实施例的电子系统590的截面图。在实施例中,电子系统590可以包括板591,诸如印刷电路板(PCB)、母板等。在实施例中,电子封装540可以通过互连592电耦合到板591。在实施例中,电子封装540可以基本上类似于诸如上述的那些电子封装。例如,电子封装540可以包括封装衬底542和附接到封装衬底542的管芯组件500。
在实施例中,管芯组件500包括第一管芯510A、第二管芯510B和放置在第一管芯510A和第二管芯510B中的腔511中的桥接衬底520。第一管芯510A和第二管芯510B中的每一个可以包括第一半导体层512、绝缘层514和第二半导体层516。腔511穿过第二半导体层516形成并且暴露绝缘层514的一部分。在实施例中,有源区518位于面向封装衬底542的第一半导体层512中。
图6示出了根据本发明的一种实施方式的计算设备600。计算设备600容纳板602。板602可以包括多个部件,包括但不限于,处理器604和至少一个通信芯片606。处理器604物理且电耦合到板602。在一些实施方式中,至少一个通信芯片606也物理且电耦合到板602。在进一步的实施方式中,通信芯片606是处理器604的一部分。
这些其他部件包括但不限于,易失性存储器(例如,DRAM)、非易失性存储器(例如ROM)、闪存、图形处理器、数字信号处理器、加密处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码解码器、视频编码解码器、功率放大器、全球定位系统(GPS)设备、指南针、加速度计、陀螺仪、扬声器、相机和大容量储存设备(例如,硬盘驱动器、光盘(CD)、数字多用途盘(DVD)等等)。
通信芯片606实现了无线通信,用于往来于计算设备600传送数据。术语“无线”及其派生词可以用于描述可以通过非固态介质借助使用调制电磁辐射传送数据的电路、设备、系统、方法、技术、通信信道等。该术语并非暗示相关设备不包含任何导线,尽管在一些实施例中它们可以不包含。通信芯片606可以实施多个无线标准或协议中的任意一个,包括但不限于,Wi-Fi(IEEE 802.11族)、WiMAX(IEEE 802.16族)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其派生物,以及被指定为3G、4G、5G及更高代的任何其他无线协议。计算设备600可以包括多个通信芯片606。例如,第一通信芯片606可以专用于近距离无线通信,例如Wi-Fi和蓝牙,第二通信芯片606可以专用于远距离无线通信,例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
计算设备600的处理器604包括封装在处理器604内的集成电路管芯。在本发明的一些实施方式中,处理器的集成电路管芯可以封装在电子系统中,该电子系统包括根据本文所述的实施例的管芯组件,该管芯组件具有第一管芯、第二管芯以及设置在第一管芯和第二管芯中的腔中的桥接衬底,其中,桥接衬底将第一管芯电耦合到第二管芯。术语“处理器”可以指代任何设备或设备的部分,其处理来自寄存器和/或存储器的电子数据,以将该电子数据转变为可以存储在寄存器和/或存储器中的其他电子数据。
通信芯片606也包括封装在通信芯片606内的集成电路管芯。根据本发明的另一个实施方式,通信芯片的集成电路管芯可以封装在电子系统中,该电子系统包括根据本文所述的实施例的管芯组件,该管芯组件具有第一管芯、第二管芯以及设置在第一管芯和第二管芯中的腔中的桥接衬底,其中,桥接衬底将第一管芯电耦合到第二管芯。
对本发明的所示实施方式的以上描述(包括摘要中所描述的内容)并非旨在是详尽无遗的或将本发明限制于所公开的精确形式。虽然本文中出于说明性目的描述了特定实施方式和示例,但是如相关领域的技术人员将认识到的,在本发明的范围内可以进行各种等同修改。
根据以上具体实施方式,可以对本发明进行这些修改。以下权利要求中使用的术语不应被解释为将本发明限制为说明书和权利要求中公开的特定实施方式。相反,本发明的范围完全由以下权利要求确定,权利要求应根据权利要求解释的既定原则来解释。
示例1:一种管芯组件,包括:第一管芯;第二管芯,与第一管芯在横向上相邻,其中,第一管芯和第二管芯均包括:第一半导体层;绝缘体层,在第一半导体层上方;第二半导体层,在绝缘体层上方;腔,穿过第二半导体层设置;桥接衬底,将第一管芯电耦合到第二管芯,其中,桥位于第一管芯的腔和第二管芯的腔中。
示例2:示例1的管芯组件,其中,第一管芯的腔沿着第一管芯的第一边缘,并且其中,第二管芯的腔沿着第二管芯的第一边缘。
示例3:示例2的管芯组件,其中,第一管芯的第一边缘面向第二管芯的第一边缘。
示例4:示例1-3的管芯组件,其中,第一管芯和第二管芯还包括:在第一半导体层中的有源区。
示例5:示例4的管芯组件,其中,有源区通过穿过第一半导体层和绝缘体层的穿衬底过孔(TSV)电耦合到桥。
示例6:示例1-5的管芯组件,其中,第一半导体层和第二半导体层包括相同的半导体材料。
示例7:示例1-6的管芯组件,其中,第一半导体层包括硅或III-V族半导体系统。
示例8:示例1-7的管芯组件,其中,第一半导体层的厚度小于第二半导体层的厚度。
示例9:示例1-8的管芯组件,其中,桥接衬底是无源部件。
示例10:示例1-8的管芯组件,其中,桥接衬底是有源部件。
示例11:一种电子封装,包括:封装衬底;管芯组件,耦合到封装衬底,其中,管芯组件包括:第一管芯;第二管芯,与第一管芯相邻;腔,进入到第一管芯和第二管芯中;及桥接衬底,在腔中,其中,桥接衬底将第一管芯电耦合到第二管芯。
示例12:示例11的电子封装,其中,第一管芯和第二管芯中的每一个均包括有源表面,其中,有源表面面向封装衬底。
示例13:示例12的电子封装,其中,有源表面通过在腔的底表面处终止的穿衬底过孔(TSV)电耦合到桥接衬底。
示例14:示例13的电子封装,其中,腔的底表面包括绝缘体。
示例15:示例11-14的电子封装,其中,第一管芯和第二管芯中的每一个均包括:第一半导体层;绝缘体,在第一半导体层上方;及第二半导体层,其中,腔穿过第二半导体层。
示例16:示例15的电子封装,其中,第一半导体层和第二半导体层包括相同的半导体材料。
示例17:示例15的电子封装,其中,第一半导体层和第二半导体层包括不同的半导体材料。
示例18:示例11-17的电子封装,其中,填充材料包封桥接衬底并填充腔。
示例19:示例11-18的电子封装,其中,桥接衬底的顶表面在第一管芯和第二管芯的顶表面下方。
示例20:示例11-19的电子封装,其中,桥接衬底是无源部件。
示例21:示例11-19的电子封装,其中,桥接衬底是有源部件。
示例22:一种电子系统,包括:板;封装衬底,电耦合到板;及管芯组件,电耦合到封装衬底,其中,管芯组件包括:多个管芯,其中,多个管芯中的管芯在横向上彼此相邻;桥接衬底,将管芯电耦合在一起,其中,桥接衬底位于跨越相邻管芯的腔中。
示例23:示例22的电子系统,其中,多个管芯包括第一管芯和第二管芯。
示例24:示例22或示例23的电子系统,其中,多个管芯包括多于两个的管芯,并且其中,管芯组件还包括多个桥接衬底,其中,每个桥接衬底位于跨越相邻管芯的不同腔中。
示例25:示例22-24的电子系统,其中,多个管芯中的每个管芯包括:第一半导体层,其中,管芯的有源表面在第一半导体层中;绝缘体层,在第一半导体层上方;及第二半导体层,在绝缘体层上方,其中,腔穿过第二半导体层。
Claims (25)
1.一种管芯组件,包括:
第一管芯;
第二管芯,所述第二管芯与所述第一管芯在横向上相邻,其中,所述第一管芯和所述第二管芯均包括:
第一半导体层;
绝缘体层,所述绝缘体层在所述第一半导体层上方;
第二半导体层,所述第二半导体层在所述绝缘体层上方;
腔,所述腔穿过所述第二半导体层设置;以及
桥接衬底,所述桥接衬底将所述第一管芯电耦合到所述第二管芯,其中,所述桥位于所述第一管芯的腔和所述第二管芯的腔中。
2.根据权利要求1所述的管芯组件,其中,所述第一管芯的腔沿着所述第一管芯的第一边缘,并且其中,所述第二管芯的腔沿着所述第二管芯的第一边缘。
3.根据权利要求2所述的管芯组件,其中,所述第一管芯的第一边缘面向所述第二管芯的第一边缘。
4.根据权利要求1、2或3所述的管芯组件,其中,所述第一管芯和所述第二管芯还包括:
在所述第一半导体层中的有源区。
5.根据权利要求4所述的管芯组件,其中,所述有源区通过穿过所述第一半导体层和所述绝缘体层的穿衬底过孔(TSV)电耦合到所述桥。
6.根据权利要求1、2或3所述的管芯组件,其中,所述第一半导体层和所述第二半导体层包括相同的半导体材料。
7.根据权利要求1、2或3所述的管芯组件,其中,所述第一半导体层包括硅或III-V族半导体系统。
8.根据权利要求1、2或3所述的管芯组件,其中,所述第一半导体层的厚度小于所述第二半导体层的厚度。
9.根据权利要求1、2或3所述的管芯组件,其中,所述桥接衬底是无源部件。
10.根据权利要求1、2或3所述的管芯组件,其中,所述桥接衬底是有源部件。
11.一种电子封装,包括:
封装衬底;
管芯组件,所述管芯组件耦合到所述封装衬底,其中,所述管芯组件包括:
第一管芯;
第二管芯,所述第二管芯与所述第一管芯相邻;
腔,所述腔进入到所述第一管芯和所述第二管芯中;以及
桥接衬底,所述桥接衬底在所述腔中,其中,所述桥接衬底将所述第一管芯电耦合到所述第二管芯。
12.根据权利要求11所述的电子封装,其中,所述第一管芯和所述第二管芯中的每一个均包括有源表面,其中,所述有源表面面向所述封装衬底。
13.根据权利要求12所述的电子封装,其中,所述有源表面通过在所述腔的底表面处终止的穿衬底过孔(TSV)电耦合到所述桥接衬底。
14.根据权利要求13所述的电子封装,其中,所述腔的底表面包括绝缘体。
15.根据权利要求11、12、13或14所述的电子封装,其中,所述第一管芯和所述第二管芯中的每一个均包括:
第一半导体层;
绝缘体,所述绝缘体在所述第一半导体层上方;以及
第二半导体层,其中,所述腔穿过所述第二半导体层。
16.根据权利要求15所述的电子封装,其中,所述第一半导体层和所述第二半导体层包括相同的半导体材料。
17.根据权利要求15所述的电子封装,其中,所述第一半导体层和所述第二半导体层包括不同的半导体材料。
18.根据权利要求11、12、13或14所述的电子封装,其中,填充材料包封所述桥接衬底并填充所述腔。
19.根据权利要求11、12、13或14所述的电子封装,其中,所述桥接衬底的顶表面在所述第一管芯和所述第二管芯的顶表面下方。
20.根据权利要求11、12、13或14所述的电子封装,其中,所述桥接衬底是无源部件。
21.根据权利要求11、12、13或14所述的电子封装,其中,所述桥接衬底是有源部件。
22.一种电子系统,包括:
板;
封装衬底,所述封装衬底电耦合到所述板;以及
管芯组件,所述管芯组件电耦合到所述封装衬底,其中,所述管芯组件包括:
多个管芯,其中,所述多个管芯中的管芯在横向上彼此相邻;
桥接衬底,所述桥接衬底将所述管芯电耦合在一起,其中,所述桥接衬底位于跨越相邻管芯的腔中。
23.根据权利要求22所述的电子系统,其中,所述多个管芯包括第一管芯和第二管芯。
24.根据权利要求22或23所述的电子系统,其中,所述多个管芯包括多于两个的管芯,并且其中,所述管芯组件还包括多个桥接衬底,其中,每个所述桥接衬底位于跨越相邻管芯的不同腔中。
25.根据权利要求22或23所述的电子系统,其中,所述多个管芯中的每个管芯包括:
第一半导体层,其中,所述管芯的有源表面在所述第一半导体层中;
绝缘体层,所述绝缘体层在所述第一半导体层上方;以及
第二半导体层,所述第二半导体层在所述绝缘体层上方,其中,所述腔穿过所述第二半导体层。
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US7999383B2 (en) | 2006-07-21 | 2011-08-16 | Bae Systems Information And Electronic Systems Integration Inc. | High speed, high density, low power die interconnect system |
US10943792B2 (en) | 2016-09-27 | 2021-03-09 | Intel Corporation | 3D stacked-in-recess system in package |
US9984995B1 (en) * | 2016-11-13 | 2018-05-29 | Nanya Technology Corporation | Semiconductor package and manufacturing method thereof |
US10535608B1 (en) * | 2018-07-24 | 2020-01-14 | International Business Machines Corporation | Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate |
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