TWI520305B - 斜坡堆疊晶片封裝中之光學通訊 - Google Patents

斜坡堆疊晶片封裝中之光學通訊 Download PDF

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Publication number
TWI520305B
TWI520305B TW100128697A TW100128697A TWI520305B TW I520305 B TWI520305 B TW I520305B TW 100128697 A TW100128697 A TW 100128697A TW 100128697 A TW100128697 A TW 100128697A TW I520305 B TWI520305 B TW I520305B
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semiconductor die
semiconductor
optical signal
optical
ramp
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TW100128697A
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TW201230289A (en
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約翰 哈瑞達
大衛 道格拉斯
羅伯特 多斯特
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奧瑞可國際公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • G—PHYSICS
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    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
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    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Optics & Photonics (AREA)
  • Optical Couplings Of Light Guides (AREA)
  • Optical Integrated Circuits (AREA)

Description

斜坡堆疊晶片封裝中之光學通訊
本發明一般而言係有關一種半導體晶片封裝之設計。更明確地，本發明係有關一種包括一配置於堆疊中之晶片族群及一斜坡組件的半導體晶片封裝，該斜坡組件係與半導體晶粒傳遞光學信號。
相較於連接至印刷電路板之個別封裝的晶片，包括堆疊之半導體晶片的晶片封裝可提供顯著較高的性能。這些晶片封裝亦提供某些優點，諸如下列能力：使用堆疊中之不同晶片上的不同製程、結合較高密度的邏輯和記憶體、及使用較少的電力來轉移資料。例如，實施動態隨機存取記憶體(DRAM)之晶片的堆疊可使用一基礎晶片中之高金屬層數的、高性能的邏輯程序以實施輸入/輸出(I/O)及控制器功能，而一組較低金屬層數的、DRAM特殊處理過的晶片可被使用於該堆疊之剩餘晶片。以此方式，結合之晶片組可具有較佳的性能及較低的成本，相較於以下方式：一種包括使用DRAM製程所製造之I/O和控制器功能的單一晶片；一種包括使用邏輯製程所製造之記憶體電路的單一晶片；或一種藉由嘗試使用單一製程來製作邏輯和記憶體兩者之實體結構而建構的系統。
然而，欲獲得低成本、高性能(例如，高頻寬)之互連於堆疊的半導體晶片之間可能是困難的。例如，半導體晶片可使用晶片堆疊中之表面上的暴露焊墊(bond pads)間之焊線(wire bond)而被電耦合，其中晶片係彼此偏移以界定晶片邊緣之梯狀鋸齒。但雖然這些焊線可使用低成本的組裝技術來實施，其所得的焊線通常具有低的頻寬。
反之，矽穿孔(TSV)通常具有較焊線更高的頻寬。於TSV製造技術中，將晶片處理以致在其主動面上之一或更多金屬層被導電地連接至其背面上之新的墊。接著，晶片被黏性地連接於一堆疊中，以致一晶片之背面上的新墊得以完成與一相鄰晶片之主動面上的相應墊之導電接觸。
然而，TSV通常具有較焊線更高的成本。這是因為TSV通過一晶片之主動矽層。結果，TSV佔據了其可能已被用於電晶體或佈線之區域。此機率成本可能很大。例如，假如TSV排除或排外直徑為20μm，且TSV被置於30μm之節距上，則約45%之矽區域被TSV所損耗。此約略為堆疊中之晶片中的任何電路之每區域成本的兩倍。(事實上，製造費用(overhead)可能甚至更高，因為電路通常會散開以容納TSV，其浪費更多區域。)此外，製造TSV通常需要額外的處理操作，其亦增加了成本。
因此，需要一種提供堆疊晶片之優點而無上述問題的晶片封裝。
本發明之一實施例係提供一種晶片封裝。此晶片封裝包括一組配置在垂直方向之垂直堆疊中的半導體晶粒，其係實質上垂直於垂直堆疊中之第一半導體晶粒。此外，各半導體晶粒(在該第一晶粒之後)從垂直堆疊中緊接在前的半導體晶粒以水平方向被偏移一偏移值，藉此界定一步進階地(stepped terrace)於垂直堆疊之一側上。再者，晶片封裝中之一斜坡組件被堅固地機械式耦合至半導體晶粒。此斜坡組件被置於垂直堆疊之該一側上，且係幾乎平行於沿著步進階地之方向，其係介於水平方向與垂直方向之間。此外，斜坡組件包括：一光學波導，其傳遞光學信號；及一光學耦合組件，其係將光學信號光學地耦合至該組半導體晶粒中之一半導體晶粒。
於某些實施例中，斜坡組件包括一組光學耦合組件，其包括該光學耦合組件。此外，該組光學耦合組件中之一既定的光學耦合組件可將該光學信號光學地耦合至該組半導體晶粒(其包括該半導體晶粒)中之一既定的半導體晶粒。
注意：光學波導可於沿著步進階地之方向傳遞光學信號。再者，光學耦合組件可將光學信號重新導引入半導體晶粒之一平面。例如，光學信號可透過半導體晶粒之一邊緣而被光學地耦合至半導體晶粒。另一方面，光學耦合組件可沿著斜坡組件之表面的一法線而重新導引光學信號。因此，光學信號可於半導體晶粒之邊緣以外的半導體晶粒之表面上的位置上被光學地耦合至半導體晶粒。
此外，該組半導體晶粒中之一對半導體晶粒可將來自該對中之第一半導體晶粒的光學信號光學地耦合至該對中之第二半導體晶粒而不使用斜坡組件。
於某些實施例中，斜坡組件被製造於半導體以外的材料上。再者，斜坡組件可為另一半導體晶粒。
於某些實施例中，斜坡組件被耦合至每一半導體晶粒，其係使用下列之至少一者：焊料、微彈簧及/或各向異性導電膜。
另一實施例提供一種包括晶片封裝之電子裝置(諸如電腦系統)。
另一實施例提供一種用以傳遞光學信號之方法。於此方法期間，光學信號被傳遞於斜坡組件中之一光學波導中，該斜坡組件被堅固地機械式耦合至該組配置在垂直方向之垂直堆疊中的半導體晶粒。注意：半導體晶粒被彼此偏移於水平方向，藉此界定步進階地於垂直堆疊之一側上。再者，斜坡組件被置於幾乎平行於沿著步進階地之方向的垂直堆疊之一側上，其係介於水平方向與垂直方向之間。接著，光學信號係使用一光學耦合組件而被光學地耦合至該組半導體晶粒之一半導體晶粒。
描述一種晶片封裝、一種包括晶片封裝之電子裝置、及一種用以傳遞光學信號於晶片封裝中之方法的實施例。此晶片封裝包括半導體晶粒之一垂直堆疊或者在水平方向上彼此偏移之晶片，藉此界定一步進階地。一高頻寬的斜坡組件(其被設置幾乎平行於步進階地)被機械式耦合至半導體晶粒。再者，斜坡組件包括一傳遞光學信號之光學波導、及一將光學信號光學地耦合至半導體晶粒之一的光學耦合組件，藉此促成半導體晶粒與斜坡組件間之光學信號的高頻寬通訊。
藉由去除半導體晶粒中昂貴且佔面積的矽穿孔(TSV)，晶片封裝可提供高頻寬及低成本。例如，可藉由避免半導體晶粒中與TSV相關的處理操作和浪費掉的區域來減少成本。因此，可使用標準的處理技術來製造堆疊中之晶片。再者，相較於焊線(wire bonding)，焊料(solder)、微彈簧及/或各向異性導電膜可具有較低的成本及/或可提供增進的可靠性。此外，相較於焊線，斜坡組件可提供較高的組件間通訊頻寬以及減少的潛時(latency)；並且相較於那些由包括TSV之半導體晶粒所提供者可具有差不多的通訊頻寬以及潛時。
現在描述晶片封裝之實施例。圖1代表一方塊圖，其說明一晶片封裝100之側視圖。此晶片封裝(其有時被稱為「斜坡堆疊晶片封裝」)中，一組半導體晶粒110被配置於垂直方向114之堆疊112中。注意：垂直方向114係實質上垂直於堆疊112中之半導體晶粒110-1(而因此，實質上垂直於半導體晶粒110-1中之水平方向116)。此外，各半導體晶粒(在半導體晶粒110-1之後)可從堆疊112中一緊接在前的半導體晶粒以水平方向116被偏移一相關的偏移值118，藉此界定一步進階地120於堆疊112之一側上。這些偏移值可針對該組半導體晶粒110具有一恆定值或者可於該組半導體晶粒110中有變化(亦即，步進階地120中之不同步進的偏移值可為不同)。
再者，高頻寬的斜坡組件122被堅固地機械式耦合至半導體晶粒110。例如，堅固的機械式及/或電耦合至半導體晶粒110(諸如耦合電信號及/或供應電力至半導體晶粒110)可經由焊料球(諸如焊料球138)而發生。此斜坡組件122被置於堆疊112之一側上，且幾乎平行於沿著步進階地120之方向124(以角度126)，其係介於水平方向116與垂直方向114之間。
此外，斜坡組件122可包括：沿著方向124以傳遞光學信號之光學波導128，及一組可將光學信號光學地耦合至及/或自半導體晶粒110之光學耦合組件(諸如光學耦合組件130)，藉此促成一或更多光學信號至及/或自半導體晶粒110之通訊。注意：一既定的光學耦合組件係將光學信號光學地耦合至及/或自一既定的半導體晶粒(因此，光學耦合組件130可將光學信號光學地耦合至及/或自半導體晶粒110-N)。此外，這些光學耦合組件可包括：一繞射光柵、一斜角反射器或鏡、一光束分裂器及/或透鏡。如以下所進一步描述，於某些實施例中，傳遞光學信號至及/或自半導體晶粒110可涉及光學耦合信號之光學近處通訊(其可提供高頻寬且低潛時的通訊)。同時注意：雖然圖1係顯示半導體晶粒110被置於斜坡組件122中之V形溝槽中，但於其他實施例中可能於斜坡組件122中並無此類溝槽(例如，可能有一間隙介於半導體晶粒110與斜坡組件122之間)。
堆疊112中之半導體晶粒110可藉由黏著層132(諸如在150° C於10秒內硬化的環氧樹脂或膠)。再者，該組半導體晶粒110中之一既定半導體晶粒可具有一額定厚度134，而黏著層132可具有一額定厚度136。然而，注意：於某些實施例中，堆疊112中之至少一些半導體晶粒110及/或黏著層132的厚度可為不同(例如，半導體晶粒110和黏著層132之任一或兩者的厚度可沿著垂直方向114而改變)。
於一範例實施例中，厚度134為150±5μm。(然而，於其他實施例中，厚度134可介於30與250μm之間。)。注意：針對介於50與100μm之間的額定厚度134，角度126可介於15與20度之間。一般而言，額定厚度134係取決於(部分地)堆疊112中之半導體晶粒110的數目。再者，注意：黏著層132之額定厚度136可高達600μm。(然而，於其他實施例中，厚度136可小如10μm。)
此外，偏移值118可根據方向124(或角度126)及用以將斜坡組件122堅固地機械式耦合至該組半導體晶粒110之焊料(諸如焊料球138)的額定厚度來決定。注意：焊料之厚度可於堆疊112上幾乎為恆定或者可於堆疊上改變(沿著垂直方向114)。
於某些實施例中，在垂直方向114上涵蓋該組半導體晶粒110之累積的位置誤差(亦即，在涵蓋堆疊112之半導體晶粒的垂直位置中的累積位置誤差)係小於關連與該組半導體晶粒110及介於半導體晶粒110間之黏著層132的垂直誤差之總和。例如，累積位置誤差可關連與：半導體晶粒110之厚度變化、黏著層132之厚度變化、及/或在至少某些黏著層132中之一選擇性熱散佈材料140(諸如壓形的石墨纖維)的厚度變化。於某些實施例中，累積位置誤差可小於1μm，且可小如0μm。此外，該組半導體晶粒110可具有平面中之最大位置誤差(亦即在距離142之最大誤差)，其係關連與半導體晶粒110之邊緣變化(諸如鋸齒線位置中之變化)，其係小於一預界定值(例如，最大位置誤差可小於1μm，且可小如0μm)。此可藉由使用一種拾起並放置工具以使用半導體晶粒110上之光學對準標記(諸如基準標記)來組裝晶片封裝100而完成，以致測得相對於半導體晶粒110之鋸齒道中心的距離142。此外，於組裝期間，半導體晶粒110可參照一組裝組件或配件，其包括一鏡射步進階地120之步進階地(以取代將半導體晶粒110-1後之各半導體晶粒參照堆疊112中其緊接在前的半導體晶粒)。
注意：為了考量垂直方向114上之機械對準誤差，焊料凸塊或墊(諸如焊料墊144-1及/或焊料墊144-2)及/或焊料球138之高度和節距可於至少某些半導體晶粒110之間沿著垂直方向114而改變。注意：距離142(亦即，焊料墊144-1相對於半導體晶粒110-1之鋸齒道中心的位置)可為60μm且焊料墊144可各具有80μm之寬度。再者，焊料球(諸如焊料球138)在重流或熔化之前可具有120μm之直徑，及在熔化後介於40與60μm之間的約略厚度。於某些實施例中，二或更多列的焊料球可將斜坡組件122堅固地耦合至一既定的半導體晶粒。
圖2呈現一方塊圖，其說明晶片封裝100之側視圖。於此範例中，薄膜電晶體210係透過一既定半導體晶粒之邊緣212(亦即，垂直於既定半導體晶粒之邊緣212或平行於法線214)而被光學地耦合至該既定半導體晶粒(諸如半導體晶粒110-N)。如先前所述，於某些實施例中，光學信號210之光學耦合涉及介於斜坡組件122與既定半導體晶粒之間的光學近處通訊。同時注意：於某些實施例中，在既定半導體晶粒從其母晶圓被切開後，係藉由拋光邊緣212以促成光學耦合。此拋光可確保邊緣212之粗糙度小於光學信號210之載波波長。
於某些實施例中，可藉由透過除了與邊緣212相關者以外之既定半導體晶粒的表面以光學地耦合光學信號210，來避免邊緣212之拋光。此係顯示於圖3，其呈現一說明晶片封裝100之側視圖的方塊圖。特別地，光學耦合組件130可沿著一法線310而重新導引光學信號210至斜坡組件122之一表面。接著，光學信號210可經由表面312(而非邊緣212)而進入既定半導體晶粒。因此，光學信號210可透過一關連與鋸齒線之表面而進入既定半導體晶粒，其可為較小的粗糙度且其可具有減少的光學散射或喪失。
雖然先前實施例說明使用斜坡組件122以將光學及/或電信號耦合至及/或自半導體晶粒110，但於其他實施例中，可以有介於半導體晶粒110之間的直接通訊(亦即，直接堆疊內通訊)，相對於經由斜坡組件122的介於半導體晶粒110之間的間接通訊。此係顯示於圖4，其呈現一說明晶片封裝100之側視圖的方塊圖。特別地，光學信號210係直接光學地介於半導體晶粒110中的一對半導體晶粒(諸如半導體晶粒110-1與110-2)之間而不使用斜坡組件122。為了促成此直接通訊(或利用斜坡組件122之通訊)，注意：半導體晶粒110之一或更多可包括：光學波導、光學耦合組件(其可重新安排或改變光學信號210之傳播方向)及/或光源。同時注意：可藉由其執行光學信號210之路由的一或更多半導體晶粒110來促成直接堆疊內通訊。於某些實施例中，直接堆疊內通訊係藉由一或更多半導體晶粒110中的TSV及/或圍繞這些TSV之黏著層中的開口來促成。
圖5呈現一說明晶片封裝100之頂視圖的方塊圖，其中堆疊112(圖1)包括四個半導體晶粒110。晶片封裝100之此視圖說明：於某些實施例中，焊料墊510可具有非矩形的形狀。例如，焊料墊510可具有橢圓形狀，諸如那些具有80μm寬及120μm長的形狀。半導體晶粒110及/或斜坡組件122上之這些焊料墊形狀可承受一些水平及/或垂直位置誤差。
於某些實施例中，焊料墊可被移除至斜坡組件122之邊緣。如此可促成垂直定向(亦即，圖1中之角度126可為0度)。此組態可促成一種記憶體模組，其中關連與輸入/輸出(I/O)信號線及電力線之接點或墊係位於斜坡組件之邊緣上(而非於「脊柱」下)。以此方式，斜坡組件中之數個擴散層可被減少。例如，於此記憶體模組中，可有60個接點或墊沿著斜坡組件122之邊緣。
回來參考圖1，雖然前文說明了介於斜坡組件122與半導體晶粒110之間或介於半導體晶粒110之間的一或更光學信號之通訊，但於其他實施例中，一或更多電信號亦被連通。例如，斜坡組件122可包括一傳遞電信號之信號線。於這些實施例中，斜坡組件122可使用多種技術而被電氣地及/或機械式地至半導體晶粒110，該些技術包括：焊料、微彈簧、微球(以一種坑中球的架構)、及/或各向異性導電膜(諸如各向異性彈性體膜，其有時被稱為「各向異性導電膜」)。電信號至及/或自半導體晶粒110之此通訊可涉及近處通訊(PxC)，諸如經由斜坡組件122及或半導體晶粒110之表面上(或表面附近)的PxC連接器(未顯示)之電容耦合信號的電容耦合近處通訊(其可提供高頻寬及低潛時的通訊)。
因此，於某些實施例中，介於斜坡組件122與半導體晶粒110之間(及，更一般性地，介於晶片封裝的組件之間或介於晶片封裝與外部裝置之間)的通訊可涉及電磁耦合信號之PxC，諸如：電容耦合信號之通訊(其被稱為「電近處通訊」)、電磁耦合信號之通訊(其被稱為「電磁近處通訊」)、電感耦合信號之通訊、及/或導電耦合信號之通訊。
於其中使用PxC以傳遞電信號之實施例中，所得之電接觸的阻抗可(一般地)為傳導性的及/或電容性的，亦即，可具有包括同相組件及/或異相組件之複合阻抗。不論電接觸機制為何(諸如，焊料、微彈簧、各向異性層，等等)，假如與接觸相關之阻抗為傳導性的，則可使用習知的傳輸和接收I/O電路於晶片封裝之實施例中的組件中。然而，針對具有複合(及，可能為可變的)阻抗之接觸，則傳輸和接收I/O電路可包括美國專利申請案12/425,871(由Robert J. Drost等人於2009年四月17日提出申請，案名為「Receive Circuit for Connectors with Variable Complex Impedance」)中所述之一或更多實施例，其內容被併入於此以供參考。
現在描述方法之實施例。圖6呈現一說明一種方法600之流程圖，該方法600係用以傳遞光學信號於晶片封裝之前述實施例之一中。於此方法期間，光學信號被傳遞於斜坡組件中之光學波導中，該斜坡組件被堅固地機械式耦合至該組配置於垂直方向上之垂直堆疊中的半導體晶粒(操作610)。注意：半導體晶粒被彼此偏移於水平方向，藉此界定步進階地於垂直堆疊之一側上。再者，斜坡組件被置於幾乎平行於沿著步進階地之方向的垂直堆疊之一側上，該方向係介於水平方向與垂直方向之間。接著，光學信號係使用一光學耦合組件而被光學地耦合至該組半導體晶粒中之一半導體晶粒(操作612)。
於方法600之某些實施例中，可有額外的或較少的操作。此外，該些操作之順序可被改變，及/或二或更多操作可被結合為單一操作。
現在描述電子裝置之實施例。圖7呈現一方塊圖，其說明一包括晶片封裝710(其可為晶片封裝之前述實施例的一者)之電子裝置700。
於一範例實施例中，一晶片封裝(諸如晶片封裝之前述實施例的一者)可促成高性能的裝置。例如，於某些實施例中，斜坡堆疊晶片封裝被包括於雙線內(in-line)記憶體模組中。例如，可有高達80個記憶體裝置(諸如動態隨機存取記憶體或其他型式的記憶體儲存裝置)於斜坡堆疊晶片封裝中。假如需要的話，「壞的」或故障的記憶體裝置可被除能。因此，可使用72個記憶體裝置(在80個內)。再者，此架構可展現記憶體模組中之記憶體裝置的完整頻寬，以致僅有極少或者沒有潛時延遲於任何記憶體裝置之存取時。
另一方面，雙線內記憶體模組可包括各可包括一斜坡堆疊晶片封裝之多數欄位。例如，可有四個斜坡堆疊晶片封裝(其各包括九個記憶體裝置)於雙線內記憶體模組中。
於某些實施例中，這些雙線內記憶體模組之一或更多(其可包括一或更多斜坡堆疊晶片封裝)可被耦合至一處理器。例如，處理器可使用電容耦合信號之電容性近處通訊而被耦合至一或更多雙線內記憶體模組。接著，處理器可使用C4焊料球而被安裝於一基底上。
因此，電子裝置700可包括一裝置或系統，諸如VLSI電路、開口、集線器、橋、路由器、通訊系統、儲存區域網路、資料中心、網路(諸如局部區域網路)、及/或電腦系統(諸如多核心處理器電腦系統)。再者，電腦系統可包括(但不限定於)：伺服器(諸如多插槽、多框架伺服器)、筆記型電腦、通訊裝置或系統、個人電腦、工作站、主機電腦、刀鋒、企業電腦、資料中心、可攜式計算裝置、超級電腦、網路附加儲存(NAS)系統、儲存區域網路(SAN)系統、及/或其他電子計算裝置。注意：一既定的電腦系統可於一位置上或者可被分布於多數、地理上分散的位置。
晶片封裝100(圖1至5)以及電子裝置700可包括較少的組件或額外的組件。例如，可能有界定於斜坡堆疊晶片封裝中之半導體晶粒堆疊中的斷裂，諸如由於不包括斜坡組件上之一或更多半導體晶粒的焊料墊。此外，晶片封裝之一實施例中的一或更多組件可包括：一光學調變器、一光學多工器(諸如增加濾波器)、一光學解多工器(諸如刪除濾波器)、一光學濾波器及/或一光學開關。
此外，雖然這些裝置及系統被顯示為具有數個離散項目，但這些實施例應被視為可能出現之各種特徵的功能性描述而非此處所述之實施例的結構示意圖。結果，於這些實施例中，二或更多組件可被結合為單一組件及/或一或更多組件之位置可被改變。此外，前述實施例中之功能可被較多地實施於硬體而較少地實施於軟體，或者較少於硬體而較多於軟體，如本技術中所已知者。
雖然前述實施例係使用晶片封裝中之半導體晶粒(諸如矽)，但於其他實施例中，可將半導體之外的不同材料使用為一或更多這些晶片中的基底材料。然而，於其中使用矽之實施例中，可使用標準的矽處理來製造半導體晶粒110(圖1至5)。這些半導體晶粒可提供支援邏輯及/或記憶體功能之矽區域。
再者，回來參考圖1，斜坡組件122可為被動組件，諸如具有用以電耦合至半導體晶粒110之金屬軌跡的塑膠基底。例如，斜坡組件122可使用射出成型塑膠。另一方面，斜坡組件122可為另一具有一或更多微影界定的佈線、信號線或光學波導之半導體晶粒。例如，光學波導128(圖1至5)可使用絕緣體上之矽的技術來實施。於其中斜坡組件122包括半導體晶粒之實施例中，可包括主動裝置(諸如限制放大器)以減少信號線之間的串音。此外，可使用差動發信以減少主動或被動斜坡組件122中之串音。
於某些實施例中，斜坡組件122包括電晶體及佈線，其係經由焊料球(諸如焊料球138)以將資料及電力信號來回移動於半導體晶粒110之間。例如，斜坡組件122可包括高電壓信號。這些信號可使用如下元件而被降壓以供用於半導體晶粒110：降壓調整器(諸如電容至電容降壓調整器)、以及電容及/或電感離散組件，以耦合至半導體晶粒110。
此外，斜坡組件122可包括一用於記憶體之緩衝器或邏輯晶片、及/或通至外部裝置及/或系統之I/O連接器。例如，I/O連接器可包括一或更多：焊球、焊線、邊緣連接器及/或PxC連接器，用以耦合至外部裝置。於某些實施例中，這些I/O連接器可位於斜坡組件122之背部表面上，且斜坡組件122可包括一或更多矽穿孔(TSV)，其係將I/O連接器耦合至靠近半導體晶粒110之額外連接器，諸如PxC連接器或焊料墊(例如，焊料墊144-2)。
於某些實施例中，斜坡組件122及半導體晶粒110被安裝於一可選基底上(諸如印刷電路板或半導體晶粒)。此可選基底可包括：焊球、焊線、邊緣連接器及/或PxC連接器，用以耦合至外部裝置。假如這些I/O連接器係位於可選基底之背部表面上，則可選基底可包括一或更多TSV。
如先前所述，於某些實施例中，可選的散熱材料140(及，更一般性地，介於具有高熱傳導性的半導體晶粒110之間的中間材料)可協助移除在一或更多半導體晶粒110及/或斜坡組件122上於電路之操作期間所產生的熱。此熱管理可包括任何下列熱路徑：於半導體晶粒110之平面中的第一熱路徑；於黏著層132之平面中的第二熱路徑；及/或於可選的散熱材料140之平面中的第三熱路徑。特別地，與這些熱路徑關連的熱通量可經由晶片封裝之一邊緣上的熱耦合而被彼此獨立地管理。注意：此熱管理可包括使用：相位改變冷卻、浸沒冷卻、及/或冷卻板。同時注意：與第一熱路徑關連的熱通量(其擴散通過晶片封裝之邊緣上的橫斷面區域)為額定厚度134之函數。因此，晶片封裝中之熱管理可隨著半導體晶粒110之較大或較小額定厚度而不同。
雖然前述實施例說明晶片封裝之特定架構，但數種技術和架構亦可被用於實施組件之機械對準。例如，半導體晶粒110及/或斜坡組件122可使用一種球與坑對準技術(及，更一般性地，負特徵中之正特徵的對準技術)而相對於彼此地定位。特別地，球可被置於蝕刻坑中以機械式地耦合及相對地對準堆疊112中之半導體晶粒110。於其他實施例中，可使用多種正特徵，諸如半球狀凸塊。因此，一般而言，晶片封裝中之組件上的機械式鎖定的正與負表面特徵之組合可被使用以對準及/或組裝晶片封裝。
注意：當面對較低的半導體晶粒產量或者用以在封裝與組裝前廣泛地測試所需的高花費時，容許某項再加工之封裝技術是更為成本效益高的。因此，於其中介於半導體晶粒110與斜坡組件122之間的機械式、光學及/或電耦合是可重配對的實施例中，可藉由容許再加工(諸如替換一個在組裝、測試或預燒期間被發現為壞的晶片)以增加晶片封裝之產量。在這方面，可重配對的機械式、光學及/或電耦合應被理解成可被重複地(亦即，二或更多次)建立及打斷而無須再加工或加熱(諸如利用焊料)之機械式、光學及/或電耦合。於某些實施例中，可重配對的機械式、光學及/或電耦合係涉及設計成彼此耦合之陽性及陰性組件(諸如扣合在一起的組件)。
於某些實施例中，可以有可選的囊封於前述實施例中之晶片封裝的至少一部分周圍。此外，介於晶片封裝中的組件間之空氣間隙可被填充以增進熱移除。此可藉由減少角度126來促成，亦即，110可被更朝向垂直方向114地傾斜。
以上描述係為了使任何熟悉此項技術人士得以製造及使用本發明，且係在特定應用及其需求之背景下提供。此外，本發明之實施例的先前描述僅為了說明及描述之目的而提供。其並非想要排除其他或限制本發明於所揭露之形式。因此，對於熟悉此項技術之從業人員而言，許多修飾及改變將是很顯見的，且此處所界定之一般性原則可被應用於其他的實施例及應用而不背離本發明之精神及範圍。此外，先前實施例之討論並不是要限制本發明。因此，本發明不應被限制於所示之實施例，而應包括符合此處所揭露之原則和特徵的最廣範圍。
100．．．晶片封裝
110．．．半導體晶粒
110-1,110-2．．．半導體晶粒
110-N．．．半導體晶粒
112．．．堆疊
114．．．垂直方向
116．．．水平方向
118．．．偏移值
118-1,118-N-1．．．偏移值
120．．．步進階地
122．．．斜坡組件
124．．．方向
126．．．角度
128．．．光學波導
130．．．光學耦合組件
132．．．黏著層
134．．．厚度
136．．．厚度
138．．．焊料球
140．．．散熱材料
142．．．距離
144-1．．．焊料墊
144-2．．．焊料墊
210．．．光學信號
212．．．邊緣
214．．．法線
310．．．法線
510．．．焊料墊
700．．．電子裝置
710．．．晶片封裝
圖1係一方塊圖，其說明依據本發明之一實施例的晶片封裝之側視圖。
圖2係一方塊圖，其說明依據本發明之一實施例之圖1中的晶片封裝之側視圖。
圖3係一方塊圖，其說明依據本發明之一實施例之圖1中的晶片封裝之側視圖。
圖4係一方塊圖，其說明依據本發明之一實施例之圖1中的晶片封裝之側視圖。
圖5係一方塊圖，其說明依據本發明之一實施例之圖1中的晶片封裝之頂視圖。
圖6係一方塊圖，其說明一種用以傳遞光學信號於一依據本發明之一實施例的晶片封裝中之方法。
圖7係一方塊圖，其說明一種包括一依據本發明之一實施例的晶片封裝之電子裝置。
注意：類似的參考數字係參照所有圖式中之相應的部件。再者，相同部件之諸多實例是由一共同字首(以破折號分隔其實例編號)來標示。
100．．．晶片封裝
110-1,110-2．．．半導體晶粒
110-N．．．半導體晶粒
112．．．堆疊
114．．．垂直方向
116．．．水平方向
118-1,118-N-1．．．偏移值
120．．．步進階地
122．．．高頻寬的斜坡組件
124．．．方向
126．．．角度
128．．．光學波導
130．．．光學耦合組件
132．．．黏著層
134．．．厚度
136．．．厚度
138．．．焊料球
140．．．散熱材料
142．．．距離
144-1．．．焊料墊
144-2．．．焊料墊

Claims (20)

  1. 一種晶片封裝，包含：一組配置在垂直方向之垂直堆疊中的半導體晶粒，其係實質上垂直於該垂直堆疊中之第一半導體晶粒，其中在該第一半導體晶粒後之各半導體晶粒從該垂直堆疊中緊接在前的半導體晶粒以水平方向被偏移一偏移值，藉此界定一步進階地於該垂直堆疊之一側上；及一斜坡組件，其被堅固地機械式耦合至該些半導體晶粒，其中該斜坡組件被置於該垂直堆疊之該一側上；其中該斜坡組件係幾乎平行於沿著該步進階地之方向，其係介於水平方向與垂直方向之間；及其中該斜坡組件包括：一光學波導，其組態成傳遞光學信號；及一光學耦合組件，其組態成將該光學信號光學地耦合至該組半導體晶粒中之一半導體晶粒。
  2. 如申請專利範圍第1項之晶片封裝，其中該斜坡組件包括一組光學耦合組件，其包括該光學耦合組件；及其中該組光學耦合組件中之一既定的光學耦合組件係組態成將該光學信號光學地耦合至包括該半導體晶粒之該組半導體晶粒中之一既定的半導體晶粒。
  3. 如申請專利範圍第1項之晶片封裝，其中該光學波導係組態成於沿著該步進階地之方向傳遞該光學信號；及其中該光學耦合組件將該光學信號重新導引入該半導體晶粒之一平面。
  4. 如申請專利範圍第3項之晶片封裝，其中該光學信號係透過該半導體晶粒之一邊緣而被光學地耦合至該半導體晶粒。
  5. 如申請專利範圍第1項之晶片封裝，其中該光學波導係組態成於沿著該步進階地之方向傳遞該光學信號；及其中該光學耦合組件係沿著該半導體晶粒之表面的一法線而重新導引該光學信號。
  6. 如申請專利範圍第5項之晶片封裝，其中該光學信號於該半導體晶粒之邊緣以外的該半導體晶粒之表面上的位置被光學地耦合至該半導體晶粒。
  7. 如申請專利範圍第1項之晶片封裝，其中該組半導體晶粒中之一對半導體晶粒係組態成將來自該對中之第一半導體晶粒的該光學信號光學地耦合至該對中之第二半導體晶粒而不使用該斜坡組件。
  8. 如申請專利範圍第1項之晶片封裝，其中該斜坡組件被製造於半導體以外的材料上。
  9. 如申請專利範圍第1項之晶片封裝，其中該斜坡組件為另一半導體晶粒。
  10. 如申請專利範圍第1項之晶片封裝，其中該斜坡組件被耦合至每一半導體晶粒，其係使用下列之至少一者：焊料、微彈簧及各向異性導電膜。
  11. 一種包含晶片封裝之電子裝置，其中該晶片封裝包括：一組配置在垂直方向之垂直堆疊中的半導體晶粒，其係實質上垂直於該垂直堆疊中之第一半導體晶粒，其中在該第一半導體晶粒後之各半導體晶粒從該垂直堆疊中緊接在前的半導體晶粒以水平方向被偏移一偏移值，藉此界定一步進階地於該垂直堆疊之一側上；及一斜坡組件，其被堅固地機械式耦合至該些半導體晶粒，其中該斜坡組件被置於該垂直堆疊之該一側上；其中該斜坡組件係幾乎平行於沿著該步進階地之方向，其係介於水平方向與垂直方向之間；及其中該斜坡組件包括：一光學波導，其組態成傳遞光學信號；及一光學耦合組件，其組態成將該光學信號光學地耦合至該組半導體晶粒中之一半導體晶粒。
  12. 如申請專利範圍第11項之電子裝置，其中該斜坡組件包括一組光學耦合組件，其包括該光學耦合組件；及其中該組光學耦合組件中之一既定的光學耦合組件係組態成將該光學信號光學地耦合至包括該半導體晶粒之該組半導體晶粒中之一既定的半導體晶粒。
  13. 如申請專利範圍第11項之電子裝置，其中該光學波導係組態成於沿著該步進階地之方向傳遞該光學信號；及其中該光學耦合組件將該光學信號重新導引入該半導體晶粒之一平面。
  14. 如申請專利範圍第13項之電子裝置，其中該光學信號係透過該半導體晶粒之一邊緣而被光學地耦合至該半導體晶粒。
  15. 如申請專利範圍第11項之電子裝置，其中該光學波導係組態成於沿著該步進階地之方向傳遞該光學信號；及其中該光學耦合組件係沿著該半導體晶粒之表面的一法線而重新導引該光學信號。
  16. 如申請專利範圍第15項之電子裝置，其中該光學信號於該半導體晶粒之邊緣以外的該半導體晶粒之表面上的位置被光學地耦合至該半導體晶粒。
  17. 如申請專利範圍第11項之電子裝置，其中該組半導體晶粒中之一對半導體晶粒係組態成將來自該對中之第一半導體晶粒的該光學信號光學地耦合至該對中之第二半導體晶粒而不使用該斜坡組件。
  18. 如申請專利範圍第11項之電子裝置，其中該斜坡組件被製造於半導體以外的材料上。
  19. 如申請專利範圍第11項之電子裝置，其中該斜坡組件為另一半導體晶粒。
  20. 一種用以傳遞光學信號之方法，包含：傳遞該光學信號於斜坡組件中之一光學波導中，該斜坡組件被堅固地機械式耦合至一組配置在垂直方向之垂直堆疊中的半導體晶粒，其中該些半導體晶粒被彼此偏移於水平方向，藉此界定步進階地於該垂直堆疊之一側上，及其中該斜坡組件被置於幾乎平行於沿著步進階地之方向的該垂直堆疊之該一側上，其係介於水平方向與垂直方向之間；及使用一光學耦合組件以將來自該光學波導之該光學信號光學地耦合至該組半導體晶粒中之一半導體晶粒。
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