TWI830800B - 積體電路封裝件 - Google Patents

積體電路封裝件 Download PDF

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Publication number
TWI830800B
TWI830800B TW108139228A TW108139228A TWI830800B TW I830800 B TWI830800 B TW I830800B TW 108139228 A TW108139228 A TW 108139228A TW 108139228 A TW108139228 A TW 108139228A TW I830800 B TWI830800 B TW I830800B
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Taiwan
Prior art keywords
die
integrated circuit
package
molded portion
circuit package
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TW108139228A
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English (en)
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TW202034001A (zh
Inventor
郭豐維
周淳朴
陳碩懋
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台灣積體電路製造股份有限公司
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    • H01L23/5386—Geometry or layout of the interconnection structure
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Abstract

一種將光子晶粒（oDie）和電子晶粒（eDie）集成的積體電路封裝件。更確切地說，積體電路封裝件可包含以通訊方式耦合到光子晶粒和/或電子晶粒中的至少一個的多個重分佈層，其中模塑材料至少部分地包圍光子晶粒和/或電子晶粒中的至少一個。

Description

積體電路封裝件
本發明實施例是關於積體電路封裝件及其製作方法。
常規封裝技術大致上包含分割晶圓且隨後將單獨晶粒封裝在經切割的晶圓片上。由於在已切割晶圓之後封裝單獨晶粒，因此封裝件大小往往會顯著大於晶粒大小。相比之下，在標準晶圓級封裝技術中，在使晶圓的部分靜止時封裝積體電路，且隨後切割晶圓。因此，所得封裝件通常與晶粒自身大小相同。然而，由於可容納於有限封裝件佔據面積中的外部接觸件的數量有限，因此有封裝件較小的優點也有不利方面。在一些情況下，這可以在考慮需要大量接觸件的複雜半導體器件時變成明顯的限制。
在一實施例中，一種積體電路封裝件，包括：光子晶粒(oDie)，包含至少一個光學元件；電子晶粒(eDie)；基底，包含多個重分佈層，所述多個重分佈層通訊耦合到所述光子晶粒和/或所述電子晶粒中的至少一個，其中所述基底包括模塑部分，所述模塑部分至少部分地包圍所述光子晶粒和/或所述電子晶粒中的所述至少一個；以及接續段，將所述光子晶粒和/或電子晶粒中的所述至少一個電耦合到至少一個 重分佈層，所述至少一個重分佈層定位成鄰近於所述積體電路封裝件的最上層。
104:第一封裝件
108、236、336、436、536:eDie
112、260、360、460、560:光纖
116、240、340、440、540:oDie
117、264、364、464、564、832:光學內連線
120、208、220、252、286A、286B、308、320、352、386A、386B、408、420、452、486A、486B、508、520、552、586A、586B、806、808、810、842、844、845、846、848、850、852、854、856:重分佈層
124、128:微凸塊
132、390、490、590、592、866、868、870:凸塊
136:矽穿孔
140:oDie封裝部分
144:第一連接部分
148:矽層
152:第二連接部分
156:保護材料
200:第二封裝件
204、304、404、504:基底
212、216、224、312、316、324、412、416、424、512、516、524、840、841、858:保護層
218、248、318、348、388、418、448、488、518、548:通孔
228、328、428、528:凸塊下金屬化層
232A~232C、332A~332C、432A~432C、532A~532C:連接件
246、346、446、546:背側重分佈層
270、370、470、570:導電部分
272、372、472、572、814、816、818、820、822:TIV
276、376、476、576:介接部分
282、382、482、582:絕緣部分
284A、284B、384A、384B、484A、484B、584A、584B:襯墊
300:第三封裝件
400:第四封裝件
500:第五封裝件
588:插入件
600:系統
604:光子封裝件
608:處理子系統
612:記憶體子系統
704、708、712、716、720、724、728、732:步驟
802:膜
804:玻璃載體基底
812:光阻層
824、838:導電材料
828:晶粒附接膜
830:O-Die
834:E-Die
836:模塑化合物
860、862、864:UBM
872:部分
874:光纖陣列
當結合附圖閱讀時，從以下詳細描述最好地理解本公開的各方面。應注意，根據業界中的標準慣例，各個特徵未按比例繪製。實際上，為了論述清楚起見，可以任意增大或減小各種特徵的尺寸。
圖1描繪根據一些實施例的光子封裝件的第一實例的橫截面圖。
圖2A到圖2B描繪根據一些實施例的光子封裝件的第二實例的橫截面圖。
圖3A到圖3B描繪根據一些實施例的光子封裝件的第三實例的橫截面圖。
圖4A到圖4B描繪根據一些實施例的光子封裝件的第四實例的橫截面圖。
圖5A到圖5B描繪根據一些實施例的光子封裝件的第五實例的橫截面圖。
圖6描繪根據一些實施例的併入光子封裝件的系統。
圖7描繪根據一些實施例的用於形成光子封裝件的方法的流程圖。
圖8A到圖8P說明根據一些實施例的用於製造光子封裝件的製程的步驟。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同實施例或實例。下文描述元件和佈置的特定實例來簡化本公開。當然，這些只是實例且並不意欲為限制性的。舉例來說，在以下描述中，第一特徵在第二特徵上方或上的形成可包括第一特徵和第二特徵直接接觸地形成的實施例，且還可包括額外特徵可在第一特徵與第二特徵之間形成以使得第一特徵和第二特徵可不直接接觸的實施例。另外，本公開可在各個實例中重複附圖標號和/或字母。這種重複是出於簡單和清晰的目的，且本身並不指示所論述的各種實施例和/或配置之間的關係。
另外，在本文中為易於描述，可使用例如「在......下」、「在......下方」、「下部」、「在......上方」、「上部」以及類似術語的空間相對術語來描述如圖中所說明的一個元件或特徵與另一元件或特徵的關係。除了圖中所描繪的定向之外，空間相對術語意圖涵蓋器件在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用的空間相對描述詞可同樣相應地進行解釋。
當將例如雷射器、光學調節器、光學檢測器以及光學開關的光學元件併入到封裝電子模組中時，常規封裝技術和標準晶圓級(wafer level)封裝技術通常可導致低密度引腳計數、更大的外觀尺寸以及更高的成本。舉例來說，積體電路可經由微凸塊附接到例如矽插入件的插入件且隨後經由導電膠連接到印刷電路板。當光纖陣列位於插入件上時，來自與光纖陣列介接的積體電路的連接、電源和/或資料，通過插入件內的一或多個軌線和導線接合的連接，從微凸塊佈線到位於PCB處的外部襯墊。當導線接合可具成本效益和為靈活的時，導線接合技術可遭受安全性問題且通常導致封裝件大小更大。
包含一或多個光學模組的多晶片模組可包含與光學模組通訊的積體電路。在一些情況下，可採用倒裝晶片封裝技術，使得積體電路和光學模組以通訊方式彼此耦合且利用一或多個凸塊附接到基底。在一些情況下，插入件可駐留在積體電路與光學模組之間，使得連接(例如耦合到積體電路和/或光學模組且耦合到基底的連接)可散佈到更寬的間距且/或將連接重佈線到不同的連接。在一些情況下，插入件可利用矽穿孔(through-silicon via；TSV)來將插入件連接到基底，同時積體電路和光學模組可利用現有連接方法(例如凸塊連接)附接到插入件。在一些情況下，插入件可為用於將光從例如雷射器的光源導向和/或導引到封裝件中的另一位置的光子插入件。這類多晶片模組通常具有更大的外觀尺寸、更高的成本，且通常具有較低的密度和引腳計數。
本文中所描述的實施例公開了將光子晶粒(photonic die；oDie)和電子晶粒(electronic die；eDie)集成到一個封裝件中的先進封裝技術。在一些情況下，除了oDie和eDie之外的組件也可包含於封裝件中。舉例來說，封裝件可包含oDie、eDie以及形成內連線封裝件的開關ASIC。eDie的元件可包含但不限於以下中的至少一個：一或多個串列器/並行器(串列並行器(serde))、一或多個收發信機、時鐘電路以及控制邏輯和電路。eDie與開關ASIC的集成可以縮短串列並行器與開關邏輯之間的距離，這反過來可以減小串列並行器的大小和功率消耗。在一些情況下，矽穿孔可用於基底中以電連接各種元件。在本文中所描述的其他實施例中，oDie可與一種或多種額外的光子組件集成於單個積體電路封裝件中。eDie隨後可經由一或多個凸塊附接到積體電路封裝件。
如本文中所描述，封裝件可利用集成扇出型(Integrated Fan-Out；InFO)技術來將可包含光子積體電路應用的多個晶粒集成到積體電路封裝件封裝件(又稱為晶圓級封裝件)中。因此，可獲得能夠操控高引腳計數(例如具有高引腳和元件密度)同時具有小外觀尺寸的先進封裝件。由於可利用InFO技術，因此這種封裝件可高度集成且可比傳統封裝技術製造成本更低。先進的封裝件可適用於高速電路。
至少由於扇出型封裝利用單獨晶粒且將其包埋於例如環氧樹脂模塑化合物或其他材料的材料中以及針對額外I/O連接點在每一晶粒之間分配空間，InFO封裝技術不同於其他封裝技術。因此，可避免使用矽基板面來容納更高引腳計數。此外，重分佈層可用以將一些I/O連接佈線/重佈線到邊緣區域，進一步增加到更高封裝件引腳計數密度和接觸件利用率。
圖1描繪根據本公開的一些實施例的第一封裝件104的橫截面圖。更確切地說，第一封裝件可利用積體電路封裝技術(如InFO封裝技術)且提供耦合到光學內連線117的光纖112，其中光學內連線117可特定地配置成接收光且將所接收光提供到oDie 116以用於進一步處理。也就是說，當經由光纖在第一封裝件104處接收光時，第一封裝件104配置成將光轉換成電信號。一或多個光學內連線117可接收光，且經由光學波導將光導向或導引到定位於oDie 116處的一或多個檢測器。oDie 116的一或多個檢測器可檢測光且隨後將光轉換成一或多個對應的電信號。一或多個電信號可流動通過重分佈層120到例如eDie 108，其中eDie 108可進一步處理所接收的一或多個電信號。oDie 116可經由重分佈層120和一或多個凸塊(例如oDie 116的微凸塊124和eDie 108的微凸塊128)耦合到eDie 108。eDie 108可處理 一或多個電信號且經由重分佈層120和矽穿孔136將一或多個處理過的電信號提供到凸塊132以用於連接到另一晶粒的印刷電路板。
第一封裝件104可包含一或多個部分。舉例來說，第一封裝件104可包含eDie 108、光纖112以及oDie封裝部分140。oDie封裝部分140可包含第一連接部分144、一或多個重分佈層120、一或多個oDie 116、一或多個矽層148、一或多個矽穿孔136以及一或多個第二連接部分152。一個或多個第一連接部分144可包含一或多個如先前所論述的凸塊124；一或多個第二連接部分152可包含一或多個凸塊132。eDie 108、oDie封裝部分140以及光纖112可封裝於保護材料156中，其中可暴露一或多個第二連接部分152中的一或多個凸塊132以用於連接到印刷電路板、其他晶粒和/或外部連接。舉例來說，第一封裝件104可耦合到日誌和/或記憶體。
圖2A描繪根據本公開的實施例的第二封裝件200的橫截面圖。圖2B描繪圖2A中所描繪的第二封裝件200的放大部分。類似於第一封裝件104，第二封裝件200可利用積體電路封裝技術，如InFO封裝技術。第二封裝件可包含基底204。基底204可包含模具材料、矽材料和/或其他基本上絕緣的或半導體材料。封裝件200可包含形成於基底204頂部上、直接接觸基底204且/或佈置在基底204上的保護層212。保護層212可包含聚醯亞胺和/或聚苯並惡唑材料。保護層212可為在封裝之前用作保護層或「緩衝塗層」或用作重分佈層252的應力消除塗層。在形成保護層212之前，一或多個重分佈層208可形成於基底204頂部上、直接接觸基底204且/或佈置在基底204的至少一部分上。另一保護層216可形成於保護層212和重分佈層252的至少一部分上。在一些實施例中，一或多個通孔218可形成於保護層216和/ 或保護層212內。在一些情況下，第一通孔可在形成第一保護層212之後形成，而第二通孔可在形成第二保護層216之後形成。或者或另外，第一通孔和/或第二通孔可在已形成保護層212和保護層216之後形成。舉例來說，可移除保護層216的一或多個部分；例如，可蝕刻、鑽孔所述一或多個部分和/或使其曝露於光，以在保護層212和/或保護層216中形成第一孔。絕緣材料隨後可置於第一孔內以加襯所述孔的側邊。最終，導電材料可置於所述孔中，由此形成一或多個通孔218。
封裝件200可包含一或多個重分佈層220，所述重分佈層形成於保護層216上、形成於保護層216頂部上、直接接觸保護層216或以其他方式佈置在保護層216上。在一實施例中，保護層224可形成於保護層216上、形成於保護層216頂部上、直接接觸保護層216或以其他方式佈置在保護層216上。可移除保護層224的一或多個部分。舉例來說，可將所述一或多個部分蝕刻、鑽孔、曝露於光等，且由此在保護層224中形成孔。隨後，重分佈層220可形成於重分佈層220的一或多個孔內。最後，一或多個凸塊下金屬化層228可形成於重分佈層220上；所述一或多個凸塊下金屬化層228可配置成接收焊球和/或連接件232A到連接件232C，以形成例如球柵陣列。
如先前所論述，封裝件200可包含重分佈層208；重分佈層208可提供經由介接部分276從光學晶粒(optical die；oDie)240和/或一或多個eDie 236中的一或多個到連接件232A到連接件232C中的一或多個的信號路徑。連接部分244可包含重分佈層286A和/或重分佈層286B、一或多個襯墊284A和襯墊284B、一或多個導電部分270以及一或多個絕緣部分282中的一或多個。積體電路封裝穿孔(through integrated circuit package via)或絕緣體穿孔(through insulator via；TIV) 272可形成於基底204中。舉例來說，TIV 272可將重分佈層208耦合到背側重分佈層246。舉例來說，背側重分佈層246可將重分佈層208耦合到一或多個重分佈層252。因此，可形成將重分佈層252耦合到一或多個重分佈層286A和/或重分佈層286B的通孔248。重分佈層286A和/或重分佈層286B可形成於襯墊284A和/或襯墊284B正上方或以其他方式佈置在襯墊284A和/或襯墊284B上。襯墊284A和/或襯墊284B可佈置在包含絕緣材料的絕緣部分282內；因此，襯墊284A和/或襯墊284B中的一或多個可經由導電部分270耦合到oDie和/或eDie 236。
如先前所論述，oDie 240可耦合到光學內連線264，所述光學內連線可配置成接收來自光纖260的光和/或將所述光傳送到oDie 240的檢測器部分。因此，開口可存在於封裝件200的光纖陣列接收側。oDie 240可將光轉換成一或多個電信號並將所述一或多個電信號傳輸或以其他方式提供到eDie 236和/或外部連接，例如連接件232A到連接件232C中的一或多個。可通過封裝件200經由重分佈層、一或多個通孔、一或多個TIV、一或多個襯墊284A和/或襯墊284B以及一或多個導電部分270中的一或多個傳輸一或多個電信號。
根據本公開的一些實施例，oDie 240和eDie 236可駐留在封裝件200內。舉例來說，空腔、孔或其他部分可形成或以其他方式存在於基底204中。一或多個oDie 240和/或一或多個eDie 236中的每一個可駐留在例如橫截面圖中的兩側上的TIV之間。此外，基底材料204可包含環氧基或另外為環氧基。在一些實施例中，oDie 240和/或eDie 236可直接連接到導電部分270中的一或多個或以其他方式佈置在所述導電部分中的一或多個上。
圖3A描繪根據本公開的實施例的第三封裝件300的橫截面圖。圖3B描繪圖3A中所描繪的第三封裝件300的放大部分。類似於第一封裝件104和第二封裝件200，第三封裝件300可利用積體電路封裝技術。第三封裝件可包含基底304。基底304可包含模具材料、矽材料和/或其他基本上絕緣的或半導體材料。封裝件300可包含形成於基底304頂部上、直接接觸基底304且/或佈置在基底304上的保護層312。保護層312可包含聚醯亞胺和/或聚苯並惡唑材料。保護層312可為在封裝之前用作保護層或「緩衝塗層」或用作重分佈層352的應力消除塗層。在形成保護層312之前，一或多個重分佈層308可形成於基底304頂部上、直接接觸基底304且/或佈置在基底304的至少一部分上。另一保護層316可形成於保護層312和重分佈層352的至少一部分上。在一些實施例中，一或多個通孔318可形成於保護層316和/或保護層312內。在一些情況下，第一通孔可在形成第一保護層312之後形成，而第二通孔可在形成第二保護層316之後形成。或者或另外，第一通孔和/或第二通孔可在已形成保護層312和保護層316之後形成。舉例來說，可移除保護層316的一或多個部分；例如，可蝕刻、鑽孔所述一或多個部分和/或使其曝露於光，以在保護層312和/或保護層316中形成第一孔。絕緣材料隨後可置於第一孔內以加襯所述孔的側邊。最終，導電材料可置於所述孔中，由此形成一或多個通孔318。
封裝件300可包含一或多個重分佈層320，所述重分佈層形成於保護層316上、形成於保護層316頂部上、直接接觸保護層316或以其他方式佈置在保護層316上。在一實施例中，保護層324可形成於保護層316上、形成於保護層316頂部上、直接接觸保護層316或以其他方式佈置在保護層316上。可移除保護層324的一或多個部 分。舉例來說，可將所述一或多個部分蝕刻、鑽孔、曝露於光等，且由此在保護層324中形成孔。隨後，重分佈層320可形成於重分佈層320的一或多個孔內。最後，一或多個凸塊下金屬化層328可形成於重分佈層320上；所述一或多個凸塊下金屬化層328可配置成接收焊球和/或連接件332A到連接件332C，以形成例如球柵陣列。
如先前所論述，封裝件300可包含重分佈層308；重分佈層308可提供經由介接部分376從光學晶粒(oDie)340和/或一或多個eDie 336中的一或多個到連接件332A到連接件332C中的一或多個的信號路徑。連接部分344可包含重分佈層386A和/或重分佈層386B中的一或多個、一或多個襯墊384A和襯墊384B、一或多個導電部分370以及一或多個絕緣部分382。積體電路封裝穿孔(TIV)或絕緣體穿孔372可形成於基底304中。舉例來說，TIV 372可將重分佈層308耦合到背側重分佈層346。舉例來說，背側重分佈層346可將重分佈層308耦合到一或多個重分佈層352。因此，可形成將重分佈層352耦合到一或多個重分佈層386A和/或重分佈層386B的通孔348。重分佈層368A和/或重分佈層386B可形成於襯墊384A和/或襯墊384B正上方或以其他方式佈置在襯墊384A和/或襯墊384B上。襯墊384A和/或襯墊384B可佈置在包含絕緣材料的絕緣部分382內；因此，襯墊384A和/或襯墊384B中的一或多個可經由導電部分370耦合到eDie 336。
oDie 340可耦合到光學內連線364，所述光學內連線可配置成接收來自光纖360的光和/或將所述光傳送到oDie 340的檢測器部分。因此，開口可存在於封裝件300的光纖陣列接收側。oDie 340可將光轉換成一或多個電信號並將所述一或多個電信號傳輸或以其他方式提供到eDie 336和/或外部連接，例如連接件332A到連接件332C 中的一或多個。可通過封裝件300經由重分佈層、一或多個通孔、一或多個TIV、一或多個襯墊384A和/或襯墊384B以及一或多個導電部分370中的一或多個傳輸一或多個電信號。
根據本公開的一些實施例，oDie 340和eDie 336可駐留在封裝件300內。舉例來說，空腔、孔或其他部分可形成或以其他方式存在於基底304中。一或多個oDie 340和/或一或多個eDie 336中的每一個可駐留在例如橫截面圖中的兩側上的TIV之間。此外，基底材料304可包含環氧基或另外為環氧基，使得基底材料可在eDie 336、oDie 340以及一或多個TIV中的一或多個之間。在一些實施例中，eDie 336可直接連接到導電部分370和絕緣部分382中的一或多個或以其他方式佈置在所述導電部分和所述絕緣部分中的一或多個上。
如圖3A到圖3B中進一步描繪，eDie 336可定位於oDie 340與絕緣部分382之間。因此，oDie 340可經由一或多個通孔388和一或多個凸塊390耦合到eDie 336。根據至少一個實例，oDie 340可經倒裝晶片接合到eDie 346，而封裝件300採用積體電路封裝技術。
圖4A描繪根據本公開的實施例的第四封裝件400的橫截面圖。圖4B描繪圖4A中所描繪的第四封裝件400的放大部分。類似於第一封裝件104、第二封裝件200以及第三封裝件300，第四封裝件400可利用積體電路封裝技術。第四封裝件可包含基底404。基底404可包含模具材料、矽材料和/或其他基本上絕緣的或半導體材料。封裝件400可包含形成於基底404頂部上、直接接觸基底404且/或佈置在基底404上的保護層412。保護層412可包含聚醯亞胺和/或聚苯並惡唑材料。保護層412可為在封裝之前用作保護層或「緩衝塗層」或用作重分佈層452的應力消除塗層。在形成保護層412之前，一或多個 重分佈層408可形成於基底404頂部上、直接接觸基底404且/或佈置在基底404的至少一部分上。另一保護層416可形成於保護層412和重分佈層452的至少一部分上。在一些實施例中，一或多個通孔418可形成於保護層416和/或保護層412內。在一些情況下，第一通孔可在形成第一保護層412之後形成，而第二通孔可在形成第二保護層416之後形成。或者或另外，第一通孔和/或第二通孔可在已形成保護層412和保護層416之後形成。舉例來說，可移除保護層416的一或多個部分；例如，可蝕刻、鑽孔所述一或多個部分和/或使其曝露於光，以在保護層412和/或保護層416中形成第一孔。絕緣材料隨後可置於第一孔內以加襯所述孔的側邊。最終，導電材料可置於所述孔中，由此形成一或多個通孔418。
封裝件400可包含一或多個重分佈層420，所述重分佈層形成於保護層416上、形成於保護層416頂部上、直接接觸保護層416或以其他方式佈置在保護層416上。在一實施例中，保護層424可形成於保護層416上、形成於保護層416頂部上、直接接觸保護層416或以其他方式佈置在保護層416上。可移除保護層424的一或多個部分。舉例來說，可將所述一或多個部分蝕刻、鑽孔、曝露於光等，且由此在保護層424中形成孔。隨後，重分佈層420可形成於重分佈層420的一或多個孔內。最後，一或多個凸塊下金屬化層428可形成於重分佈層420上；所述一或多個凸塊下金屬化層428可配置成接收焊球和/或連接件432A到連接件432C，以形成例如球柵陣列。
如先前所論述，封裝件400可包含重分佈層408；重分佈層408可提供經由介接部分476從光學晶粒(oDie)440和/或一或多個eDie 436中的一或多個到連接件432A到連接件432C中的一或多個的 信號路徑。連接部分可包含重分佈層486A和/或重分佈層486B中的一或多個、一或多個襯墊484A和襯墊484B、一或多個導電部分470以及一或多個絕緣部分482。絕緣體穿孔(TIV)472(或積體電路封裝穿孔)可形成於基底404中。舉例來說，TIV 472可將重分佈層408耦合到背側重分佈層446。舉例來說，背側重分佈層446可將重分佈層408耦合到一或多個重分佈層452。因此，可形成將重分佈層452耦合到一或多個重分佈層486A和/或重分佈層486B的通孔448。重分佈層468A和/或重分佈層486B可形成於襯墊484A和/或襯墊484B正上方或以其他方式佈置在襯墊484A和/或襯墊484B上。襯墊484A和/或襯墊484B可佈置在包含絕緣材料的絕緣部分482內；因此，襯墊484A和/或襯墊484B中的一或多個可經由導電部分470耦合到oDie 440。
oDie 440可耦合到光學內連線464，所述光學內連線可配置成接收來自光纖460的光和/或將所述光傳送到oDie 440的檢測器部分。因此，開口可存在於封裝件400的光纖陣列接收側。oDie 440可將光轉換成一或多個電信號並將所述一或多個電信號傳輸或以其他方式提供到eDie 436和/或外部連接，例如連接件432A到連接件432C中的一或多個。可通過封裝件400經由重分佈層、一或多個通孔、一或多個TIV、一或多個襯墊484A和/或襯墊484B以及一或多個導電部分470中的一或多個傳輸一或多個電信號。
根據本公開的一些實施例，oDie 440和eDie 436可駐留在封裝件400內。舉例來說，空腔、孔或其他部分可形成或以其他方式存在於基底404中。一或多個oDie 440和/或一或多個eDie 436中的每一個可駐留在例如橫截面圖中的兩側上的TIV之間。此外，基底材料404可包含環氧基或另外為環氧基，使得基底材料可在eDie 436、oDie 440以及一或多個TIV中的一或多個之間。在一些實施例中，oDie 440可直接連接到導電部分470和絕緣部分482中的一或多個或以其他方式佈置在所述導電部分和所述絕緣部分中的一或多個上。
如圖4A到圖4B中進一步描繪，oDie 440可定位於eDie 436與絕緣部分482之間。因此，eDie 436可利用一或多個凸塊490耦合到oDie 440。一或多個通孔488可促進oDie 440與導電部分470和/或eDie 436的連接。根據至少一個實例，eDie 436可經倒裝晶片接合到oDie 440，而封裝件400採用積體電路封裝技術。
圖5A描繪根據本公開的實施例的第五封裝件500的橫截面圖。圖5B描繪圖5A中所描繪的第五封裝件500的放大部分。類似於第一封裝件104、第二封裝件200、第三封裝件300以及第四封裝件400，第五封裝件500可利用積體電路封裝技術。第五封裝件可包含基底504。基底504可包含模具材料、矽材料和/或其他基本上絕緣的或半導體材料。封裝件500可包含形成於基底504頂部上、直接接觸基底504且/或佈置在基底504上的保護層512。保護層512可包含聚醯亞胺和/或聚苯並惡唑材料。保護層512可為在封裝之前用作保護層或「緩衝塗層」或用作重分佈層552的應力消除塗層。在形成保護層512之前，一或多個重分佈層508可形成於基底504頂部上、直接接觸基底504且/或佈置在基底504的至少一部分上。另一保護層516可形成於保護層512和重分佈層552的至少一部分上。在一些實施例中，一或多個通孔518可形成於保護層516和/或保護層512內。在一些情況下，第一通孔可在形成第一保護層512之後形成，而第二通孔可在形成第二保護層516之後形成。或者或另外，第一通孔和/或第二通孔可在已形成保護層512和保護層516之後形成。舉例來說，可移除保護 層516的一或多個部分；例如，可蝕刻、鑽孔所述一或多個部分和/或使其曝露於光，以在保護層512和/或保護層516中形成第一孔。絕緣材料隨後可置於第一孔內以加襯所述孔的側邊。最終，導電材料可置於所述孔中，由此形成一或多個通孔518。
封裝件500可包含一或多個重分佈層520，所述重分佈層形成於保護層516上、形成於保護層516頂部上、直接接觸保護層516或以其他方式佈置在保護層516上。在一實施例中，保護層524可形成於保護層516上、形成於保護層516頂部上、直接接觸保護層516或以其他方式佈置在保護層516上。可移除保護層524的一或多個部分。舉例來說，可將所述一或多個部分蝕刻、鑽孔、曝露於光等，且由此在保護層524中形成孔。隨後，重分佈層520可形成於重分佈層520的一或多個孔內。最後，一或多個凸塊下金屬化層528可形成於重分佈層520上；所述一或多個凸塊下金屬化層528可配置成接收焊球和/或連接件532A到連接件532C，以形成例如球柵陣列。
如先前所論述，封裝件500可包含重分佈層508；重分佈層508可提供經由介接部分576從光學晶粒(oDie)540和/或一或多個eDie 536中的一或多個到連接件532A到連接件532C中的一或多個的信號路徑。連接部分可包含重分佈層586A和/或重分佈層586B中的一或多個、一或多個襯墊584A和襯墊584B、一或多個導電部分570以及一或多個絕緣部分582。絕緣體穿孔(TIV)572可形成於基底504中。舉例來說，TIV 572可將重分佈層508耦合到背側重分佈層546。舉例來說，背側重分佈層546可將重分佈層508耦合到一或多個重分佈層552。因此，可形成將重分佈層552耦合到一或多個重分佈層586A和/或重分佈層586B的通孔548。重分佈層568A和/或重分佈層586B 可形成於襯墊584A和/或襯墊584B正上方或以其他方式佈置在襯墊584A和/或襯墊584B上。襯墊584A和/或襯墊584B可佈置在包含絕緣材料的絕緣部分582內；因此，襯墊584A和/或襯墊584B中的一或多個可將可耦合oDie 540和eDie 536的插入件588耦合到導電部分570。
oDie 540可耦合到光學內連線564，所述光學內連線可配置成接收來自光纖560的光和/或將所述光傳送到oDie 540的檢測器部分。因此，開口可存在於封裝件500的光纖陣列接收側。oDie 540可將光轉換成一或多個電信號並將所述一或多個電信號傳輸或以其他方式提供到eDie 536和/或外部連接，例如連接件532A到連接件532C中的一或多個。可通過封裝件500經由重分佈層、一或多個通孔、一或多個TIV、一或多個襯墊584A和/或襯墊584B以及一或多個導電部分570中的一或多個傳輸一或多個電信號。
根據本公開的一些實施例，oDie 540和eDie 536可連同插入件588駐留在封裝件500內。舉例來說，空腔、孔或其他部分可形成或以其他方式存在於基底504中。一或多個oDie 540、一或多個eDie 536以及插入件588中的每一個可駐留在例如橫截面圖中的兩側上的TIV之間。此外，基底材料504可包含環氧基或另外為環氧基，使得基底材料可在eDie 536、oDie 540以及一或多個TIV中的一或多個之間。在一些實施例中，oDie 540和eDie 536可利用一或多個凸塊590和凸塊592連接到插入件588，而插入件588直接連接到導電部分570和絕緣部分582中的一或多個或以其他方式佈置在所述導電部分和所述絕緣部分中的一或多個上。如圖5A到圖5B中進一步描繪，eDie 588可定位於oDie 540和/或eDie 536與絕緣部分582之間。根據至少一 個實例，eDie 536和/或oDie 540可經倒裝晶片接合到封裝件500中的插入件588，所述封裝件採用積體電路封裝技術。
圖1到圖5B中所示的封裝件的前述實施例中的一或多個可包含於系統或器件中。更確切地說，圖6繪示包含光子封裝件604的系統600。系統600還包含處理子系統608(具有一或多個處理器)和記憶體子系統612(具有記憶體)。
一般來說，系統600可使用硬體和/或軟體的組合實施。因此，系統600可包含存儲於記憶體子系統612(例如DRAM或另一類型的易失性電腦可讀記憶體或非易失性電腦可讀記憶體)中的一或多個程式模組或指令集，所述程式模組或指令集在操作期間可由處理子系統608執行。
系統600可包含：開關、集線器、橋接器、路由器、通訊系統(例如波分複用通訊系統)、存儲區域網路、資料中心、網路(例如區域網路)和/或電腦系統(例如多核心處理器電腦系統)。此外，電腦系統可包含但不限於：伺服器(例如多插口、多機架伺服器)、筆記型電腦、通訊器件或系統、個人電腦、工作站、主機電腦、葉片(blade)、企業電腦、資料中心、平板電腦、超級電腦、網路附接存儲(network-attached-storage；NAS)系統、存儲區域網路(storage-areanetwork；SAN)系統、媒體播放機(例如MP3播放機)、電器設備、子筆記本/上網本、平板電腦、智慧型電話、蜂窩電話、網路設備、機上盒、個人數位助理(personal digital assistant；PDA)、玩具、控制器、數位訊號處理器、遊戲控制台、器件控制器、電器設備內的計算引擎、消費者電子器件、可擕式計算器件或可擕式電子器件、個人助理和/或另一電子器件。
此外，光子封裝件604可以用於廣泛多種應用中，例如：通 訊(例如，用於收發信機、光學內連線或光學鏈路中，例如用於晶圓內通訊或晶圓間通訊)、射頻濾波器、生物感測器、醫學(例如診斷技術或外科手術)、條碼掃描器、計量(例如距離的精確測量)、製造(切割或焊接)、微影製程、資料存儲裝置(例如光學記憶體件或系統)和/或娛樂(雷射展示)。
圖7描繪根據一些實施例的用於形成光子封裝件的第一實例方法的流程圖。在一實施例中，圖7的過程可用於構建圖1到圖5B中繪示的光子封裝件。首先，一或多個oDie 116、eDie 108和/或插入件588在步驟704中接合在一起，使得所得定向導致主動表面向下。舉例來說，一或多個oDie、eDie和/或插入件如圖1到5B中所指示接合在一起。倒裝晶片接合技術可應用於接合一或多個oDie、eDie和/或插入件。使用臨時黏合劑將所得接合晶粒和/或插入件固定到臨時載體晶圓，所述臨時載體晶圓可包含一或多個接續段(connection section)。通過在步驟708中分配模塑化合物來形成中間封裝件以包封oDie、eDie和/或插入件，且可對分配的模塑化合物執行壓縮和固化操作以在步驟712中產生中間封裝件。可在步驟716中對中間封裝件執行反向研磨操作以揭示oDie、eDie和/或插入件的背側。在步驟720中，絕緣體通孔(TIV)形成於中間封裝件中。在步驟724中，重分佈層(redistribution layer；RDL)220形成於通過反向研磨操作而暴露的表面的一或多個部分上，其中RDL有助於將信號從通孔佈線到焊球。在一些實施例中，可形成一或多個襯墊、額外的RDL以及更多保護層。在步驟728中移除臨時載體晶圓，並且翻轉所得中間封裝件以暴露oDie和/或eDie的主動表面。在步驟732中，含有光學波導的一或多個光學連接件可安裝到中間封裝件，以使得光學波導光學耦合到oDie。
圖8A到圖8P說明根據一些實施例的用於製造光子封裝件的示例製造過程。當步驟8A到步驟8P描繪為單獨的步驟時，應理解，一或多個步驟可與另一步驟組合且/或分成多個額外步驟。製造過程可開始於圖8A，其中膜802(例如PBO膜)可施加於載體基底，例如玻璃載體基底804。作為一個實例，可經由光傳遞熱量轉換處理來施加膜802。根據本公開的實施例，膜802施加於玻璃載體基底804的背側，如將從所製造的光子封裝件中顯而易見。在圖8B處，例如Ti/Cu的晶種層可施加於膜804，接著是導電層以及光圖案化和濕式酸蝕刻，以形成重分佈層(RDL)806、RDL 808以及RDL 810。舉例來說，晶種層Ti/CU可為1K/5KA厚，且導電層可為7微米厚。當然，涵蓋了Ti/CU層的其他厚度。在圖8C處，光阻層812可施加於膜802和/或RDL 806、RDL 808以及RDL 810。舉例來說，光阻層812可為180微米到250微米厚。當然，涵蓋了光阻層812的其他厚度。在施加光阻層812之後，一或多個絕緣體穿孔(TIV)814、TIV 816、TIV 818、TIV 820以及TIV 822可產生於光阻層812中。TIV 814、TIV 816、TIV 818、TIV 820以及TIV 822為可能產生的TIV的實例；如位置、定向以及定尺般在本文中涵蓋了更多或更少的TIV。舉例來說，TIV可包含12微米直徑的孔。孔中的每一個可包含或可不包含加襯孔內部的絕緣部分。在一些情況下，絕緣部分僅可加襯孔的一部分。在一些情況下，絕緣部分可能不存在。
在圖8D處，可使用導電材料824填充孔。導電材料824可包含銅或其他導電材料。在一些情況下，可使用例如但不限於Cu-ECP的電化學鍍敷製程來形成導電材料824。在圖8E處，可移除多餘的銅從而暴露光阻層812。舉例來說，可使用化學機械平坦化(Cu-CMP) 製程來移除多餘的銅。當然，涵蓋了其他移除製程。在圖8F處，可剝除光阻層812，留下TIV。此外，晶粒附接膜(die attach film；DAF)828可用以固定光學內連線832、O-Die 830以及E-Die 834。O-Die 830、E-Die 834以及光學內連線832可與先前描述的O-Die、E-Die以及本文中先前所描述的光學內連線相同或類似。在一些情況下，DAF 828可預膠合到已知良好的晶粒且使用取放式單元放置。在一些實例中，DAF 828可利用已知良好的晶粒取放10次。在一些實例中，DAF 828可小於或大於10微米厚。在圖8G處，可施加過度模塑化合物(molding compound；MC)836；MC 836可為50微米厚；在一些實例中，MC 836可小於或大於50微米厚。如圖8H中所描繪，可移除過量的MC 836；例如可經由研磨和/或化學機械平坦化移除多餘的MC 836。
根據實施例，導電材料838可施加於MC 836的表面。在一些實例中，導電材料838可與導電材料824相同或類似。在一些實例中，可利用例如但不限於Cu-ECP的電化學鍍敷製程。導電材料824可電耦合到導電材料824，且在一些情況下電耦合到RDL 806、RDL 808以及RDL 810中的一或多個。如圖8J中所描繪，可移除導電材料838的一或多個部分且保護層840可形成於MC 836的頂部和導電材料838的一或多個部分上。在一些實例中，導電材料838可為7微米厚。在一些實例中，保護層840可為4.5微米厚；在其他實例中，保護層840的厚度可小於或大於4.5微米厚。保護層可與例如但不限於先前所描述的保護層412的保護層相同或類似。在一些實例中，保護層840可包含PBO材料。
如圖8J中所描繪，一些實例可包含RDL 842、RDL 844、RDL 846、RDL 848以及RDL 850。RDL 842、RDL 844、RDL 845、RDL 846、 RDL 848以及RDL 850可包含例如銅的導電材料，且可利用例如但不限於Cu-ECP圖案化製程的製程。如圖8K中所描繪，保護層841可施加於保護層840和RDL 842、RDL 844、RDL 846、RDL 848以及RDL 850的一或多個部分。根據一些實例，可將形成RDL 852、RDL 854以及RDL 856的導電材料圖案化到保護層841上。如圖8L中所描繪，另一保護層858可設置於保護層840和RDL 852、RDL 854以及RDL 856上。保護層858可為PBO層。可利用光掩模和圖案化製程且隨後繼之以例如濕式酸蝕刻的蝕刻製程來施加RDL 852、RDL 854以及RDL 856，。在一些實例中，可經由旋轉塗佈來施加保護層858。圖8M描繪下凸塊安裝件(under bump mount；UBM)860、UBM 862以及UBM 864。可使用光掩模圖案化製程繼之以例如但不限於濕式酸蝕刻的蝕刻製程來施加UBM 860、UBM 862以及UBM 864。隨後可沉積UBM 860、UBM 862以及UBM 864；在一些實例中，UBM 860、UBM 862以及UBM 864可為銅，且可利用Cu-ECP製程進行沉積。如圖8N中所描繪，凸塊866、凸塊868以及凸塊870可形成於對應的UBM 860、UBM 862以及UBM 864的頂部上。
如圖8O中所描繪，可在UV曝光於LTHC之後移除玻璃載體804，其中保護層802充當已組裝封裝件的最終保護層。如圖8P中所描繪，可移除背側區域的部分872以容納光纖陣列874。雖然已利用多個步驟繪示了製造過程，但是這些步驟和/或這些步驟的順序不應被視為具限制性。
在一實施例中，一種集成扇出型(InFO)封裝件提供成一種積體電路封裝件，所述積體電路封裝件可包含：光子晶粒(oDie)，包含至少一個光學元件；電子晶粒(eDie)；以及模塑部分，其中所述模 塑部分包含以通訊方式耦合到oDie和/或eDie中的至少一個的多個重分佈層，且其中所述模塑部分至少部分地包圍oDie和/或eDie中的至少一個。
在一實施例中，一種積體電路封裝件，包括：光子晶粒(oDie)，包含至少一個光學元件；電子晶粒(eDie)；基底，包含多個重分佈層，所述多個重分佈層通訊耦合到所述光子晶粒和/或所述電子晶粒中的至少一個，其中所述基底包括模塑部分，所述模塑部分至少部分地包圍所述光子晶粒和/或所述電子晶粒中的所述至少一個；以及接續段，將所述光子晶粒和/或電子晶粒中的所述至少一個電耦合到至少一個重分佈層，所述至少一個重分佈層定位成鄰近於所述積體電路封裝件的最上層。
在一實施例中，所述光子晶粒光學耦合到至少一個光纖。在一實施例中，所述光子晶粒佈置在所述電子晶粒與所述接續段之間。在一實施例中，所述電子晶粒佈置在所述光子晶粒與所述接續段之間。在一實施例中，所述積體電路封裝件的第一側包含一或多個凸塊下金屬化層，且與所述積體電路封裝件的所述第一側相對的所述積體電路封裝件的第二側包含所述光子晶粒和/或電子晶粒中的所述至少一個的暴露表面。在一實施例中，更包括所述第一側與至少一個封裝穿孔(TIV)之間的至少一個重分佈層，所述封裝穿孔將所述重分佈層耦合到所述接續段。在一實施例中，所述接續段包含一或多個重分佈層和一或多個通孔，所述一或多個重分佈層和所述一或多個通孔將定位於所述積體電路封裝件的所述第一側處的焊料凸塊耦合到所述光子晶粒和/或電子晶粒中的所述一或多個。在一實施例中，所述光子晶粒和/或電子晶粒中的所述至少一個直接耦合到所述接續段。在一實施例中， 更包括佈置在所述光子晶粒和/或所述電子晶粒中的所述至少一個與所述接續段之間的插入件。在一實施例中，所述光子晶粒經由一或多個焊料凸塊耦合到所述電子晶粒。
在一實施例中，一種器件包含電耦合到所述積體電路封裝件的邏輯和/或記憶體元件中的至少一個。
在另一實施例中，提供一種包括光子晶粒(oDie)和電子晶粒(eDie)的封裝件，所述oDie包含至少一個光學元件。封裝件可包含具有第一側和第二側的模塑部分，其中所述模塑部分包含一或多個重分佈層，所述一或多個重分佈層將與模塑部分一起定位於封裝件的第一側處的oDie和/或eDie中的至少一個耦合到定位於封裝件的第二側處的導電部分。
在另一實施例中，一種封裝件包括：光子晶粒(oDie)，包含至少一個光學元件；電子晶粒(eDie)；以及模塑部分，具有第一側和第二側，所述模塑部分包含一或多個重分佈層，所述一或多個重分佈層將定位於所述封裝件的所述第一側處的所述模塑部分中的所述光子晶粒和/或所述電子晶粒中的至少一個耦合到定位於所述封裝件的所述第二側處的導電部分。
在另一實施例中，所述模塑部分至少部分地包圍所述光子晶粒和/或所述電子晶粒中的所述至少一個。在另一實施例中，更包含將所述光子晶粒和/或電子晶粒中的所述至少一個電耦合到至少一個重分佈層的接續段，所述至少一個重分佈層定位成鄰近於所述封裝件的所述第二側。在另一實施例中，所述光子晶粒佈置在所述電子晶粒與所述接續段之間。在另一實施例中，所述電子晶粒佈置在所述光子晶粒與所述接續段之間。在另一實施例中，更包括佈置在所述光子晶粒 和/或所述電子晶粒中的所述至少一個與所述接續段之間的插入件。
在另一實施例中，一種器件包含電耦合到根所述的積體電路封裝件的邏輯和/或記憶體元件中的至少一個。
在一些實施例中，提供一種製作例如積體電路(InFO)封裝件的積體電路封裝件的方法。所述方法可包含：將至少一個光學晶粒(oDie)電耦合到電子晶粒(eDie)；在oDie的一部分和eDie的一部分周圍形成包括模塑部分的中間封裝件；以及移除所述模塑部分的至少一部分。隨後，可在對應於移除部分的模塑部分的位置處形成至少一個重分佈層，且可在至少一個重分佈層上形成至少一個保護層，其中定位於模塑部分與積體電路封裝件的第一側之間的至少一個重分佈層將oDie和/或eDie中的至少一個耦合到定位於積體電路封裝件的第一側處的導電部分。
在一些實施例中，更包括：形成多個封裝通孔，其中所述封裝通孔定位於所述模塑部分的一部分中，以使得所述光子晶粒和/或所述電子晶粒中的所述至少一個定位於橫截面圖中的所述多個封裝通孔中的兩個封裝通孔之間。
前文概述若干實施例的特徵以使得本領域的技術人員可更好地理解本公開的方面。本領域的技術人員應瞭解，其可很容易地將本公開用作設計或修改用於實現本文引入的實施例的相同目的及/或達成相同優勢的其他製程和結構的基礎。本領域的技術人員還應認識到，這類等效構造並不脫離本公開的精神和範圍，且其可在不脫離本公開的精神和範圍的情況下在本文中進行各種改變、替代以及更改。
104:第一封裝件
108:eDie
112:光纖
116:oDie
117:光學內連線
120:重分佈層
124、128:微凸塊
132:凸塊
136:矽穿孔
140:oDie封裝部分
144:第一連接部分
148:矽層
152:第二連接部分
156:保護材料

Claims (10)

  1. 一種積體電路封裝件，包括：獨立的光子晶粒，包含至少一個光學元件；電子晶粒；基底，包含多個重分佈層，所述多個重分佈層電耦合到所述光子晶粒和所述電子晶粒，其中所述基底包括模塑部分，所述模塑部分至少部分地包圍所述光子晶粒和所述電子晶粒中每一個，所述模塑部分包含在所述積體電路封裝件的背側處的開口，所述開口暴露所述光子晶粒的背側；以及接續段，將所述光子晶粒和電子晶粒電耦合到所述多個重分佈層中的至少一個。
  2. 如請求項1所述的積體電路封裝件，其中所述光子晶粒光學耦合到至少一個光纖。
  3. 如請求項1所述的積體電路封裝件，其中所述積體電路封裝件的前側包含一或多個凸塊下金屬化層，且與所述積體電路封裝件的所述前側相對的所述積體電路封裝件的背側包含所述光子晶粒的暴露表面。
  4. 如請求項1所述的積體電路封裝件，更包括：背側重分佈層，在所述模塑部分的所述背側處；以及至少一個絕緣體穿孔，位在所述模塑部分內且將所述多個重分佈層耦合到所述背側重分佈層。
  5. 如請求項1所述的積體電路封裝件，其中所述接續段包括一或多個重分佈層和一或多個襯墊。
  6. 如請求項1所述的積體電路封裝件，其中所述接續段更包括一或多個導電部分和一或多個絕緣部分。
  7. 如請求項1所述的積體電路封裝件，更包括位在所述積體電路封裝件的所述背側處的保護層。
  8. 一種封裝件，包括：光子晶粒，包含至少一個光學元件；電子晶粒；以及模塑部分，具有前側和背側，所述光子晶粒和所述電子晶粒位於所述模塑部分內，所述模塑部分包含在所述模塑部分的所述背側處的開口，所述開口暴露所述光子晶粒的背側；接續段，位元在所述模塑部分內以及所述模塑部分的前側處，所述光子晶粒和所述電子晶粒電耦合到所述接續段；以及一或多個重分佈層，位於所述模塑部分的所述前側處且電耦合到所述接續段。
  9. 一種積體電路封裝件，包括：模塑部分，具有前側和背側；光子晶粒，經組態以光學耦合到光纖，所述光子晶粒位於所述模塑部分內；電子晶粒，位元於所述模塑部分內；接續段，位元在所述模塑部分內以及所述模塑部分的所述前側處，其中所述光子晶粒和所述電子晶粒電耦合到所述接續段；以及一或多個重分佈層，位於所述模塑部分的所述前側處且電耦合到所述接續段，其中所述模塑部分包含在所述模塑部分的所述背側處的開口，所述開口暴露所述光子晶粒的背側。
  10. 一種積體電路封裝件的製作方法，所述方法包括： 將至少一個光學晶粒電耦合到電子晶粒；在所述光子晶粒的一部分和所述電子晶粒的一部分周圍形成模塑部分；移除所述模塑部分的至少一部分；在對應於移除部分的所述模塑部分的位置處形成至少一個重分佈層；以及在所述至少一個重分佈層上形成至少一個保護層，其中定位於所述模塑部分與所述積體電路封裝件的第一側之間的所述至少一個重分佈層將所述光子晶粒和/或所述電子晶粒中的至少一個耦合到定位於所述積體電路封裝件的所述第一側處的導電部分。
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Publication number Priority date Publication date Assignee Title
US11088079B2 (en) * 2019-06-27 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having line connected via portions
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200703496A (en) * 2005-06-01 2007-01-16 Renesas Tech Corp Semiconductor manufacturing method
US20100215317A1 (en) * 2006-05-05 2010-08-26 Reflex Photonics Inc. Optically enabled integrated circuit package
TW201725408A (zh) * 2015-10-21 2017-07-16 樂仕特拉公司 用於基板上晶圓上晶片總成之方法及系統
TW201826483A (zh) * 2017-01-13 2018-07-16 台灣積體電路製造股份有限公司 半導體結構及其製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8831437B2 (en) * 2009-09-04 2014-09-09 Luxtera, Inc. Method and system for a photonic interposer
DE102014219792A1 (de) * 2014-09-30 2016-03-31 Technische Universität Berlin Optoelektronisches Bauelement
WO2017171696A1 (en) * 2016-03-28 2017-10-05 Intel IP Corporation Optical fiber connection on package edge

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200703496A (en) * 2005-06-01 2007-01-16 Renesas Tech Corp Semiconductor manufacturing method
US20100215317A1 (en) * 2006-05-05 2010-08-26 Reflex Photonics Inc. Optically enabled integrated circuit package
TW201725408A (zh) * 2015-10-21 2017-07-16 樂仕特拉公司 用於基板上晶圓上晶片總成之方法及系統
TW201826483A (zh) * 2017-01-13 2018-07-16 台灣積體電路製造股份有限公司 半導體結構及其製造方法

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