WO2022133801A1 - 光电装置以及光电集成结构 - Google Patents

光电装置以及光电集成结构 Download PDF

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Publication number
WO2022133801A1
WO2022133801A1 PCT/CN2020/138618 CN2020138618W WO2022133801A1 WO 2022133801 A1 WO2022133801 A1 WO 2022133801A1 CN 2020138618 W CN2020138618 W CN 2020138618W WO 2022133801 A1 WO2022133801 A1 WO 2022133801A1
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Prior art keywords
substrate
conductive
pic
eic
optoelectronic device
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PCT/CN2020/138618
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English (en)
French (fr)
Inventor
张胜利
汤富生
杨明
王猛
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2020/138618 priority Critical patent/WO2022133801A1/zh
Priority to CN202080100691.6A priority patent/CN115516629A/zh
Publication of WO2022133801A1 publication Critical patent/WO2022133801A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits

Definitions

  • the embodiments of the present application relate to the field of optoelectronic communications, and more particularly, to optoelectronic devices and optoelectronic integrated structures in the field of optoelectronic communications.
  • Photonic integrated packaging technology is an effective way to solve the above challenges.
  • Photonic integrated packaging technology refers to the integration of photonic integrated circuits (PICs) and electronic integrated circuits (EICs) made by different processes. On a common substrate or within a device, it is a package-level integration technology.
  • the optoelectronic package usually packages the PIC and EIC on the substrate by means of 3D stacking. Specifically, a PIC and an application specific integrated circuit (ASIC) are respectively provided on the substrate, and an EIC is provided on the PIC, wherein the EIC is electrically connected to the PIC, and the EIC passes through at least one silicon chip running through the PIC. Through silicon vias (TSVs) and circuit traces of the substrate are electrically connected to the ASIC disposed on the substrate.
  • TSVs silicon vias
  • circuit traces of the substrate are electrically connected to the ASIC disposed on the substrate.
  • the embodiments of the present application provide an optoelectronic device and an optoelectronic integrated structure, which can reduce process complexity and manufacturing cost.
  • an embodiment of the present application provides an optoelectronic device, comprising: a first substrate, an application specific integrated circuit ASIC, a second substrate and a photonic integrated circuit PIC are respectively disposed on a first surface of the first substrate, and the first surface The circuit traces of the first substrate are formed thereon; the electronic integrated circuit EIC is flip-chip stacked on the second substrate and the PIC, the EIC is electrically connected to the PIC; runs through the second surface of the second substrate and the first At least one conductive through hole on the third surface of the second substrate, the EIC is electrically connected to the ASIC provided on the first substrate through the at least one conductive through hole and the circuit trace of the first substrate, wherein the second The surface is the surface of the second substrate away from the first substrate along the thickness direction of the second substrate, and the third surface is the surface of the second substrate close to the first substrate along the thickness direction of the second substrate.
  • the EIC is electrically connected to the ASIC provided on the first substrate through at least one conductive via penetrating the second substrate and the circuit traces of the first substrate, without going through the PIC, thereby avoiding the need for Design and manufacture conductive vias on the PIC.
  • the second substrate is a packaging substrate
  • the process technology for designing and manufacturing conductive vias on the packaging substrate is relatively complete, and the complexity of the process technology and the manufacturing cost are low. Therefore, the optoelectronic device provided by the embodiment of the present application has a Process technology complexity and manufacturing cost are low.
  • the second substrate and the PIC are molded by a molding medium.
  • the at least one conductive via also penetrates the fourth surface of the molding medium and the fifth surface of the molding medium, wherein the fourth surface is the thickness of the molding medium along the second substrate The direction is close to the surface of the EIC, and the fifth surface is the surface of the molding medium close to the first substrate along the thickness direction of the second substrate.
  • the optoelectronic device further includes at least one first conductive metal wire penetrating the fourth surface of the molding medium and the sixth surface of the molding medium, and the sixth surface is the surface of the molding medium along the The thickness direction of the second substrate is located between the fourth surface and the PIC and is in contact with the PIC;
  • the PIC is electrically connected to the first end of the at least one first conductive metal wire, and the second end of the at least one first conductive metal wire is electrically connected to the EIC.
  • the optoelectronic device further includes a first conductive connection member disposed between the PIC and the EIC; the second end of the at least one first conductive metal wire is connected to the first conductive connection member. The first end is electrically connected, and the second end of the first conductive connector is electrically connected to the EIC.
  • the optoelectronic device further includes a second conductive connection member disposed between the EIC and the second substrate; the EIC is electrically connected to the first end of the second conductive connection member, and the first The second ends of the two conductive connectors are electrically connected to the circuit traces of the first substrate through the at least one conductive through hole.
  • the second substrate is a silicon substrate, a glass substrate or a ceramic substrate.
  • the embodiments of the present application further provide another optoelectronic device, comprising: a first substrate, an application-specific integrated circuit ASIC, a second substrate and a photonic integrated circuit PIC are respectively provided on the first surface of the first substrate, the first substrate A circuit trace of the first substrate is formed on a surface; an electronic integrated circuit EIC disposed in the first substrate is embedded, and the EIC passes through the circuit trace of the first substrate and the ASIC provided on the first substrate Electrical connection; at least one conductive through hole passing through the second surface of the second substrate and the third surface of the second substrate, the PIC is electrically connected to the EIC through the at least one conductive through hole, wherein the second surface is The surface of the second substrate away from the first substrate along the thickness direction of the second substrate, and the third surface is the surface of the second substrate close to the first substrate along the thickness direction of the second substrate.
  • the PIC is electrically connected to the EIC through at least one conductive via penetrating the second substrate without going through the PIC, thereby avoiding designing and manufacturing the conductive via on the PIC.
  • the second substrate is a packaging substrate
  • the process technology for designing and manufacturing conductive vias on the packaging substrate is relatively complete, and the complexity of the process technology and the manufacturing cost are low. Therefore, the optoelectronic device provided by the embodiment of the present application is suitable The technological complexity of the process and the manufacturing cost are low.
  • the EIC is embedded in the first substrate, and the EIC is electrically connected to the ASIC through circuit traces on the first substrate, and the signal transmission path is short, which can reduce the parasitic parameters of the signal during the transmission process, And reduce the loss of the signal, therefore, the bandwidth of the signal transmission can be increased, thereby improving the signal transmission performance.
  • the second substrate and the PIC are molded by a molding medium.
  • the at least one conductive via also penetrates the fourth surface of the molding medium and the fifth surface of the molding medium, wherein the fourth surface is the thickness of the molding medium along the second substrate
  • the surface of the fifth surface is the surface of the molding medium close to the first substrate along the thickness direction of the second substrate.
  • the optoelectronic device further includes at least one first conductive metal wire penetrating the fourth surface of the molding medium and the sixth surface of the molding medium, and the sixth surface is the surface of the molding medium along the The thickness direction of the second substrate is located between the fourth surface and the PIC and is in contact with the PIC; the PIC is electrically connected to the first end of the at least one first conductive metal wire, the at least one first conductive metal The second end of the wire is electrically connected to the EIC through the at least one conductive via.
  • the optoelectronic device further includes a first conductive connection member disposed on a seventh surface of the PIC, where the seventh surface is a surface of the PIC away from the first substrate along the thickness direction of the PIC ;
  • the second end of the at least one first conductive metal wire is electrically connected to the first end of the first conductive connection piece, and the second end of the first conductive connection piece is electrically connected to the EIC through the at least one conductive through hole.
  • the second substrate is a silicon substrate, a glass substrate or a ceramic substrate.
  • the embodiments of the present application further provide an optoelectronic integrated structure, comprising:
  • PCB printed circuit board
  • FIG. 1 provides a schematic structural diagram of an existing optoelectronic device 100
  • FIG. 2 provides a schematic structural diagram of an optoelectronic device 200 according to an embodiment of the present application
  • FIG. 3 provides a schematic diagram (top view) of the connection between the ASIC and the first substrate according to the embodiment of the present application;
  • FIG. 4 provides another schematic diagram (cross-sectional view) of the connection between the ASIC and the first substrate according to the embodiment of the present application
  • FIG. 5 provides a schematic structural diagram of an optoelectronic device 500 according to an embodiment of the present application
  • FIG. 6 provides a schematic structural diagram of an optoelectronic device 600 according to an embodiment of the present application.
  • FIG. 7 provides a schematic structural diagram of an optoelectronic device 700 according to an embodiment of the present application.
  • FIG. 8 provides a schematic structural diagram of an optoelectronic device 800 according to an embodiment of the present application.
  • FIG. 9 provides a schematic structural diagram of another optoelectronic device 800 according to an embodiment of the present application.
  • FIG. 10 provides a schematic structural diagram of an optoelectronic device 1000 according to an embodiment of the present application.
  • FIG. 11 provides a schematic structural diagram of an optoelectronic device 1100 according to an embodiment of the present application.
  • 3D stacking technology is to combine chips or structures with different functions through micromachining technology such as stacking technology or via interconnection to form three-dimensional integration, signal connectivity and wafer-level, chip-level, and silicon cap packaging in the Z-axis direction.
  • micromachining technology such as stacking technology or via interconnection to form three-dimensional integration, signal connectivity and wafer-level, chip-level, and silicon cap packaging in the Z-axis direction.
  • Three-dimensional stacking processing technology targeting other packaging and reliability technologies.
  • TSV is the key to 3D chip stacking technology.
  • 3D chips allow multi-layer stacking, while TSV is used to provide vertical communication of multiple wafers.
  • TSV is a method of using vertical through-silicon vias to complete the interconnection between chips. Due to the shorter connection distance and higher strength, it can achieve smaller and thinner packages with better performance, higher density, and significantly reduced size and weight. , and can also be used for interconnection between dissimilar chips.
  • TSV realizes the interconnection between chips by making vertical conduction between chips and between wafers, which can maximize the density of 3D chip stacking, minimize the external size, and greatly improve chip speed and reduce power consumption .
  • Flip-chip bonding refers to depositing tin-lead balls on the input/output (I/O) pads of the chip, and then turning the chip over and heating to use the molten tin-lead balls to combine with the substrate.
  • RDL is a critical part of fan-out packaging.
  • RDL is to deposit metal layers and dielectric layers on the surface of the wafer and form corresponding metal wiring patterns to rearrange the I/O ports of the chip and arrange them to new areas with looser pitch and occupancy.
  • FIG. 1 shows a schematic structural diagram of an existing optoelectronic device 100, and the optoelectronic device 100 adopts the optoelectronic packaging technology based on 3D stacking.
  • the optoelectronic device 100 may include a substrate 101 on which an ASIC 102 and a PIC 103 are respectively disposed.
  • the optoelectronic device 100 also includes an EIC 104 stacked on the PIC 103 and at least one TSV 105 running through the PIC 103 .
  • the PIC 103 is electrically connected to the EIC 104
  • the EIC 104 is electrically connected to the ASIC 102 disposed on the substrate 101 through the at least one TSV 105 and the circuit traces of the substrate 101 .
  • the existing optoelectronic device 100 needs to design and manufacture at least one TSV on the PIC 103 .
  • FIG. 2 shows a schematic structural diagram of the optoelectronic device 200 provided by the embodiment of the present application.
  • the optoelectronic device 200 may include a first substrate 201 , and an ASIC 202 , a second substrate 203 and a PIC 204 are respectively disposed on the first surface of the first substrate 201 .
  • the optoelectronic device 200 also includes an EIC 205 flip-chip stacked on the second substrate 203 and the PIC 204 and at least one conductive via 206 extending through the second surface of the second substrate 203 and the third surface of the second substrate 203 .
  • the EIC 205 is electrically connected to the PIC 204
  • the EIC 205 is electrically connected to the ASIC 202 provided on the first substrate 201 through the at least one conductive via 206 and the circuit traces of the first substrate 201 .
  • the circuit traces of the first substrate 201 are formed on the first surface; the second surface may be the surface of the second substrate 203 away from the first substrate 201 along the thickness direction of the second substrate;
  • the third surface is the surface of the second substrate 203 close to the first substrate 201 along the thickness direction of the second substrate.
  • the first surface may be surface 1 as shown in FIG. 2
  • the second surface may be surface 2 as shown in FIG. 2
  • the third surface may be surface 3 as shown in FIG. 2 .
  • the at least one conductive via 206 may be arranged in various manners, which are not limited in this embodiment of the present application.
  • the at least one conductive via 206 may be arranged in an array of M rows and N columns, where both M and N are integers greater than 0.
  • the at least one conductive via 206 may be arranged in other manners according to actual requirements, which is not limited in this embodiment of the present application.
  • the conductive via 206 may implement conduction in various manners, which is not limited in this embodiment of the present application.
  • the conductive through hole 206 may be filled with conductive metal to form a conductive metal column, and the conductive through hole 206 is electrically conductive through the conductive metal column.
  • the inner wall of the conductive through hole 206 is provided with a conductive metal layer, and the conductive through hole 206 is electrically conductive through the conductive metal layer.
  • a conductive metal wire may be provided in the conductive through hole 206 , and the conductive through hole 206 is electrically conductive through the conductive metal wire.
  • the second substrate 203 may be a substrate made of various packaging materials, which is not limited in this embodiment of the present application.
  • the second substrate 203 may be a silicon substrate, a glass substrate, a ceramic substrate or other organic substrates.
  • the PIC204 may be various types of chips, which are not limited in this embodiment of the present application.
  • the PIC204 can be an active chip, a passive chip or an integrated chip.
  • the PIC 204 may be a chip made of multiple chip materials, which is not limited in this embodiment of the present application.
  • the PIC204 can be a silicon-based chip or a III-V compound-based chip.
  • the chip types and chip materials of the above-mentioned PIC204 may be combined in various ways, which are not limited in this embodiment of the present application.
  • the PIC204 may be a silicon-based active chip, or the PIC204 may be a III-V compound (eg, InP or GaAs)-based integrated chip.
  • the EIC 205 is electrically connected to the ASIC 202 provided on the first substrate 201 through at least one conductive via 206 penetrating the second substrate 203 and circuit traces of the first substrate 201 , Instead of going through the PIC204, designing and fabricating conductive vias on the PIC204 can be avoided.
  • the second substrate 203 belongs to the packaging substrate, and the process technology for designing and manufacturing conductive vias on the packaging substrate is relatively complete, and the complexity of the process technology and the manufacturing cost are low. Some optoelectronic devices 100 have relatively low technological complexity and manufacturing cost.
  • the ASIC 202 , the second substrate 203 and the PIC 204 are respectively disposed on the first surface of the first substrate 201 , which can be understood as: the ASIC 202 , the second substrate 203 and the PIC 204 are respectively mounted on the surface 1 .
  • the ASIC 202 , the second substrate 203 and the PIC 204 may be mounted on the surface 1 in various manners, which are not limited in this embodiment of the present application.
  • circuit traces of the ASIC 202 are formed on the seventh surface of the ASIC 202, and the seventh surface is the surface close to the first substrate 201 along the thickness direction of the ASIC 202; the eighth surface of the PIC 204 is formed with For the circuit traces of the PIC204, the eighth surface is a surface close to the EIC205 along the thickness direction of the PIC204.
  • the seventh surface may be surface 7 as shown in FIG. 2 ; the eighth surface may be surface 8 as shown in FIG. 2 .
  • the ASIC 202 can be flip-chip mounted on the first surface, and the PIC 204 can be front-mounted on the first surface.
  • flip-chip mounting described in the embodiments of the present application may also be referred to as “flip-chip bonding” or “flip-chip packaging”, which is not limited in the embodiments of the present application.
  • the ASIC 202 may be flip-chip mounted on the surface 1 through at least one first solder ball 210 .
  • FIG. 3 top view
  • FIG. 4 cross-sectional view
  • a schematic diagram of the connection between the AIC 202 and the first substrate 201 is shown.
  • the surface 1 of the first substrate 201 is provided with at least A first pad 211
  • at least one second pad 212 is provided on the surface 7 of the ASIC 202
  • at least one first solder ball 210 passes between the at least one first pad 211 and the at least one second pad 212 welded together.
  • the installation method of the second substrate 203 and the PIC 204 on the first substrate 201 may refer to the installation method of the ASIC 202 on the first substrate 201 described in FIG. 3 and FIG. 4 . To avoid repetition, It will not be repeated here.
  • the EIC 205 is flip-chip stacked on the second substrate 203 and the PIC 204, which may include: the EIC 205 is flip-chip mounted on the surface 2 of the second substrate 203; or the EIC 205 is flip-chip mounted on the PIC 204 On the surface 8 of the second substrate 203; or, the EIC 205 is flip-chip mounted on the surface 2 of the second substrate 203 and the surface 8 of the PIC204.
  • circuit traces of the EIC 205 are formed on the ninth surface of the EIC 205 , and the ninth surface is close to the surface of the PIC 204 along the thickness direction of the EIC 205 .
  • the ninth surface may be surface 9 as shown in FIG. 2 .
  • the EIC 205 may be flip-chip stacked on the second substrate 203 and the PIC 204 in various manners, which are not limited in this embodiment of the present application.
  • the EIC 205 may be flip-chip mounted on the second substrate 203 and/or the PIC 204 through at least one second solder ball.
  • the installation method of the EIC 205 on the first substrate 201 may refer to the installation method of the ASIC 202 on the first substrate 201 described in FIG. 3 and FIG. 4 .
  • the EIC 205 may be electrically connected to the PIC 204 in various ways, which are not limited in this embodiment of the present application.
  • the optoelectronic device 200 may further include a first conductive connection member 207 disposed between the PIC 204 and the EIC 205 , and the EIC 205 is connected to the first conductive connection member 207 .
  • the first end is electrically connected, and the second end of the first conductive connector 207 is electrically connected to the PIC 204 .
  • the first conductive connector 207 may be in various forms, which are not limited in this embodiment of the present application.
  • the first conductive connection member 207 may be the first redistribution layer 207 .
  • the first conductive connection member 207 may be at least one second conductive metal wire 207 .
  • the EIC 205 may be electrically connected to the ASIC 202 through the at least one conductive via 206 and the circuit traces of the first substrate 201 in various manners, which are not limited in this embodiment of the present application.
  • the EIC 205 is electrically connected to the first end of the at least one conductive via 206 , and the second end of the at least one conductive via 206 is connected to the ASIC 202 through the circuit traces of the first substrate 201 . electrical connection.
  • the optoelectronic device 200 may further include a second conductive connection member 208 disposed between the EIC 205 and the second substrate 203 , and the EIC 205 is connected to the second conductive connection member 208 .
  • the first end of the connector 208 is electrically connected, and the second end of the second conductive connector 208 is electrically connected to the circuit traces of the first substrate 201 on the surface 1 through the at least one conductive through hole 206 , wherein the first The circuit traces of a substrate 201 are electrically connected to the ASIC 202 .
  • the second conductive connector 208 may be in various forms, which are not limited in this embodiment of the present application.
  • the second conductive connection member 208 may be the second redistribution layer 208 .
  • the second conductive connection member 208 may be at least one third conductive metal wire 208 .
  • the optoelectronic device may further include a third conductive connection member 209 disposed between the second substrate 203 and the first substrate 201 , and the second end of the second conductive connection member 208 is electrically connected through the at least one The hole 206 is electrically connected to the first end of the third conductive connector 209 , and the second end of the third conductive connector 209 is electrically connected to the circuit traces of the first substrate 201 on the surface 1.
  • the third conductive connection member 209 may be in various forms, which are not limited in this embodiment of the present application.
  • the third conductive connection member 209 may be the third redistribution layer 209 .
  • the third conductive connection member 209 may be at least one fourth conductive metal wire 209 .
  • FIG. 2 only schematically shows that the EIC 205 is flip-chip mounted on the surface 2 and the surface 8, but the embodiment of the present application is not limited thereto.
  • FIG. 5 shows a schematic structural diagram of an optoelectronic device 500 provided by an embodiment of the present application.
  • the EIC 505 is flip-chip mounted on the surface 2 of the second substrate 503 , the PIC 504 and the EIC 505 A first conductive connection member 507 is disposed therebetween, the EIC505 is electrically connected to the first end of the first conductive connection member 507, the PIC504 is electrically connected to the second end of the first conductive connection member 507, and the EIC505 passes through the At least one conductive via 506 is electrically connected to the circuit traces of the first substrate 501 on the surface 1, wherein the circuit traces of the first substrate 501 are electrically connected to the ASIC 502 .
  • the first conductive connection member 507 may be at least one second conductive metal wire 507 .
  • FIG. 6 shows a schematic structural diagram of an optoelectronic device 600 provided by an embodiment of the present application.
  • the EIC605 is flip-chip mounted on the surface 8 of the PIC604, between the PIC604 and the EIC605
  • a second conductive connector 608 is provided, the EIC 605 is electrically connected to the PIC 604, and the EIC 605 is electrically connected to the first end of the second conductive connector 608, and the second end of the second conductive connector 608 passes through the at least one
  • the conductive vias 606 are electrically connected to the circuit traces of the first substrate 601 on the surface 1, wherein the circuit traces of the first substrate 601 are electrically connected to the ASIC 602 .
  • the second conductive connection member 608 may be at least one third conductive metal wire 608 .
  • the second substrate and the PIC may be mounted on the first substrate after plastic packaging.
  • FIG. 7 shows a schematic structural diagram of an optoelectronic device 700 provided by an embodiment of the present application.
  • the optoelectronic device 700 may include a first substrate 701 , the first substrate An ASIC 702 , a second substrate 703 and a PIC 704 are respectively disposed on the surface 1 of the 701 , wherein the second substrate 703 and the PIC 704 are encapsulated by a plastic encapsulation medium 710 .
  • the optoelectronic device 700 also includes an EIC 705 flip-chip stacked on the fourth surface of the encapsulation medium 710 and at least one conductive via 706 extending through the fourth and fifth surfaces of the encapsulation medium 710 .
  • the EIC 705 is electrically connected to the PIC 704
  • the EIC 705 is electrically connected to the ASIC 705 provided on the first substrate 701 through the at least one conductive via 706 and the circuit traces of the first substrate 701 .
  • the fourth surface is the surface of the molding medium 710 that is close to the EIC 704 along the thickness direction of the second substrate 703
  • the fifth surface is the surface of the molding medium 710 that is close to the EIC 704 along the thickness direction of the second substrate 703 .
  • the fourth surface may be the surface 4 as shown in FIG. 7 ; the fifth surface may be the surface 5 as shown in FIG. 7 .
  • the optoelectronic device 700 may further include at least one first conductive metal wire 711 penetrating the surface 4 and the sixth surface of the molding medium 710 , the PIC 704 and the at least one first conductive metal wire 711 The first end of the at least one first conductive metal wire 711 is electrically connected to the second end of the EIC 705 .
  • the sixth surface is a surface of the plastic sealing medium located between the fourth surface and the PIC along the thickness direction of the second substrate and in contact with the PIC.
  • the sixth surface may be the surface 6 shown in FIG. 7 .
  • the optoelectronic device 700 may further include a first conductive connection member 707 disposed between the PIC 704 and the EIC 705 , and the second end of the at least one first conductive metal wire 711 is connected to the first conductive connection member 707 .
  • the first end is electrically connected, and the second end of the first conductive connector 707 is electrically connected to the EIC 705 .
  • first conductive connection member 707 For the structure of the first conductive connection member 707, reference may be made to the first conductive connection member 207, which is not repeated here in order to avoid repetition.
  • the EIC 705 may be electrically connected to the ASIC 702 through the at least one conductive via 706 and the circuit traces of the first substrate 701 on the surface 1 in various ways, which are not limited in this embodiment of the present application.
  • the EIC 705 is electrically connected to the first end of the at least one conductive via 706 , and the second end of the at least one conductive via 706 is connected to the ASIC 702 through the circuit traces of the first substrate 701 . electrical connection.
  • the optoelectronic device 700 may further include a second conductive connector 708 disposed between the EIC 705 and the second substrate 703 , the EIC 705 is electrically connected to the first end of the second conductive connector 708 , and the first end of the second conductive connector 708 is electrically connected.
  • the second ends of the two conductive connectors 708 are electrically connected to the first end of the at least one conductive via 706 , and the second end of the at least one conductive via 706 is electrically connected to the ASIC 702 through the circuit traces of the first substrate 701 . .
  • the optoelectronic device 700 may further include a third conductive connector 709 disposed between the second substrate 703 and the first substrate 701 , and the second end of the at least one conductive via 706 is connected to the third conductive connection The first end of the connector 709 is electrically connected, and the second end of the third conductive connector 709 is electrically connected to the ASIC 702 through the circuit traces of the first substrate 701 .
  • the structure of the third conductive connecting member 709 may refer to the above-mentioned third conductive connecting member 209 , which is not repeated here to avoid repetition.
  • an optical waveguide for guiding optical signal transmission may be included in the PIC described in FIGS. 2 to 7 .
  • FIG. 8 shows a schematic structural diagram of an optoelectronic device 800 provided by an embodiment of the present application.
  • the PIC 804 may include an optical waveguide 812 , and the optical waveguides 812 may be arranged in parallel Between surface 8 and surface 10 of the PIC804, and close to this surface 8.
  • the optical interface of the optical waveguide 812 may be set in multiple positions, which is not limited in this embodiment of the present application.
  • the optical interface 813 of the optical waveguide 812 may be arranged on the surface 8.
  • the optical interface 813 of the optical waveguide 812 may be disposed on the end face of the PIC 804 and close to the surface 8.
  • FIG. 7 only schematically shows that the surface 1 of the first substrate 701 is plastic-sealed in the plastic-sealing medium 710 , but the embodiment of the present application is not limited thereto.
  • the area where the orthographic projection of the optical waveguide 812 on the surface 8 is located may be exposed outside the plastic sealing medium 810 .
  • the position of the optical waveguide in the PIC may refer to the description in FIGS. 8 and 9 . To avoid repetition, this It is not repeated here.
  • FIG. 10 shows a schematic structural diagram of an optoelectronic device 1000 provided by an embodiment of the present application.
  • the optoelectronic device 1000 includes a first substrate 1001 , and ASICs 1002 are respectively disposed on the first surface of the first substrate 1001 , the second substrate 1003 and the PIC 1004 .
  • the optoelectronic device 1000 further includes an EIC 1005 embedded in the first substrate 1001 and at least one conductive via 1006 penetrating the second surface of the second substrate 1003 and the third surface of the second substrate 1003 .
  • the EIC 1005 is electrically connected to the ASIC 1002 provided on the first substrate 1001 through circuit traces of the first substrate 1001
  • the PIC 1004 is electrically connected to the EIC 1005 through the at least one conductive via 1006 .
  • the circuit traces of the first substrate 1001 are formed on the first surface; the second surface may be that the second substrate 1003 is far away from the first substrate along the thickness direction of the second substrate 1003 The surface of the substrate 1001 ; the third surface is the surface of the second substrate 1003 that is close to the first substrate 1001 along the thickness direction of the second substrate 1003 .
  • the first surface may be surface 1 as shown in FIG. 10
  • the second surface may be surface 2 as shown in FIG. 10
  • the third surface may be surface 3 as shown in FIG. 10 .
  • the second substrate 1003 may be a substrate made of various packaging materials, which is not limited in this embodiment of the present application.
  • the second substrate 1003 may be a silicon substrate, a glass substrate, a ceramic substrate or other organic substrates.
  • the PIC1004 may be various types of chips, which are not limited in this embodiment of the present application.
  • the PIC1004 can be an active chip, a passive chip or an integrated chip.
  • the PIC1004 may be a chip made of multiple chip materials, which is not limited in this embodiment of the present application.
  • the PIC1004 can be a silicon-based chip or a III-V compound-based chip.
  • the chip types and chip materials of the above-mentioned PIC1004 may be combined in various ways, which are not limited in this embodiment of the present application.
  • the PIC1004 may be a silicon-based active chip, or the PIC1004 may be a III-V compound (eg, InP or GaAs)-based integrated chip.
  • the PIC 1004 is electrically connected to the EIC 1005 through at least one conductive via 1006 penetrating the second substrate 1003 without going through the PIC 1004, thereby avoiding the need to design and manufacture conductive vias on the PIC 1004 .
  • the second substrate 1003 belongs to a packaging substrate, and the process technology for designing and manufacturing conductive vias on the packaging substrate is relatively complete, and the complexity of the process technology and the manufacturing cost are low. Some optoelectronic devices 100 have relatively low technological complexity and manufacturing cost.
  • the EIC 1005 is embedded in the first substrate 1001, and the EIC 1005 is electrically connected to the ASIC 1002 through circuit traces on the first substrate 1001, and the signal transmission path is short, which can reduce signal parasitics during transmission parameters, and reduce the loss of the signal, therefore, the bandwidth of the signal transmission can be increased, thereby improving the signal transmission performance.
  • the ASIC1002, the second substrate 1003 and the PIC1004 are respectively disposed on the first surface of the first substrate 1001, which can be understood as: the ASIC1002, the second substrate 1003 and the PIC1004 are respectively mounted on the surface 1.
  • the installation methods of the ASIC 1002 , the second substrate 1003 and the PIC 1004 on the surface 1 may refer to the corresponding introduction in FIG. 2 , which will not be repeated here to avoid repetition.
  • the ASIC 1002 can be flip-chip mounted on the first surface, and the PIC 1004 can be mounted on the first surface by being mounted on the first surface.
  • the ASIC 1002 can be flip-chip mounted on the first surface
  • the PIC 1004 can be mounted on the first surface by being mounted on the first surface.
  • flip-chip mounting described in the embodiments of the present application may also be referred to as “flip-chip bonding” or “flip-chip packaging”, which is not limited in the embodiments of the present application.
  • the circuit traces of the PIC1004 are formed on the seventh surface of the PIC1004, and the seventh surface is the surface close to the EIC1005 along the thickness direction of the PIC1004; the eighth surface of the ASIC1002 is formed on the There are circuit traces of the ASIC 1002 , and the eighth surface is a surface close to the first substrate 1001 along the thickness direction of the ASIC 1002 .
  • the seventh surface may be surface 7 as shown in FIG. 10 ; the eighth surface may be surface 8 as shown in FIG. 10 .
  • the EIC 1005 is embedded in the first substrate 1001 , the circuit traces of the EIC 1005 are formed on the ninth surface of the EIC 1005 , and the ninth surface is close to the EIC 1005 along the thickness direction of the EIC 1005 . PIC1004 surface, and the ninth surface of the EIC is exposed outside the first substrate 1001 .
  • the ninth surface may be surface 9 as shown in FIG. 10 .
  • the EIC 1005 may be electrically connected to the PIC 1004 in various ways, which are not limited in this embodiment of the present application.
  • the optoelectronic device 1000 may further include a first conductive connection member 1007 disposed on the surface 7 of the PIC 1004 , and the first conductive connection member 1007 between the PIC and the first conductive connection member 1007 One end is electrically connected, the second end of the first conductive connector 1007 is electrically connected to the first end of the at least one conductive via, and the second end of the at least one conductive via is electrically connected to the EIC.
  • first conductive connecting member 1007 for the structure of the first conductive connecting member 1007 , reference may be made to the first conductive connecting member 207 , which is not repeated here in order to avoid repetition.
  • the optoelectronic device 1000 may further include a second conductive connector 1008 disposed between the second substrate 1003 and the EIC 1005 , and the second end of the at least one conductive via 1006 passes through the second conductive connector 1008 is electrically connected to the EIC.
  • the structure of the second conductive connecting member 1008 can be referred to the above-mentioned second conductive connecting member 208 , which is not repeated here in order to avoid repetition.
  • the second substrate 1003 and the PIC 1004 may be mounted on the first substrate after plastic packaging, which is not limited in this embodiment of the present application.
  • FIG. 11 shows a schematic structural diagram of an optoelectronic device 1100 provided by an embodiment of the present application.
  • the optoelectronic device 1100 may include a first substrate 1101 , the first substrate The ASIC1102 , the second substrate 1103 and the PIC1104 are respectively disposed on the surface 1 of the 1101 , wherein the second substrate 1103 and the PIC1104 are encapsulated by the encapsulating medium 1109 .
  • the optoelectronic device 1100 further includes an EIC 1105 embedded in the first substrate 1101 and at least one conductive via 1106 penetrating the fourth surface and the fifth surface of the molding medium 1109 .
  • the EIC 1105 is electrically connected to the ASIC 1102 provided on the first substrate 1101 through circuit traces of the first substrate 1101
  • the PIC 1104 is electrically connected to the EIC 1105 through the at least one conductive via 1106 .
  • the fourth surface is the surface of the molding medium 1109 along the thickness direction of the second substrate 1103 close to the EIC 1104
  • the fifth surface is the thickness of the molding medium 1109 along the second substrate 1103 The direction is close to the surface of the first substrate 1101 .
  • the PIC 1104 may be electrically connected to the EIC 1105 through the at least one conductive via 1106 in various manners, which is not limited in this embodiment of the present application.
  • the optoelectronic device 1100 further includes at least one first conductive metal wire 1110 penetrating the fourth surface of the molding medium 1109 and the sixth surface of the molding medium 1109 , the PIC1104 and the at least one first conductive metal line 1110 .
  • the first end of the first conductive metal wire 1110 is electrically connected
  • the second end of the at least one first conductive metal wire 1110 is electrically connected to the first end of the at least one conductive through hole 1106
  • the second end of the at least one conductive through hole 1106 Two ends are electrically connected to the EIC 1105 , wherein the second end of the at least one conductive via 1106 is close to the first substrate 1101 .
  • the sixth surface is a surface of the molding medium 1109 located between the fourth surface and the PIC 1104 along the thickness direction of the second substrate 1103 and in contact with the PIC 1104 .
  • the sixth surface may be surface 6 as shown in FIG. 11 .
  • the optoelectronic device 1100 further includes a first conductive connection member 1107 disposed on the seventh surface of the PIC1104, and the second end of the at least one first conductive metal wire 1110 is connected to one side of the first conductive connection member 1107 For electrical connection, the other side of the first conductive connector 1107 is electrically connected to the first end of the at least one conductive through hole 1106 .
  • first conductive connection member 1107 can be referred to the above-mentioned first conductive connection member 207 , which is not repeated here to avoid repetition.
  • the seventh surface is a surface of the PIC1104 away from the first substrate 1101 along the thickness direction of the PIC1104.
  • the seventh surface may be the surface 7 as shown in FIG. 11 .
  • the optoelectronic device 1100 may further include a second conductive connector 1108 disposed between the second substrate 1103 and the EIC 1105 , and the second end of the at least one conductive via 1106 is connected to the second conductive connector 1108 One side of the second conductive connector 1108 is electrically connected with the EIC 1105 on the other side.
  • the structure of the second conductive connecting member 1108 may refer to the above-mentioned first conductive connecting member 208 , which is not repeated here in order to avoid repetition.
  • Embodiments of the present application further provide an optoelectronic integrated structure, including a printed circuit board (PCB), on which any optoelectronic device described in FIG. 2 to FIG. 9 is integrated; or FIG. 10 is integrated. or any of the optoelectronic devices described in Figure 11.
  • PCB printed circuit board

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Abstract

本申请实施例提供的光电装置和光电集成结构，能够降低工艺复杂度和制造成本。该光电装置包括：第一基板，该第一基板的第一表面上分别设置有专用集成电路ASIC、第二基板和光子集成电路PIC，该第一表面上形成有该第一基板的电路走线；倒装堆叠在该第二基板和该PIC上的电子集成电路EIC，该EIC与该PIC电连接；贯穿该第二基板的第二表面和该第二基板的第三表面的至少一个导电通孔，该EIC通过该至少一个导电通孔和该第一基板的该电路走线与该第一基板上设置的该ASIC电连接，该第二表面为该第二基板沿该第二基板的厚度方向远离该第一基板的表面，该第三表面为该第二基板沿该第二基板的厚度方向靠近该第一基板的表面。

Description

光电装置以及光电集成结构 技术领域
本申请实施例涉及光电通信领域，并且更具体地，涉及光电通信领域中的光电装置以及光电集成结构。
背景技术
随着数据中心流量的飞速增长，数据中心对高吞吐和大带宽的需求越发迫切，光电互连技术在这样需求下应运而生，如何减少光电器件的尺寸并降低光电器件的功耗成为光电互连技术的主要挑战。光电合封技术是当前解决上述挑战的一种有效途径，光电合封技术是指利用不同的工艺制作的光子集成电路(photonic integrated circuit，PIC)和电子集成电路(electronic integrated circuit，EIC)集成在一个共同基板上或器件内，是一种封装级的集成技术。
光电合封通常通过3D堆叠的方式，将PIC和EIC封装在基板上。具体地，基板上分别设置有PIC和专用集成电路(application specific integrated circuit，ASIC)，该PIC上设置有EIC，其中，该EIC与该PIC电连接，且该EIC通过贯穿该PIC的至少一个硅通孔(through silicon via，TSV)以及该基板的电路走线与设置在该基板上的该ASIC电连接。
然而，由于在PIC上设计和制造TSV的工艺技术复杂度和制造成本较高，因此，采用现有的3D堆叠的方式实现光电合封，工艺技术复杂度和制造成本较高。
发明内容
本申请实施例提供一种光电装置和光电集成结构，能够降低工艺复杂度和制造成本。
第一方面，本申请实施例提供一种光电装置，包括：第一基板，该第一基板的第一表面上分别设置有专用集成电路ASIC、第二基板和光子集成电路PIC，该第一表面上形成有该第一基板的电路走线；倒装堆叠在该第二基板和该PIC上的电子集成电路EIC，该EIC与该PIC电连接；贯穿该第二基板的第二表面和该第二基板的第三表面的至少一个导电通孔，该EIC通过该至少一个导电通孔和该第一基板的该电路走线与该第一基板上设置的该ASIC电连接，其中，该第二表面为该第二基板沿该第二基板的厚度方向远离该第一基板的表面，该第三表面为该第二基板沿该第二基板的厚度方向靠近该第一基板的表面。
本申请实施例提供的光电装置中，EIC通过贯穿第二基板的至少一个导电通孔和第一基板的电路走线与第一基板上设置的ASIC电连接，而无需经由该PIC，从而能够避免在PIC上设计和制造导电通孔。
此外，该第二基板属于封装基板，在封装基板上设计和制造导电通孔的工艺技术已经比较完备，且工艺技术的复杂度且制造成本较低，因此，本申请实施例提供的光电装置的工艺技术复杂度和制造成本较低。
在一种可能的实现方式中，该第二基板和该PIC被塑封介质塑封。
在一种可能的实现方式中，该至少一个导电通孔还贯穿该塑封介质的第四表面和该塑封介质的第五表面，其中，该第四表面为该塑封介质沿该第二基板的厚度方向靠近该EIC的表面，该第五表面为该塑封介质沿该第二基板的厚度方向靠近该第一基板的表面。
在一种可能的实现方式中，该光电装置还包括贯穿该塑封介质的该第四表面和该塑封介质的第六表面的至少一个第一导电金属线，该第六表面为该塑封介质沿该第二基板的厚度方向位于该第四表面与该PIC之间、且与该PIC接触的表面；
该PIC与该至少一个第一导电金属线的第一端电连接，该至少一个第一导电金属线的第二端与该EIC电连接。
在一种可能的实现方式中，该光电装置还包括设置在该PIC和该EIC之间的第一导电连接件；该至少一个第一导电金属线的第二端与该第一导电连接件的第一端电连接，该第一导电连接件的第二端与该EIC电连接。
在一种可能的实现方式中，该光电装置还包括设置在该EIC和该第二基板之间的第二导电连接件；该EIC与该第二导电连接件的第一端电连接，该第二导电连接件的第二端通过该至少一个导电通孔与该第一基板的该电路走线电连接。
在一种可能的实现方式中，该第二基板为硅基板、玻璃基板或陶瓷基板。
第二方面，本申请实施例还提供另一种光电装置，包括：第一基板，该第一基板的第一表面上分别设置有专用集成电路ASIC、第二基板和光子集成电路PIC，该第一表面上形成有该第一基板的电路走线；嵌入设置在该第一基板内的电子集成电路EIC，该EIC通过该第一基板的该电路走线与该第一基板上设置的该ASIC电连接；贯穿该第二基板的第二表面和该第二基板的第三表面的至少一个导电通孔，该PIC通过该至少一个导电通孔与该EIC电连接，其中，该第二表面为该第二基板沿该第二基板的厚度方向远离该第一基板的表面，该第三表面为该第二基板沿该第二基板的厚度方向靠近该第一基板的表面。
本申请实施例提供的光电装置中，PIC通过贯穿第二基板的至少一个导电通孔与EIC电连接，而无需经由PIC，从而能够避免在PIC上设计和制造导电通孔。
另外，该第二基板属于封装基板，在封装基板上设计和制造导电通孔的工艺技术已经比较完备，且工艺技术的复杂度且制造成本较低，因此，本申请实施例提供的光电装置相的工艺技术复杂度和制造成本较低。
此外，该EIC嵌入在该第一基板中，且该EIC通过该第一基板上的电路走线与该ASIC电连接，信号传输的路径较短，这样可以减少信号在传输过程中的寄生参数，并降低信号的损耗，因此，能够提高信号传输的带宽，从而提高信号传输性能。
在一种可能的实现方式中，该第二基板和该PIC被塑封介质塑封。
在一种可能的实现方式中，该至少一个导电通孔还贯穿该塑封介质的第四表面和该塑封介质的第五表面，其中，该第四表面为该塑封介质沿该第二基板的厚度方向远离该EIC的表面，该第五表面为该塑封介质沿该第二基板的厚度方向靠近该第一基板的表面。
在一种可能的实现方式中，该光电装置还包括贯穿该塑封介质的该第四表面和该塑封介质的第六表面的至少一个第一导电金属线，该第六表面为该塑封介质沿该第二基板的厚度方向位于该第四表面与该PIC之间、且与该PIC接触的表面；该PIC与该至少一个第一导电金属线的第一端电连接，该至少一个第一导电金属线的第二端通过该至少一个导电通孔与该EIC电连接。
在一种可能的实现方式中，该光电装置还包括设置在该PIC的第七表面上的第一导电连接件，该第七表面为该PIC沿该PIC的厚度方向远离该第一基板的表面；该至少一个第一导电金属线的第二端与该第一导电连接件的第一端电连接，该第一导电连接件的第二端通过该至少一个导电通孔与该EIC电连接。
在一种可能的实现方式中，该第二基板为硅基板、玻璃基板或陶瓷基板。
第三方面，本申请实施例还提供一种光电集成结构，包括
印刷电路板PCB，该PCB上集成有上述权利要求1至7中任一项该的光电装置或8至13中任一项该的光电装置。
附图说明
图1提供了现有的光电装置100的示意性结构图；
图2提供了本申请实施例的光电装置200的示意性结构图；
图3提供本申请实施例的ASIC和第一基板的连接示意图(俯视图)；
图4提供本申请实施例的ASIC和第一基板的另一连接示意图(剖视图)；
图5提供了本申请实施例的光电装置500的示意性结构图；
图6提供了本申请实施例的光电装置600的示意性结构图；
图7提供了本申请实施例的光电装置700的示意性结构图；
图8提供了本申请实施例的光电装置800的示意性结构图；
图9提供了本申请实施例的另一光电装置800的示意性结构图；
图10提供了本申请实施例的光电装置1000的示意性结构图；
图11提供了本申请实施例的光电装置1100的示意性结构图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
首先对本申请实施例中涉及以下专业术语做介绍。
1、三维(three dimensional，3D)堆叠
3D堆叠技术是把不同功能的芯片或结构，通过堆叠技术或过孔互连等微机械加工技术，使其在Z轴方向上形成立体集成、信号连通及圆片级、芯片级、硅帽封装等封装和可靠性技术为目标的三维立体堆叠加工技术。
2、硅通孔(through silicon via，TSV)
TSV是3D芯片堆叠技术的关键三维芯片允许多层堆叠，而过TSV用来提供多个晶片垂直方向的通信。其中，TSV是利用垂直硅通孔完成芯片间互连的方法，由于连接距离更短、强度更高，它能实现更小更薄且性能更好、密度更高、尺寸和重量明显减少的封装，同时还能用于异种芯片之间的互连。TSV通过在芯片与芯片之间、晶圆与晶圆之间制作垂直导通，实现芯片之间互连，能够使3D芯片堆叠的密度最大，外形尺寸最小，并且大大改善芯片速度和降低功耗。
3、倒装焊接(flip chip，FC)
倒装焊接是指在芯片的输出/输出(input/output，I/O)焊盘(pad)上沉积锡铅球，然后将芯片翻转加热利用熔融的锡铅球与基板相结合。
4、重布线层(Redistribution Layer，RDL)
RDL是扇出型封装的关键部分。RDL是在晶圆表面沉积金属层和介质层并形成相应的金属布线图形，来对芯片的I/O端口进行重新布局，将其布置到新的、节距占位可更为宽松的区域。
图1示出了现有的光电装置100的示意性结构图，该光电装置100采用基于3D堆叠的光电合封技术。如图1所示，该光电装置100可以包括基板101，该基板101上分别设置有ASIC102和PIC103。该光电装置100还包括堆叠设置在所述PIC103上的EIC104以及贯穿该PIC103的至少一个TSV105。其中，该PIC103与该EIC104电连接，且该EIC104通过该至少一个TSV105以及该基板101的电路走线与设置在该基板101上的ASIC102电连接。
也就是说，现有的光电装置100需要在该PIC103上设计和制造至少一个TSV。
然而，由于在PIC上设计和制造TSV的工艺技术较复杂且制造成本较高，此外，业界针对PIC上的TSV制造技术的开发尚未成熟。因此，现有的光电装置100的工艺技术较复杂且制造成本较高。
针对上述现有的光电装置100所存在的问题，图2示出了本申请实施例提供的光电装置200的示意性结构图。
如图2所示，该光电装置200可以包括第一基板201，该第一基板201的第一表面上分别设置有ASIC202、第二基板203和PIC204。
该光电装置200还包括倒装堆叠在该第二基板203和该PIC204上的EIC205以及贯穿该第二基板203的第二表面和该第二基板203的第三表面的至少一个导电通孔206。该EIC205与该PIC204电连接，且该EIC205通过该至少一个导电通孔206和该第一基板201的电路走线与该第一基板201上设置的该ASIC202电连接。
需要说明的是，该第一表面上形成有该第一基板201的电路走线；该第二表面可以为该第二基板203沿该第二基板的厚度方向远离该第一基板201的表面；该第三表面为该第二基板203沿该第二基板的厚度方向靠近该第一基板201的表面。
例如：该第一表面可以为如图2中所示的表面①，该第二表面可以为如图2中所示的表面②，该第三表面可以为如图2中所示的表面③。
需要说明的是，图2中仅示意性示出一个导电通孔206，但本申请实施例不限于此。
可选地，该至少一个导电通孔206可以按照多种方式进行排布，本申请实施例对此不作限定。
在一种可能的实现方式中，该至少一个导电通孔206可以按照M行N列的阵列进行排布，其中，M和N均为大于0的整数。
可选地，该至少一个导电通孔206可以根据实际需求，按照其他方式进行排布，本申请实施例对此不作限定。
可选地，该导电通孔206可以通过多种方式实现导电，本申请实施例对此不作限定。
在一种可能的实现方式中，如图2所示，该导电通孔206中可以填充有导电金属，形成导电金属柱，该导电通孔206通过该导电金属柱实现导电。
在另一种可能的实现方式中，该导电通孔206的内壁设置有导电金属层，该导电通孔206通过该导电金属层实现导电。
在又一种可能的实现方式中，该导电通孔206中可以设置有导电金属线，该导电通孔206通过该导电金属线实现导电。
可选地，该第二基板203可以为由多种封装材料制成的基板，本申请实施例对此不作限定。
例如：该第二基板203可以为硅基板、玻璃基板、陶瓷基板或其他有机基板。
可选地，该PIC204可以为多种类型的芯片，本申请实施例对此不作限定。
例如：该PIC204可以为有源芯片、无源芯片或集成芯片。
可选地，该PIC204可以为由多种芯片材料制成的芯片，本申请实施例对此不作限定。
例如：该PIC204可以为硅基芯片或三五族化合物基芯片。
需要说明的是，上述PIC204的芯片类型和芯片材料可以进行多种组合，本申请实施例对此不做限定。例如：该PIC204可以为硅基有源芯片，或者，该PIC204可以为三五族化合物(如InP或GaAs)基集成芯片。
本申请实施例提供的光电装置200，该EIC205通过贯穿该第二基板203的至少一个导电通孔206和该第一基板201的电路走线与该第一基板201上设置的该ASIC202电连接，而无需经由该PIC204，从而能够避免在PIC204上设计和制造导电通孔。
此外，该第二基板203属于封装基板，在封装基板上设计和制造导电通孔的工艺技术已经比较完备，且工艺技术的复杂度且制造成本较低，因此，该光电装置200相比于现有的光电装置100的工艺技术复杂度和制造成本较低。
可选地，该第一基板201的第一表面上分别设置有ASIC202、第二基板203和PIC204，可以理解为：该ASIC202、该第二基板203和该PIC204分别安装在该表面①上。
可选地，该ASIC202、该第二基板203和该PIC204可以通过多种方式安装在表面①上，本申请实施例对此不作限定。
需要说明的是，该ASIC202的第七表面上形成有该ASIC202的电路走线，该第七表面为沿该ASIC202的厚度方向靠近该第一基板201的表面；该PIC204的第八表面上形成有该PIC204的电路走线，该第八表面为沿该PIC204的厚度方向靠近该EIC205的表面。
例如：该第七表面可以为如图2中所示的表面⑦；该第八表面可以为如图2中所示的表面⑧。
也就是说，该ASIC202可以倒装安装在该第一表面上，该PIC204可以正装安装在该第一表面上。
需要说明的是，本申请实施例中所述的“倒装安装”也可以称为“倒装焊接”或“倒装封装”，本申请实施例对此不作限定。
在一种可能的实现方式中，如图2所示，该ASIC202可以通过至少一个第一焊球210倒装安装在该表面①上。
例如：如图3(俯视图)和图4(剖视图)示出了该AIC202和该第一基板201的连接示意图，如图3和图4所示，该第一基板201的表面①上设置有至少一个第一焊盘211，该ASIC202的表面⑦上设置有至少一个第二焊盘212，该至少一个第一焊盘211与该至少一个第二焊盘212之间通过至少一个第一焊球210焊接在一起。
需要说明的是，图3和图4中仅以4个第一焊盘211、4个第一焊球210和4个第二焊球212为例进行介绍，本申请实施例对焊盘和焊球的数量不作限定。
需要说明的是，该第二基板203和该PIC204在该第一基板201上的安装方式可以参考图3和图4中所述的ASIC202在该第一基板201上的安装方式，为避免重复，此处不再赘述。
可选地，该EIC205倒装堆叠在该第二基板203和该PIC204上，可以包括：该EIC205倒装安装在该第二基板203的该表面②上；或者，该EIC205倒装安装在该PIC204的该表面⑧上；或者，该EIC205倒装安装在该第二基板203的该表面②和该PIC204的该表面⑧上。
需要说明的是，该EIC205的第九表面上形成有该EIC205的电路走线，该第九表面为沿该EIC205的厚度方向靠近该PIC204表面。
例如：该第九表面可以为如图2中所示的表面⑨。
可选地，该EIC205可以通过多种方式倒装堆叠在该第二基板203和该PIC204上，本申请实施例对此不作限定。
在一种可能的方式中，该EIC205可以通过至少一个第二焊球倒装安装在该第二基板203和/或该PIC204上。
需要说明的是，该EIC205在该第一基板201上的安装方式可以参考图3和图4中所述的ASIC202在该第一基板201上的安装方式，为避免重复，此处不再赘述。
可选地，该EIC205可以通过多种方式与该PIC204电连接，本申请实施例对此不作限定。
在一种可能的实现方式中，如图2所示，该光电装置200还可以包括设置在该PIC204和该EIC205之间的第一导电连接件207，该EIC205与该第一导电连接件207的第一端电连接，该第一导电连接件207的第二端与该PIC204电连接。
可选地，该第一导电连接件207可以为多种形态，本申请实施例对此不作限定。
在一种可能的实现方式中，该第一导电连接件207可以为第一重布线层207。
在另一种可能的实现方式中，该第一导电连接件207可以为至少一个第二导电金属线207。
可选地，该EIC205可以通过多种方式，通过该至少一个导电通孔206和该第一基板201的电路走线与该ASIC202电连接，本申请实施例对此不作限定。
在一种可能的实现方式中，该EIC205与该至少一个导电通孔206的第一端电连接，该至少一个导电通孔206的第二端通过该第一基板201的电路走线与该ASIC202电连接。
在另一种可能的实现方式中，如图2所示，该光电装置200还可以包括设置在该EIC205和该第二基板203之间的第二导电连接件208，该EIC205与该第二导电连接件208的第一端电连接，该第二导电连接件208的第二端通过该至少一个导电通孔206与该表面①上该第一基板201的电路走线电连接，其中，该第一基板201的电路走线与该ASIC202电连接。
可选地，该第二导电连接件208可以为多种形态，本申请实施例对此不作限定。
在一种可能的实现方式中，该第二导电连接件208可以为第二重布线层208。
在另一种可能的实现方式中，该第二导电连接件208可以为至少一个第三导电金属线208。
可选地，该光电装置还可以包括设置在该第二基板203和该第一基板201之间的第三 导电连接件209，该第二导电连接件208的第二端通过该至少一个导电通孔206与该第三导电连接件209的第一端电连接，该第三导电连接件209的第二端与该表面①上该第一基板201的电路走线电连接。
可选地，该第三导电连接件209可以为多种形态，本申请实施例对此不作限定。
在一种可能的实现方式中，该第三导电连接件209可以为第三重布线层209。
在另一种可能的实现方式中，该第三导电连接件209可以为至少一个第四导电金属线209。
需要说明的是，图2中仅示意性示出该EIC205倒装安装在该表面②和该表面⑧上，但本申请实施例不限于此。
例如：图5示出了本申请实施例提供的光电装置500的示意性结构图，如图5所示，该EIC505倒装安装在该第二基板503的该表面②上，该PIC504和该EIC505之间设置有第一导电连接件507，该EIC505与该第一导电连接件507的第一端电连接，该PIC504与该第一导电连接件507的第二端电连接，且该EIC505通过该至少一个导电通孔506和该表面①上该第一基板501的电路走线电连接，其中，该第一基板501的电路走线与该ASIC502电连接。
在一种可能的实现方式中，该第一导电连接件507可以为至少一个第二导电金属线507。
又如：图6示出了本申请实施例提供的光电装置600的示意性结构图，如图6所示，该EIC605倒装安装在该PIC604的该表面⑧上，该PIC604和该EIC605之间设置有第二导电连接件608，该EIC605与该PIC604电连接，且该EIC605与该第二导电连接件608的第一端电连接，该第二导电连接件608的第二端通过该至少一个导电通孔606与该表面①上该第一基板601的电路走线电连接，其中，该第一基板601的电路走线与该ASIC602电连接。
在一种可能的实现方式中，该第二导电连接件608可以为至少一个第三导电金属线608。
需要说明的是，图5和图6中未涉及的部分的结构可以参考图2至图4中的相关部分的介绍，为避免重复，此处不再赘述。
需要说明的是，图2至图6中仅以该第二基板和该PIC独立安装在该第一基板上为例进行介绍。
可选地，该第二基板和该PIC可以塑封后安装在该第一基板上。
在一种可能的实现方式中，图7示出了本申请实施例提供的光电装置700的示意性结构图，如图7所示，该光电装置700可以包括第一基板701，该第一基板701的表面①上分别设置有ASIC702、第二基板703和PIC704，其中，该第二基板703和该PIC704被塑封介质710塑封。
该光电装置700还包括倒装堆叠在该塑封介质710的第四表面上的EIC705以及贯穿塑封介质710的第四表面和第五表面的至少一个导电通孔706。该EIC705与该PIC704电连接，且该EIC705通过该至少一个导电通孔706和该第一基板701的电路走线与该第一基板701上设置的该ASIC705电连接。
需要说明的是，该第四表面为该塑封介质710沿该第二基板703的厚度方向靠近该 EIC704的表面，该第五表面为该塑封介质710沿该第二基板703的厚度方向靠近该第一基板701的表面。
例如：该第四表面可以为如图7中所示的表面④；该第五表面可以为如图7中所示的表面⑤。
需要说明的是，图7中未涉及的部分可以参考图2至图4中的相关部分的介绍，为避免重复，此处不再赘述。
在一种可能的实现方式中，该光电装置700还可以包括贯穿该塑封介质710的表面④和第六表面的至少一个第一导电金属线711，该PIC704与该至少一个第一导电金属线711的第一端电连接，该至少一个第一导电金属线711的第二端与该EIC705电连接。
需要说明的是，该第六表面为该塑封介质沿该第二基板的厚度方向位于该第四表面与该PIC之间、且与该PIC接触的表面。
例如：该第六表面可以为如图7中所示的表面⑥。
进一步地，该光电装置700还可以包括设置在该PIC704和该EIC705之间的第一导电连接件707，该至少一个第一导电金属线711的该第二端与该第一导电连接件707的第一端电连接，该第一导电连接件707的第二端与该EIC705电连接。
需要说明的是，该第一导电连接件707的结构可以参考上述第一导电连接件207，为避免重复，此处不再赘述。
可选地，该EIC705可以通过多种方式，通过该至少一个导电通孔706和该表面①上该第一基板701的电路走线与该ASIC702电连接，本申请实施例对此不作限定。
在一种可能的实现方式中，该EIC705与该至少一个导电通孔706的第一端电连接，该至少一个导电通孔706的第二端通过该第一基板701的电路走线与该ASIC702电连接。
可选地，该光电装置700还可以包括设置在该EIC705和该第二基板703之间的第二导电连接件708，该EIC705与该第二导电连接件708的第一端电连接，该第二导电连接件708的第二端与该至少一个导电通孔706的第一端电连接，该至少一个导电通孔706的第二端通过该第一基板701的电路走线与该ASIC702电连接。
需要说明的是，该第二导电连接件708的结构可以参考上述第二导电连接件208，为避免重复，此处不再赘述。
可选地，该光电装置700还可以包括设置在该第二基板703和该第一基板701之间的第三导电连接件709，该至少一个导电通孔706的第二端与该第三导电连接件709的第一端电连接，该第三导电连接件709的第二端通过该第一基板701的电路走线与该ASIC702电连接。
需要说明的是，该第三导电连接件709的结构可以参考上述第三导电连接件209，为避免重复，此处不再赘述。
可选地，图2至图7中所述的PIC中可以包括用于引导光信号传输的光波导。
在一种可能的实现方式中，图8示出了本申请实施例提供的光电装置800的示意性结构图，如图8所示，该PIC804可以包括光波导812，该光波导812可以平行设置在所述PIC804的表面⑧和表面⑩之间，且靠近该表面⑧。
可选地，该光波导812的光接口可以设置在多个位置，本申请实施例对此不作限定。
在一种可能的实现方式中，如图8所示，该光波导812的光接口813可以设置在该表 面⑧上。
在另一种可能的实现方式中，如图9所示，该光波导812的光接口813可以设置在该PIC804的端面，且靠近该表面⑧。
需要说明的是，图7中仅示意性示出该第一基板701的表面①塑封在该塑封介质710内，但本申请实施例不限于此。
可选地，如图8和图9所示，该表面⑧上该光波导812的正投影所在区域可以裸露在该塑封介质810外。
可选地，图2至图7中该第二基板和该PIC单独设置在该第一基板上时，该PIC中光波导的位置可以参考图8和图9中的介绍，为避免重复，此处不再赘述。
图10示出了本申请实施例提供的光电装置1000的示意性结构图，如图10所示，该光电装置1000包括第一基板1001，该第一基板1001的第一表面上分别设置有ASIC1002、第二基板1003和PIC1004。
该光电装置1000还包括嵌入设置在该第一基板1001内的EIC1005以及贯穿该第二基板1003的第二表面和该第二基板1003的第三表面的至少一个导电通孔1006。该EIC1005通过该第一基板1001的电路走线与该第一基板1001上设置的该ASIC1002电连接，且该PIC1004通过该至少一个导电通孔1006与该EIC1005电连接。
在一种可能的实现方式中，该第一表面上形成有该第一基板1001的电路走线；该第二表面可以为该第二基板1003沿该第二基板1003的厚度方向远离该第一基板1001的表面；该第三表面为该第二基板1003沿该第二基板1003的厚度方向靠近该第一基板1001的表面。
例如：该第一表面可以为如图10中所示的表面①，该第二表面可以为如图10中所示的表面②，该第三表面可以为如图10中所示的表面③。
可选地，该第二基板1003可以为由多种封装材料制成的基板，本申请实施例对此不作限定。
例如：该第二基板1003可以为硅基板、玻璃基板、陶瓷基板或其他有机基板。
可选地，该PIC1004可以为多种类型的芯片，本申请实施例对此不作限定。
例如：该PIC1004可以为有源芯片、无源芯片或集成芯片。
可选地，该PIC1004可以为由多种芯片材料制成的芯片，本申请实施例对此不作限定。
例如：该PIC1004可以为硅基芯片或三五族化合物基芯片。
需要说明的是，上述PIC1004的芯片类型和芯片材料可以进行多种组合，本申请实施例对此不做限定。例如：该PIC1004可以为硅基有源芯片，或者，该PIC1004可以为三五族化合物(如InP或GaAs)基集成芯片。
本申请实施例提供的光电装置1000，该PIC1004通过贯穿该第二基板1003的至少一个导电通孔1006与该EIC1005电连接，而无需经由该PIC1004，从而能够避免在PIC1004上设计和制造导电通孔。
另外，该第二基板1003属于封装基板，在封装基板上设计和制造导电通孔的工艺技术已经比较完备，且工艺技术的复杂度且制造成本较低，因此，该光电装置1000相比于现有的光电装置100的工艺技术复杂度和制造成本较低。
此外，该EIC1005嵌入在该第一基板1001中，且该EIC1005通过该第一基板1001 上的电路走线与该ASIC1002电连接，信号传输的路径较短，这样可以减少信号在传输过程中的寄生参数，并降低信号的损耗，因此，能够提高信号传输的带宽，从而提高信号传输性能。
可选地，该第一基板1001的第一表面上分别设置有ASIC1002、第二基板1003和PIC1004，可以理解为：该ASIC1002、该第二基板1003和该PIC1004分别安装在该表面①上。
需要说明的是，该ASIC1002、该第二基板1003和该PIC1004在表面①上的安装方式可以参考图2中的相应介绍，为避免重复，此处不再赘述。
在一种可能的实现方式中，该ASIC1002可以倒装安装在该第一表面上，该PIC1004可以正装安装在该第一表面上，具体可以参考图2中的相应介绍，此处不再赘述。
需要说明的是，本申请实施例中所述的“倒装安装”也可以称为“倒装焊接”或“倒装封装”，本申请实施例对此不作限定。
在一种可能的实现方式中，该PIC1004的第七表面上形成有该PIC1004的电路走线，该第七表面为沿该PIC1004的厚度方向靠近该EIC1005的表面；该ASIC1002的第八表面上形成有该ASIC1002的电路走线，该第八表面为沿该ASIC1002的厚度方向靠近该第一基板1001的表面。
例如：该第七表面可以为如图10中所示的表面⑦；该第八表面可以为如图10中所示的表面⑧。
在一种可能的实现方式中，该EIC1005嵌入设置在该第一基板1001内，该EIC1005的第九表面上形成有该EIC1005的电路走线，该第九表面为沿该EIC1005的厚度方向靠近该PIC1004表面，且该EIC的第九表面裸露在该第一基板1001外。
例如：该第九表面可以为如图10中所示的表面⑨。
可选地，该EIC1005可以通过多种方式与该PIC1004电连接，本申请实施例对此不作限定。
在一种可能的实现方式中，如图10所示，该光电装置1000还可以包括设置在该PIC1004的表面⑦上的第一导电连接件1007，该PIC与该第一导电连接件1007的第一端电连接，该第一导电连接件1007的第二端与该至少一个导电通孔的第一端电连接，该至少一个导电通孔的第二端与该EIC电连接。
需要说明的是，该第一导电连接件1007的结构可以参考上述第一导电连接件207，为避免重复，此处不再赘述。
可选地，该光电装置1000还可以包括设置在该第二基板1003和该EIC1005之间的第二导电连接件1008，该至少一个导电通孔1006的第二端通过该第二导电连接件1008与该EIC电连接。
需要说明的是，该第二导电连接件1008的结构可以参考上述第二导电连接件208，为避免重复，此处不再赘述。
可选地，图10中未涉及的部分可以参考图2至图6中的相关部分的介绍，为避免重复，此处不再赘述。
需要说明的是，图10中仅示意性以该第二基板1003和该PIC1004独立安装在该第一基板1001上为例进行介绍，但本申请实施例不限于此。
可选地，该第二基板1003和该PIC1004可以塑封后安装在该第一基板上，本申请实施例对此不作限定。
在一种可能的实现方式中，图11示出了本申请实施例提供的光电装置1100的示意性结构图，如图11所示，该光电装置1100可以包括第一基板1101，该第一基板1101的表面①上分别设置有ASIC1102、第二基板1103和PIC1104，其中，该第二基板1103和该PIC1104被塑封介质1109塑封。
该光电装置1100还包括嵌入设置在该第一基板1101内的EIC1105以及贯穿该塑封介质1109的第四表面和第五表面的至少一个导电通孔1106。该EIC1105通过该第一基板1101的电路走线与该第一基板1101上设置的该ASIC1102电连接，且该PIC1104通过该至少一个导电通孔1106与该EIC1105电连接。
在一种可能的实现方式中，该第四表面为该塑封介质1109沿该第二基板1103的厚度方向靠近该EIC1104的表面，该第五表面为该塑封介质1109沿该第二基板1103的厚度方向靠近该第一基板1101的表面。
例如：该第四表面可以为如图11中所示的表面④；该第五表面可以为如图11中所示的表面⑤。
需要说明的是，图11中未涉及的部分可以参考图10中的相关部分的介绍，为避免重复，此处不再赘述。
可选地，该PIC1104可以通过多种方式，通过该至少一个导电通孔1106与该EIC1105电连接，本申请实施例对此不作限定。
在一种可能的实现方式中，该光电装置1100还包括贯穿该塑封介质1109的该第四表面和该塑封介质1109的第六表面的至少一个第一导电金属线1110，该PIC1104与该至少一个第一导电金属线1110的第一端电连接，该至少一个第一导电金属线1110的第二端与该至少一个导电通孔1106的第一端电连接，该至少一个导电通孔1106的第二端与该EIC1105电连接，其中，该至少一个导电通孔1106的该第二端靠近该第一基板1101。
在一种可能的实现方式中，该第六表面为该塑封介质1109沿该第二基板1103的厚度方向位于该第四表面与该PIC1104之间、且与该PIC1104接触的表面。
例如：该第六表面可以为如图11中所示的表面⑥。
进一步地，该光电装置1100还包括设置在该PIC1104的第七表面上的第一导电连接件1107，该至少一个第一导电金属线1110的第二端与该第一导电连接件1107的一侧电连接，该第一导电连接件1107的另一侧与该至少一个导电通孔1106的第一端电连接。
需要说明的是，该第一导电连接件1107的结构可以参考上述第一导电连接件207，为避免重复，此处不再赘述。
在一种可能的实现方式中，该第七表面为该PIC1104沿该PIC1104的厚度方向远离该第一基板1101的表面。
例如：该第七表面可以为如图11中所示的表面⑦。
可选地，该光电装置1100还可以包括设置在该第二基板1103和该EIC1105之间的第二导电连接件1108，该至少一个导电通孔1106的第二端与该第二导电连接件1108的一侧电连接，该第二导电连接件1108的另一侧与该EIC1105电连接。
需要说明的是，该第二导电连接件1108的结构可以参考上述第一导电连接件208， 为避免重复，此处不再赘述。
可选地，该PIC1104中的光波导的位置以及该光波导的光口的位置可以参考图8和图9中的相应介绍，为避免重复，此处不再赘述。
本申请实施例还提供一种光电集成结构，包括印刷电路板(printed circuit board，PCB)，该PCB上集成有上述图2至图9中所述的任一光电装置；或集成有上述图10或图11中所述的任一光电装置。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应所述以权利要求的保护范围为准。

Claims (14)

  1. 一种光电装置，其特征在于，包括：
    第一基板，所述第一基板的第一表面上分别设置有专用集成电路ASIC、第二基板和光子集成电路PIC，所述第一表面上形成有所述第一基板的电路走线；
    倒装堆叠在所述第二基板和所述PIC上的电子集成电路EIC，所述EIC与所述PIC电连接；
    贯穿所述第二基板的第二表面和所述第二基板的第三表面的至少一个导电通孔，所述EIC通过所述至少一个导电通孔和所述第一基板的所述电路走线与所述第一基板上设置的所述ASIC电连接，其中，所述第二表面为所述第二基板沿所述第二基板的厚度方向远离所述第一基板的表面，所述第三表面为所述第二基板沿所述第二基板的厚度方向靠近所述第一基板的表面。
  2. 根据权利要求1所述的光电装置，其特征在于，
    所述第二基板和所述PIC被塑封介质塑封。
  3. 根据权利要求2所述的光电装置，其特征在于，
    所述至少一个导电通孔还贯穿所述塑封介质的第四表面和所述塑封介质的第五表面，其中，所述第四表面为所述塑封介质沿所述第二基板的厚度方向靠近所述EIC的表面，所述第五表面为所述塑封介质沿所述第二基板的厚度方向靠近所述第一基板的表面。
  4. 根据权利要求3所述的光电装置，其特征在于，所述光电装置还包括贯穿所述塑封介质的所述第四表面和所述塑封介质的第六表面的至少一个第一导电金属线，所述第六表面为所述塑封介质沿所述第二基板的厚度方向位于所述第四表面与所述PIC之间、且与所述PIC接触的表面；
    所述PIC与所述至少一个第一导电金属线的第一端电连接，所述至少一个第一导电金属线的第二端与所述EIC电连接。
  5. 根据权利要求4所述的光电装置，其特征在于，所述光电装置还包括设置在所述PIC和所述EIC之间的第一导电连接件；
    所述至少一个第一导电金属线的第二端与所述第一导电连接件的第一端电连接，所述第一导电连接件的第二端与所述EIC电连接。
  6. 根据权利要求1至5中任一项所述的光电装置，其特征在于，所述光电装置还包括设置在所述EIC和所述第二基板之间的第二导电连接件；
    所述EIC与所述第二导电连接件的第一端电连接，所述第二导电连接件的第二端通过所述至少一个导电通孔与所述第一基板的所述电路走线电连接。
  7. 根据权利要求1至6中任一项所述的光电装置，其特征在于，
    所述第二基板为硅基板、玻璃基板或陶瓷基板。
  8. 一种光电装置，其特征在于，包括：
    第一基板，所述第一基板的第一表面上分别设置有专用集成电路ASIC、第二基板和光子集成电路PIC，所述第一表面上形成有所述第一基板的电路走线；
    嵌入设置在所述第一基板内的电子集成电路EIC，所述EIC通过所述第一基板的所述电路走线与所述第一基板上设置的所述ASIC电连接；
    贯穿所述第二基板的第二表面和所述第二基板的第三表面的至少一个导电通孔，所述PIC通过所述至少一个导电通孔与所述EIC电连接，其中，所述第二表面为所述第二基板沿所述第二基板的厚度方向远离所述第一基板的表面，所述第三表面为所述第二基板沿所述第二基板的厚度方向靠近所述第一基板的表面。
  9. 根据权利要求8所述的光电装置，其特征在于，
    所述第二基板和所述PIC被塑封介质塑封。
  10. 根据权利要求9所述的光电装置，其特征在于，
    所述至少一个导电通孔还贯穿所述塑封介质的第四表面和所述塑封介质的第五表面，其中，所述第四表面为所述塑封介质沿所述第二基板的厚度方向远离所述EIC的表面，所述第五表面为所述塑封介质沿所述第二基板的厚度方向靠近所述第一基板的表面。
  11. 根据权利要求10所述的光电装置，其特征在于，所述光电装置还包括贯穿所述塑封介质的所述第四表面和所述塑封介质的第六表面的至少一个第一导电金属线，所述第六表面为所述塑封介质沿所述第二基板的厚度方向位于所述第四表面与所述PIC之间、且与所述PIC接触的表面；
    所述PIC与所述至少一个第一导电金属线的第一端电连接，所述至少一个第一导电金属线的第二端通过所述至少一个导电通孔与所述EIC电连接。
  12. 根据权利要求11所述的光电装置，其特征在于，所述光电装置还包括设置在所述PIC的第七表面上的第一导电连接件，所述第七表面为所述PIC沿所述PIC的厚度方向远离该第一基板的表面；
    所述至少一个第一导电金属线的第二端与所述第一导电连接件的第一端电连接，所述第一导电连接件的第二端通过所述至少一个导电通孔与所述EIC电连接。
  13. 根据权利要求8至12中任一项所述的光电装置，其特征在于，
    所述第二基板为硅基板、玻璃基板或陶瓷基板。
  14. 一种光电集成结构，其特征在于，包括：
    印刷电路板PCB，所述PCB上集成有上述权利要求1至7中任一项所述的光电装置或8至13中任一项所述的光电装置。
PCT/CN2020/138618 2020-12-23 2020-12-23 光电装置以及光电集成结构 WO2022133801A1 (zh)

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CN206546453U (zh) * 2016-03-04 2017-10-10 颖飞公司 利用混合多芯片集成的光收发器
CN108735687A (zh) * 2017-04-14 2018-11-02 谷歌有限责任公司 用于高数据速率的硅光子ic的集成
CN111128990A (zh) * 2018-10-31 2020-05-08 台湾积体电路制造股份有限公司 集成电路封装件

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* Cited by examiner, † Cited by third party
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US20140151880A1 (en) * 2011-08-19 2014-06-05 Marvell World Trade Ltd. Package-on-package structures
CN206546453U (zh) * 2016-03-04 2017-10-10 颖飞公司 利用混合多芯片集成的光收发器
CN108735687A (zh) * 2017-04-14 2018-11-02 谷歌有限责任公司 用于高数据速率的硅光子ic的集成
CN111128990A (zh) * 2018-10-31 2020-05-08 台湾积体电路制造股份有限公司 集成电路封装件

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