WO2020237706A1 - 硅光模块的封装方法及硅光模块 - Google Patents

硅光模块的封装方法及硅光模块 Download PDF

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Publication number
WO2020237706A1
WO2020237706A1 PCT/CN2019/090063 CN2019090063W WO2020237706A1 WO 2020237706 A1 WO2020237706 A1 WO 2020237706A1 CN 2019090063 W CN2019090063 W CN 2019090063W WO 2020237706 A1 WO2020237706 A1 WO 2020237706A1
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Prior art keywords
silicon optical
chip
layer
silicon
optical chip
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PCT/CN2019/090063
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English (en)
French (fr)
Inventor
蔡艳
汪巍
涂芝娟
曾友宏
余明斌
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上海新微技术研发中心有限公司
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Publication of WO2020237706A1 publication Critical patent/WO2020237706A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to the field of optoelectronics, in particular to a packaging method of a silicon optical module and a silicon optical module.
  • Advanced packaging technology is an ideal choice to meet various performance requirements and complex heterogeneous integration requirements.
  • the wafer-level fan-out advanced package forms a bump array in a wider area than the chip, which can correspond to the bump contact size and pitch of the carrier board with a lower wiring density. Because it does not use the existing bonding wires, its internal connections are relatively short. Short, which is beneficial to reduce the overall package thickness, and can support high-speed electrical signal transmission, and does not use wires and interposers, which also helps reduce costs.
  • the packaging of silicon optical modules involves high-speed electrical interconnection of silicon optical chips with functional chips, and packaging with high-speed ceramic substrates or PCB substrates, usually using wire bonding or flip-chip packaging.
  • the packaging methods of wire bonding or flip-chip welding can no longer meet the demand.
  • Advanced packaging technology is a necessary way to solve these problems.
  • wafer-level fan-out packaging is also a feasible solution to increase bandwidth, increase integration, improve heat dissipation, reduce power consumption, and reduce packaging costs.
  • the packaging of silicon optical modules should consider not only electrical connection, but also optical coupling, especially fiber coupling technology and laser coupling technology. Therefore, the implementation of wafer-level fan-out packaging methods is much more difficult than Semiconductor field.
  • the technical problem to be solved by the present invention is to provide a packaging method for a silicon optical module and a silicon optical module.
  • the packaging method is a wafer-level fan-out packaging, which improves the bandwidth while ensuring that the optical fiber can be optically coupled with the optical fiber module , Improve integration, improve heat dissipation, reduce power consumption, and reduce packaging costs.
  • the present invention provides a silicon optical module packaging method, which includes the following steps: providing at least one silicon optical chip and at least one functional chip, the first surface of the silicon optical chip has an electrical connection layer, so At least one side of the silicon optical chip has an area for fiber end face coupling, the sacrificial layer covers at least the area for fiber end face coupling, and the first surface of the functional chip has an electrical connection layer;
  • the functional chip is arranged on a carrier wafer, and the first surface of the silicon optical chip and the first surface of the functional chip are in contact with the carrier wafer; the silicon optical chip and the functional chip are plastically sealed to form at least A silicon optical module unit including at least one silicon optical chip and at least one functional chip; the carrier wafer is removed to expose the first surface of the silicon optical chip and the first surface of the functional chip Form a rewiring layer, in the silicon optical module unit, the electrical connection layer of the silicon optical chip and the electrical connection layer of the functional chip are electrically connected to the rewiring layer, and the rewiring layer, and
  • the packaging method further includes a method for preparing a silicon optical chip
  • the method for preparing the silicon optical chip includes the following steps: providing a silicon optical wafer, the silicon optical wafer including a plurality of silicon optical chip units , The first surface of the silicon optical chip unit has an electrical connection layer, at least one side surface of the silicon optical chip unit has an area for fiber end face coupling; at least one trench is formed on the silicon optical wafer, so The groove exposes at least the area of the silicon optical chip unit for fiber end-face coupling; filling the groove with a sacrificial layer, the sacrificial layer covering the area of the silicon optical chip unit for optical fiber end-face coupling; cutting The silicon optical wafer forms the silicon optical chip, wherein the dicing line passes through the groove, and after cutting, the sacrificial layer is exposed.
  • the silicon optical wafer has a substrate layer and a dielectric layer disposed on the substrate layer, and the step of forming at least one trench on the silicon optical wafer includes: The area between the silicon optical chip units is sequentially removed from the dielectric layer and part of the substrate layer to form the trench. The bottom of the trench is located in the substrate layer. After the silicon optical wafer is cut, the bottom of the trench is not The cut backing layer is retained.
  • the sacrificial layer also covers the first surface of the silicon optical chip, so in the step of removing the carrier wafer, the sacrificial layer on the first surface of the silicon optical chip is also removed.
  • the material of the sacrificial layer is organic.
  • the method before the step of disposing the silicon optical chip and the functional chip on the carrier wafer, the method further includes performing the silicon optical chip and the functional chip with the carrier wafer. Alignment steps.
  • a step of forming an adhesive layer on the surface of the carrier wafer is included, then the silicon optical chip The chip and the functional chip are bonded to the surface of the carrier wafer through the adhesive layer.
  • the present invention also provides a silicon optical module prepared by using the above-mentioned packaging method, which includes a plastic package body and a redistribution layer arranged on the plastic package body. At least one side of the plastic package body has a notch, and the notch To allow fiber insertion, at least one silicon optical chip and at least one functional chip are arranged in the plastic package, at least one side of the silicon optical chip has an area for fiber end face coupling, and the area for fiber end face coupling is exposed In the recess, the redistribution layer is electrically connected to the silicon optical chip and the functional chip to electrically interconnect the silicon optical chip and the functional chip and to an external device.
  • the silicon optical chip includes a substrate layer and a dielectric layer disposed on the substrate layer, the dielectric layer is provided with a waveguide layer, and the side surface of the dielectric layer is exposed to the notch, It is used as the area where the silicon optical chip is used for fiber end face coupling.
  • part of the side surface of the substrate layer is also exposed to the recess.
  • the advantage of the present invention is that the packaging method is a wafer-level fan-out packaging method, which can increase bandwidth, increase integration, improve heat dissipation, reduce power consumption, and reduce packaging costs; at the same time, the packaging method also forms a method for optical fiber
  • the inserted recess allows the optical fiber to be optically coupled with the silicon optical module. That is to say, the packaging method of the present invention provides a good packaging process and also ensures that the optical fiber can be coupled with the silicon optical module.
  • FIG. 1 is a schematic diagram of the steps of the packaging method of the silicon optical module of the present invention.
  • FIGS. 2A to 2G are process flow diagrams of the packaging method of the silicon optical module of the present invention.
  • 3A to 3D are process flow diagrams of an embodiment of a method for manufacturing a silicon optical chip
  • Figure 4 is a schematic diagram of the structure of the silicon optical module of the present invention.
  • FIG. 1 is a schematic diagram of the steps of the packaging method of the silicon optical module of the present invention.
  • the packaging method of the silicon optical module of the present invention includes the following steps: Step S10, providing at least one silicon optical chip and at least one functional chip, the first surface of the silicon optical chip is provided with an electrical connection layer, and the silicon At least one side surface of the optical chip has an area for fiber end face coupling, the sacrificial layer covers at least the area for fiber end face coupling, and the first surface of the functional chip has an electrical connection layer; step S11, the silicon optical chip And the functional chip is arranged on a carrier wafer, the first surface of the silicon optical chip and the first surface of the functional chip are in contact with the carrier wafer; step S12, plastic packaging the silicon optical chip and the The functional chip forms at least one silicon optical module unit, the silicon optical module unit includes at least one silicon optical chip and at least one functional chip; step S13, the carrier wafer is removed to expose the first surface of the silicon optical chip and The first surface of the functional chip; step S
  • FIGS. 2A to 2G are process flow diagrams of the packaging method of the silicon optical module of the present invention.
  • step S10 and FIG. 2A Please refer to step S10 and FIG. 2A to provide at least one silicon optical chip 200 and at least one functional chip 210. Since the packaging method of the present invention is a wafer-level packaging, multiple silicon optical chips 200 and multiple functional chips 210 can be provided. Among them, only two silicon optical chips 200 and two functions are schematically shown in the drawings. Chip 210.
  • the first surface 200A of the silicon optical chip 200 is provided with an electrical connection layer 201.
  • a plurality of electrical connection points 2010 are provided in the electrical connection layer 201, and the electrical connection points 2010 can be electrically connected to different external structures.
  • a part of the electrical connection points may be electrically connected to the electrical connection points of the functional chip 210, and another part of the electrical connection points may be electrically connected to external devices.
  • At least one side surface of the silicon optical chip 200 has a region 200B for fiber end-face coupling.
  • the area 200B used for fiber end face coupling refers to the area that needs to be connected to the optical fiber after the silicon optical module is formed.
  • the silicon optical chip 200 may be provided with an area 200B for fiber end-face coupling only on one side, or may be provided with an area 200B for fiber end-face coupling on two or more side surfaces. In this embodiment, the silicon optical chip 200 is provided with an area 200B for fiber end-face coupling only on one side surface as an example for description.
  • the sacrificial layer 202 covers at least the area 200B for fiber end face coupling.
  • the sacrificial layer 202 can protect the region 200B for fiber end-face coupling to avoid damage to the region 200B for fiber end-face coupling during the packaging operation.
  • the sacrificial layer 202 may only cover the area 200B for fiber end-face coupling, or it may cover both the area 200B of the silicon optical chip for fiber end-face coupling and the first surface 200A.
  • the sacrificial layer 202 covers both the area 200B of the silicon optical chip 200 for fiber end-face coupling and the first surface 200A.
  • the first surface 210A of the functional chip 210 has an electrical connection layer 211.
  • a plurality of electrical connection points 2110 are provided in the electrical connection layer 211, and the electrical connection points 2110 can be electrically connected to different external structures.
  • a part of the electrical connection points may be electrically connected to the electrical connection points of the silicon optical chip 200, and another part of the electrical connection points may be electrically connected to external devices.
  • the functional chip 210 includes, but is not limited to, a functional chip using a silicon optical module well known to those skilled in the art, for example, an electric drive chip.
  • the present invention also provides an embodiment of the method for manufacturing the above-mentioned silicon optical chip.
  • 3A to 3D are process flow diagrams of an embodiment of a method for manufacturing a silicon optical chip.
  • a silicon optical wafer 300 is provided.
  • the silicon optical wafer 300 includes a plurality of silicon optical chip units 301.
  • Three silicon optical chip units 301 are schematically shown in FIG. 3A.
  • the first surface 301A of the silicon optical chip unit 301 has an electrical connection layer 302.
  • a plurality of electrical connection points 3020 are provided in the electrical connection layer 302, and the electrical connection points 3020 can be electrically connected to different external structures.
  • At least one side surface of the silicon optical chip unit has a region 301B (shown in FIG. 3B) for fiber end-face coupling.
  • the silicon optical wafer 300 has a substrate layer 310 and a dielectric layer 320 disposed on the substrate layer 310.
  • the dielectric layer 320 is provided with a waveguide layer 321, and the electrical connection layer 302 It is arranged on the dielectric layer 320.
  • the substrate layer 310, the dielectric layer 320, the waveguide layer 321, and the electrical connection layer 302 are all structures of silicon optical modules that are well known to those skilled in the art.
  • the substrate layer 310 includes but is not limited to a silicon substrate
  • the dielectric layer 320 includes but is not limited to an oxide layer
  • the waveguide layer 321 includes but is not limited to silicon, silicon nitride, or a specially designed dioxide Silicon or silicon oxynitride.
  • the silicon optical wafer 300 may include an SOI substrate wafer and a silicon nitride-based wafer.
  • SOI substrate wafers it includes a Si substrate, a 2 micron or 3 micron thick silicon dioxide buried oxide layer (BOX), and an epitaxial silicon layer above the silicon dioxide buried oxide layer.
  • the epitaxial silicon layer is generally several hundred thick Nanometer to several micrometers, where the epitaxial silicon layer can be used as a waveguide layer.
  • a thick silicon dioxide layer is formed on the silicon substrate, and a silicon nitride layer is deposited on the silicon dioxide layer, wherein the silicon nitride layer serves as a waveguide layer. Referring to FIG.
  • the trench 303 is formed on the silicon optical wafer 300, and the trench 303 exposes at least a region 301B of the silicon optical chip unit 301 for fiber end-face coupling.
  • the trench 303 may be formed by an etching process.
  • an etching process may be used to sequentially remove the dielectric layer 320 and part of the substrate layer 310 to form the trench 303, and the bottom of the trench 303 is located in the substrate layer 310.
  • the trench 303 may also penetrate the substrate layer 310.
  • the sacrificial layer 304 is filled in the trench 303.
  • the sacrificial layer 304 covers the area 301B of the silicon optical chip unit 301 for fiber end-face coupling.
  • the sacrificial layer 304 fills the trench 303, and the sacrificial layer 304 covers the first surface 301A of the silicon optical chip unit 301.
  • the sacrificial layer 304 may only cover the area of the silicon optical chip unit 301 for fiber end-face coupling.
  • the silicon optical wafer 300 is cut to form the silicon optical chip 200.
  • the dicing path when cutting the silicon optical wafer 300 passes through the trench 303, and after cutting, the sacrificial layer 304 on the side of the silicon optical module unit 301 is exposed.
  • the uncut substrate layer 310 at the bottom of the trench 303 is retained, that is, the side surface of the substrate layer 310 forms a stepped configuration.
  • the present invention only lists the above-mentioned preparation methods of the silicon optical chip. It is understood that those skilled in the art can also use other conventional methods to form the silicon optical chip.
  • step S11 and FIG. 2B Please continue to refer to step S11 and FIG. 2B to set the silicon optical chip 200 and the functional chip 210 on the carrier wafer 220.
  • the silicon optical chip 200 is fixed relative to the carrier wafer 220
  • the function chip 210 is fixed relative to the carrier wafer 220.
  • the material of the carrier wafer 220 includes but is not limited to silicon or glass.
  • the first surface 200A of the silicon optical chip 200 and the first surface 210A of the functional chip 210 are in contact with the carrier wafer 220, that is, the first surface 200A of the silicon optical chip 200 has an electrical connection layer 201 It is fixedly connected to the carrier wafer 220, and the first surface 210A of the functional chip 210 having the electrical connection layer 211 is fixedly connected to the carrier wafer 220.
  • step S11 the step of forming an adhesive layer 230 on the surface of the carrier wafer 220 is also included.
  • the silicon optical chip 200 and the functional chip 210 pass through The bonding layer 230 is bonded to the surface of the carrier wafer 220.
  • the material of the adhesive layer 230 includes but is not limited to organic matter.
  • the sacrificial layer 202 since the sacrificial layer 202 also covers the first surface 200A, after performing this step, the sacrificial layer 202 is in contact with the adhesive layer 230.
  • step S11 it further includes a step of aligning the silicon optical chip 200 and the functional chip 210 with the carrier wafer 220.
  • the silicon optical chip 200 and the functional chip 210 are placed on the carrier wafer 220, the silicon optical chip 200 and the functional chip 210 are combined with each other.
  • the edges of the carrier wafer 220 are aligned.
  • the alignment accuracy can be about 0.1mm.
  • alignment marks are first prepared on the carrier wafer 220, and the silicon optical chip 200 and the functional chip 210 are placed The optical chip 200 and the functional chip 210 are aligned with pre-made alignment marks.
  • the silicon optical module unit 240 includes at least one silicon optical chip 200 and at least one functional chip 210 .
  • the silicon optical module unit 240 includes a silicon optical chip 200 and a functional chip 210.
  • the silicon optical module unit may also include multiple silicon optical chips 200 and multiple
  • the functional chip 210 is not limited herein.
  • the molding method is a method well known to those skilled in the art, and the molding material includes, but is not limited to, a composite material of epoxy resin and highly doped silicon.
  • step S13 and FIG. 2D Please continue to refer to step S13 and FIG. 2D to remove the carrier wafer 220 to expose the first surface 200A of the silicon optical chip 200 and the first surface 210A of the functional chip 210.
  • the adhesive layer 230 and the sacrificial layer 202 in contact with the adhesive layer 230 are removed at the same time.
  • the bonding layer 230 and the sacrificial layer 202 can be removed by wet or dry etching.
  • the rewiring layer 250 is formed.
  • the electrical connection layer 201 of the silicon optical chip 200 and the electrical connection layer 211 of the functional chip 210 are electrically connected to the redistribution layer 250, and the redistribution layer 250 is used to
  • the silicon optical chip 200 is electrically connected to the functional chip 210, and the silicon optical chip 200 and the functional chip 210 are electrically connected to external devices.
  • the rewiring layer 250 is a conventional electrical connection structure in the art, and electrical connection lines are arranged inside it.
  • the rewiring layer 250 includes but is not limited to one or more copper wiring layers.
  • the electrical connection layer of the silicon optical chip 200 is connected to the electrical connection lines in the redistribution layer 250, and the electrical connection layer of the functional chip 210 is connected to the electrical connection lines in the redistribution layer 250, thereby enabling The silicon optical chip 200 and the functional chip 210 are electrically interconnected.
  • the electrical connection layer 201 of the silicon optical chip 200 can also be electrically connected to the pins 251 located on the end surface of the rewiring layer through the redistribution layer 250, and the electrical connection layer 211 of the functional chip 210 can also pass through
  • the redistribution layer 250 is electrically connected to the pins 251 on the surface of the redistribution layer.
  • the pin 251 will be connected with a high-speed ceramic substrate or a substrate of a printed circuit board to supply power to the functional chip and output electrical signals.
  • the production of pins 251 on the rewiring layer 250 is a conventional structure in the art, and will not be repeated here.
  • the redistribution layer 250 covers the exposed surface of the silicon optical chip 200, the functional chip 210, and the lower surface of the plastic package body 260, and is located on the lower surface of the silicon optical chip 200.
  • the sacrificial layer 202 is also covered by the rewiring layer 250.
  • a plurality of independent silicon light module units 240 are formed by cutting, and the sacrificial layer 202 is exposed.
  • the cutting line must pass through at least the side surface of the sacrificial layer 202 or through the sacrificial layer 202 to ensure that the sacrificial layer 202 can be cut and be exposed after cutting to facilitate subsequent processes.
  • step S16 and FIG. 2G Please refer to step S16 and FIG. 2G to remove the sacrificial layer 202.
  • the sacrificial layer 202 is an organic substance, it can generally be cleaned and removed by a wet etching method.
  • a notch 270 is formed in the original position of the sacrificial layer 202. Since the sacrificial layer 202 covers the area 200B of the silicon optical chip for fiber end-face coupling, after the sacrificial layer 202 is removed, the area of the silicon optical chip for optical fiber end-face coupling is exposed to the notch 270.
  • the area of the silicon optical chip used for fiber end-face coupling can be coupled with an external optical fiber for light input and output.
  • the notch 270 is used to support the optical fiber, that is, when an external optical fiber is coupled with the silicon optical chip 200, the optical fiber can be inserted into the notch 270, and the notch 270 functions to guide and support the The role of the fiber end face.
  • the packaging method of the silicon optical module of the present invention is a wafer-level fan-out packaging method, which can increase bandwidth, improve integration, improve heat dissipation, reduce power consumption, and reduce packaging costs; at the same time, the packaging method also forms a method for fiber insertion The notch allows the optical fiber to be coupled to the silicon optical module. That is to say, the packaging method of the present invention can ensure that the optical fiber can be coupled with the silicon optical module while providing a good packaging process.
  • the invention also provides a silicon optical module prepared by adopting the above-mentioned packaging method.
  • Figure 4 is a schematic diagram of the structure of the silicon optical module of the present invention. Please refer to FIG. 4, the silicon light module of the present invention includes a plastic package 400 and a redistribution layer 410 disposed on the plastic package 400.
  • At least one side surface of the plastic package 400 has a notch 401.
  • the notch 401 is recessed toward the inside of the plastic package 400.
  • the notch 401 allows optical fibers (not shown in the drawings) to be inserted for light input and output.
  • one side of the plastic package 400 has a notch 401, and in other embodiments of the present invention, multiple sides of the plastic package 400 have a notch 401.
  • At least one silicon optical chip 402 is arranged in the plastic package 400.
  • the silicon optical module includes one silicon optical chip 402.
  • the silicon optical module may also include multiple silicon optical chips.
  • At least one side surface of the silicon optical chip 402 has a region 402B for fiber end-face coupling. The region 402B for coupling of the fiber end face is exposed to the notch 401.
  • the silicon optical chip 402 includes a substrate layer 4021 and a dielectric layer 4022 disposed on the substrate layer 4021.
  • the dielectric layer 4022 is provided with a waveguide layer, and the side surface of the dielectric layer 4022 is exposed to the notch 401 to serve as an area of the silicon optical chip for fiber end-face coupling.
  • the structure of the region 402B of the silicon optical chip for coupling to the end face of the optical fiber is a conventional structure of the silicon optical chip in the art, and will not be repeated. Further, part of the side surface of the substrate layer 4021 is also exposed to the notch 401, so that the notch 401 can provide better support for the optical fiber.
  • At least one functional chip 403 is arranged in the plastic package 400.
  • the silicon optical module includes one functional chip 403.
  • the silicon optical module may also include multiple functional chips 403.
  • the functional chip 403 includes, but is not limited to, a functional chip using a silicon optical module well known to those skilled in the art, for example, an electric drive chip.
  • the redistribution layer 410 is electrically connected with the silicon optical chip 402 and the functional chip 403 to electrically interconnect the silicon optical chip 402 with the functional chip 403 and with external devices.
  • the rewiring layer 410 is connected to the electrical connection layer 4023 of the silicon optical chip 402, and is electrically connected to the electrical connection layer 4031 of the functional chip 403, so that the silicon optical chip 402 can be
  • the functional chip 403 is electrically interconnected and the silicon optical chip 402 and the functional chip 403 are electrically connected to external devices.
  • a notch 401 is formed on the side of the plastic package 400, which can facilitate the combination of the optical fiber and the silicon optical module, thereby improving the optical coupling performance of the optical fiber and the silicon optical module.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

一种硅光模块及其封装方法，采用晶圆级扇出封装方法，提供至少一硅光芯片及至少一功能芯片，在硅光芯片的至少一侧面具有用于光纤端面耦合的区域形成凹口，以暴露出硅光芯片用于光纤端面耦合的区域，且凹口用于支撑光纤使得光纤能够与硅光模块耦合。

Description

硅光模块的封装方法及硅光模块 技术领域
本发明涉及光电领域，尤其涉及一种硅光模块的封装方法及硅光模块。
背景技术
目前半导体产业中涌现了许多新兴的大趋势应用，比如移动应用、大数据、人工智能(AI)、5G、高性能计算(HPC)、物联网(IoT)、智能汽车、工业4.0和数据中心等。支持这些新兴大趋势的电子硬件需要高计算能力、高速度、更多带宽、低延迟、低功耗、更多功能、更多内存、系统级集成、各种传感器，以及最重要的低成本。
先进封装技术是满足各种性能要求和复杂异构集成需求的理想选择。晶圆级扇出形先进封装在比芯片更广的面积中构成凸块阵列，可对应配线密度较低的载板凸块接点尺寸与间距，因不使用既有打线，其内部连结较短，有利于缩减整体封装厚度，并可支持高速电信号的传输，且未使用打线与中介层，亦有助于降低成本。
硅光模块的封装涉及到将硅光芯片与功能芯片进行高速电互连，并与高速陶瓷基板或PCB基板进行封装，通常使用打线或者倒装焊的封装方式。随着硅光模块的带宽、功耗、集成度等更高的性能要求，打线或者倒装焊的封装方式已经不能满足需求。先进封装技术是解决这些问题的必需途径。除了基于硅通孔TSV的2.5D/3D封装形式，晶圆级的扇出形封装也是提高带宽、提高集成度、改善散热、降低功耗、降低封装成本的可行方案。但是，硅光模块的封装不仅仅要考虑电的连接，更要考虑光的耦合，尤其是光纤耦合技术和激光器耦合技术，因此，晶圆级的扇出形封装方法的实施难度远远高于半导体领域。
应该注意，上面对技术背景的介绍只是为了方便对本申请的技术方案进行清楚、完整的说明，并方便本领域技术人员的理解而阐述的。不能仅仅因为这些方案在本申请的背景技术部分进行了阐述而认为上述技术方案为本领域技术人员所公知。
发明内容
本发明所要解决的技术问题是，提供一种硅光模块的封装方法及硅光模块，该封装方法是晶圆级扇出形封装，在保证光纤能够与光纤模块进行光耦合的同时，提高带宽、提高集成度、改善散热、降低功耗、降低封装成本。
为了解决上述问题，本发明提供了一种硅光模块的封装方法，其包括如下步骤：提供至少一硅光芯片及至少一功能芯片，所述硅光芯片的第一表面具有电连接层，所述硅光芯片的至少一侧面具有用于光纤端面耦合的区域，牺牲层至少覆盖用于光纤端面耦合的区域， 所述功能芯片的第一表面具有电连接层；将所述硅光芯片及所述功能芯片设置在载体晶圆上，所述硅光芯片的第一表面及所述功能芯片的第一表面与所述载体晶圆接触；塑封所述硅光芯片及所述功能芯片，形成至少一硅光模块单元，硅光模块单元包括至少一硅光芯片及至少一功能芯片；去除所述载体晶圆，以暴露出所述硅光芯片的第一表面及所述功能芯片的第一表面；形成重布线层，在硅光模块单元中，所述硅光芯片的电连接层及所述功能芯片的电连接层与所述重布线层电连接，所述重布线层用于将所述硅光芯片与所述功能芯片电连接，并将所述硅光芯片及所述功能芯片与外部器件电连接；切割形成多个彼此独立的硅光模块单元，暴露所述牺牲层；去除所述牺牲层，形成凹口，以暴露出所述硅光芯片用于光纤端面耦合的区域，且所述凹口用于支撑光纤。
在一实施例中，所述封装方法还包括硅光芯片的制备方法，所述硅光芯片的制备方法包括如下步骤：提供硅光晶圆，所述硅光晶圆包括多个硅光芯片单元，所述硅光芯片单元的第一表面具有电连接层，所述硅光芯片单元的至少一侧面具有用于光纤端面耦合的区域；在所述硅光晶圆上形成至少一沟槽，所述沟槽至少暴露出所述硅光芯片单元用于光纤端面耦合的区域；在所述沟槽中填充牺牲层，所述牺牲层覆盖所述硅光芯片单元用于光纤端面耦合的区域；切割所述硅光晶圆，形成所述硅光芯片，其中切割道经过所述沟槽，切割后，暴露所述牺牲层。
在一实施例中，所述硅光晶圆具有衬底层及设置在所述衬底层上的介质层，在所述硅光晶圆上形成至少一沟槽的步骤包括：在相邻的两个硅光芯片单元之间的区域依次去除所述介质层及部分衬底层而形成所述沟槽，所述沟槽底部位于所述衬底层中，切割所述硅光晶圆后，沟槽底部未被切割的衬底层被保留。
在一实施例中，所述牺牲层还覆盖所述硅光芯片的第一表面，则在去除所述载体晶圆的步骤中，所述硅光芯片的第一表面的牺牲层也被去除。
在一实施例中，所述牺牲层的材料为有机物。
在一实施例中，在将所述硅光芯片及所述功能芯片设置在所述载体晶圆上的步骤之前，还包括将所述硅光芯片及所述功能芯片与所述载体晶圆进行对准的步骤。
在一实施例中，在将所述硅光芯片及所述功能芯片设置在所述载体晶圆上的步骤之前，包括在所述载体晶圆表面形成粘结层的步骤，则所述硅光芯片及所述功能芯片通过所述粘结层粘结在所述载体晶圆表面。
本发明还提供一种采用上述的封装方法制备的硅光模块，其包括塑封体及设置在所述 塑封体上的重布线层，所述塑封体的至少一侧面具有凹口，所述凹口允许光纤插入，至少一硅光芯片及至少一功能芯片设置在所述塑封体内，所述硅光芯片的至少一侧面具有用于光纤端面耦合的区域，所述用于光纤端面耦合的区域被暴露于所述凹口，所述重布线层与所述硅光芯片及所述功能芯片电连接，以将所述硅光芯片与所述功能芯片电互连及与外部器件电连接。
在一实施例中，所述硅光芯片包括衬底层及设置在所述衬底层上的介质层，所述介质层中设置有波导层，所述介质层的侧面被暴露于所述凹口，以作为所述硅光芯片用于光纤端面耦合的区域。
在一实施例中，所述衬底层的部分侧面也被暴露于所述凹口。
本发明的优点在于，该封装方法是晶圆级扇出形封装的方法，其能够提高带宽、提高集成度、改善散热、降低功耗、降低封装成本；同时该封装方法还形成了用于光纤插入的凹口，其使得光纤能够与硅光模块进行光纤耦合。也就是说，本发明封装方法在提供了良好的封装工艺的同时还保证光纤能够与硅光模块耦合。
附图说明
图1是本发明硅光模块的封装方法的步骤示意图；
图2A～图2G是本发明硅光模块的封装方法的工艺流程图；
图3A～图3D是硅光芯片的制备方法的一实施例的工艺流程图；
图4是本发明硅光模块的结构示意图。
具体实施方式
下面结合附图对本发明提供的硅光模块的封装方法及硅光模块的具体实施方式做详细说明。
图1是本发明硅光模块的封装方法的步骤示意图。请参阅图1，本发明硅光模块的封装方法包括如下步骤：步骤S10、提供至少一硅光芯片及至少一功能芯片，所述硅光芯片的第一表面设置有电连接层，所述硅光芯片的至少一侧面具有用于光纤端面耦合的区域，牺牲层至少覆盖用于光纤端面耦合的的区域，所述功能芯片的第一表面具有电连接层；步骤S11、将所述硅光芯片及所述功能芯片设置在载体晶圆上，所述硅光芯片的第一表面及所述功能芯片的第一表面与所述载体晶圆接触；步骤S12、塑封所述硅光芯片及所述功能芯片，形成至少一硅光模块单元，硅光模块单元包括至少一硅光芯片及至少一功能芯片；步骤S13、去除所述载体晶圆，以暴露出所述硅光芯片的第一表面及所述功能芯片的第一表面；步骤S14、 形成重布线层，在硅光模块单元中，所述硅光芯片的电连接层及所述功能芯片的电连接层与所述重布线层电连接，所述重布线层用于将所述硅光芯片与所述功能芯片电连接，并将所述硅光芯片及所述功能芯片与外部器件电连接；步骤S15、切割形成多个彼此独立的硅光模块单元，暴露所述牺牲层；步骤S16、去除所述牺牲层，形成凹口，以暴露出所述硅光芯片用于光纤端面耦合的区域，且所述凹口用于支撑光纤。
图2A～图2G是本发明硅光模块的封装方法的工艺流程图。
请参阅步骤S10及图2A，提供至少一硅光芯片200及至少一功能芯片210。由于本发明封装方法为晶圆级的封装，则可提供多个硅光芯片200及多个功能芯片210，其中，在附图中仅示意性地绘示两个硅光芯片200及两个功能芯片210。
由于本发明并未涉及硅光芯片200内部结构的改进，所以与本发明技术方案不相关的所述硅光芯片200的内部结构并未示出。所述硅光芯片200的第一表面200A设置有电连接层201。具体地说，在所述电连接层201中设置有多个电连接点2010，所述电连接点2010可与外部的不同结构电连接。例如，一部分电连接点可与功能芯片210的电连接点电连接，另一部分电连接点可以与外部器件电连接。所述硅光芯片200的至少一侧面具有用于光纤端面耦合的区域200B。所述用于光纤端面耦合的区域200B指的是形成硅光模块后需要与光纤对接的区域。所述硅光芯片200可仅在一个侧面设置用于光纤端面耦合的区域200B，也可在两个及以上的侧面设置用于光纤端面耦合的区域200B。在本实施例中，以所述硅光芯片200仅在一个侧面设置用于光纤端面耦合的区域200B为例进行说明。
牺牲层202至少覆盖用于光纤端面耦合的区域200B。所述牺牲层202可保护所述用于光纤端面耦合的区域200B，以避免在封装操作过程中用于光纤端面耦合的区域200B被破坏。所述牺牲层202可以仅覆盖用于光纤端面耦合的区域200B，也可以既覆盖所述硅光芯片用于光纤端面耦合的区域200B，又覆盖所述第一表面200A。例如，在本实施例中，所述牺牲层202既覆盖所述硅光芯片200用于光纤端面耦合的区域200B，也覆盖所述第一表面200A。
所述功能芯片210的第一表面210A具有电连接层211。具体地说，在所述电连接层211中设置有多个电连接点2110，所述电连接点2110可与外部的不同结构电连接。例如，一部分电连接点可与硅光芯片200的电连接点电连接，另一部分电连接点可以与外部器件电连接。所述功能芯片210包括但不限于本领域技术人员熟知的用硅光模块的功能芯片，例如，电驱动芯片。
其中，本发明还提供了上述硅光芯片的制备方法的一个实施例。图3A～图3D是硅光芯片的制备方法的一实施例的工艺流程图。
请参阅图3A，提供硅光晶圆300，所述硅光晶圆300包括多个硅光芯片单元301。在图3A中示意性地绘示三个硅光芯片单元301。
所述硅光芯片单元301的第一表面301A具有电连接层302。所述电连接层302中设置有多个电连接点3020，所述电连接点3020可与外部的不同结构电连接。所述硅光芯片单元的至少一侧面具有用于光纤端面耦合的区域301B(绘示于图3B)。在本实施例中，所述硅光晶圆300具有衬底层310及设置在所述衬底层310上的介质层320，在所述介质层320中设置有波导层321，所述电连接层302设置在所述介质层320上。其中，所述衬底层310、所述介质层320、所述波导层321及所述电连接层302均为本领域技术人员熟知的用硅光模块的的结构。例如，所述衬底层310包括但不限于硅衬底，所述介质层320包括但不限于氧化物层，所述波导层321包括但不限于硅、氮化硅或者是通过特殊设计的二氧化硅或氮氧化硅。
所述硅光晶圆300可包括SOI衬底晶圆及基于氮化硅的晶圆。对于SOI衬底晶圆，其包括Si衬底、2微米或者3微米厚的二氧化硅埋氧层(BOX)以及二氧化硅埋氧层上面的外延硅层，外延硅层一般厚度为几百纳米到几微米，其中所述外延硅层可作为波导层。对于基于氮化硅的晶圆，硅衬底上形成较厚的二氧化硅层，在二氧化硅层上沉积氮化硅层，其中所述氮化硅层作为波导层。请参阅图3B，在所述硅光晶圆300上形成至少一沟槽303，所述沟槽303至少暴露出所述硅光芯片单元301用于光纤端面耦合的区域301B。具体地说，可采用刻蚀工艺形成所述沟槽303。在本实施例中，可采用刻蚀工艺依次去除所述介质层320及部分衬底层310而形成所述沟槽303，所述沟槽303底部位于所述衬底层310中。在本发明其他实施例中，所述沟槽303也可贯穿所述衬底层310。
请参阅图3C，在所述沟槽303中填充牺牲层304。所述牺牲层304覆盖所述硅光芯片单元301用于光纤端面耦合的区域301B。在本实施例中，所述牺牲层304填充满所述沟槽303，且所述牺牲层304覆盖所述硅光芯片单元301的第一表面301A。在本发明其他实施例中，所述牺牲层304可仅覆盖所述硅光芯片单元301用于光纤端面耦合的区域。
请参阅图3D，切割所述硅光晶圆300，形成所述硅光芯片200。其中，切割所述硅光晶圆300时的切割道经过所述沟槽303，则切割后，在所述硅光模块单元301的侧面所述牺牲层304被暴露。进一步，在本实施例中，沟槽303底部未被切割的衬底层310被保留， 即所述衬底层310的侧面形成台阶构型。
本发明仅列举了硅光芯片的上述的制备方法，可以理解的是，本领域技术人员也可采用其他常规方法形成所述硅光芯片。
请继续参阅步骤S11及图2B，将所述硅光芯片200及所述功能芯片210设置在载体晶圆220上。也就是说，所述硅光芯片200相对于所述载体晶圆220固定，所述功能芯片210相对于所述载体晶圆220固定。所述载体晶圆220的材料包括但不限于硅或者玻璃。其中，所述硅光芯片200的第一表面200A及所述功能芯片210的第一表面210A与所述载体晶圆220接触，即所述硅光芯片200具有电连接层201的第一表面200A与所述载体晶圆220固定连接，所述功能芯片210具有电连接层211的第一表面210A与所述载体晶圆220固定连接。
进一步，在本实施例中，在步骤S11之前还包括在所述载体晶圆220表面形成粘结层230的步骤，则请参阅图2B，所述硅光芯片200及所述功能芯片210通过所述粘结层230粘结在所述载体晶圆220表面。所述粘结层230的材料包括但不限于有机物。其中，在本实施例中，由于所述牺牲层202也覆盖所述第一表面200A，则在实施本步骤后，所述牺牲层202与所述粘结层230接触。
进一步，在步骤S11之前，还包括将所述硅光芯片200及所述功能芯片210与所述载体晶圆220进行对准步骤。具体地说，在本发明一实施例中，在将所述硅光芯片200及所述功能芯片210放置在载体晶圆220上时，会将所述硅光芯片200及所述功能芯片210与载体晶圆220的边缘进行对准。其中，对准精度可在0.1mm左右。在本发明另一实施例中，为了具有更高的对准精度，在载体晶圆220上首先制备好对准标记，在放置所述硅光芯片200及所述功能芯片210时将所述硅光芯片200及所述功能芯片210与预先做好的对准标记进行对准。
请继续参阅步骤S12及图2C，塑封所述硅光芯片200及所述功能芯片210，形成至少一硅光模块单元240，硅光模块单元240包括至少一硅光芯片200及至少一功能芯片210。在本实施例中，硅光模块单元240包括一个硅光芯片200及一个功能芯片210，而在本发明其他实施例中，所述硅光模块单元也可以包括多个硅光芯片200及多个功能芯片210，本文对此不进行限定。其中，塑封方法为本领域技术人员熟知的方法，塑封材料包括但不限于环氧树脂及高掺杂硅的复合材料。在塑封后，所述硅光芯片200及所述功能芯片210被所述载体晶圆220遮挡的表面未被塑封料覆盖，用于塑封的塑封料形成塑封体260。
请继续参阅步骤S13及图2D，去除所述载体晶圆220，以暴露出所述硅光芯片200的第一表面200A及所述功能芯片210的第一表面210A。在本实施例中，同时去除所述粘结层230及与所述粘结层230接触的所述牺牲层202。其中，可采用湿法或者干法刻蚀的方法去除所述粘结层230及所述牺牲层202。去除所述载体晶圆220、粘结层230及牺牲层202后，所述硅光芯片200的电连接层201、所述功能芯片210的电连接层211及所述塑封体260的下表面被暴露。
请参阅步骤S14及图2E，形成重布线层250。在硅光模块单元240中，所述硅光芯片200的电连接层201及所述功能芯片210的电连接层211与所述重布线层250电连接，所述重布线层250用于将所述硅光芯片200与所述功能芯片210电连接，并将所述硅光芯片200及所述功能芯片210与外部器件电连接。所述重布线层250为本领域常规的电连接结构，其内部设置有电连接线路，例如所述重布线层250包括但不限于一层或多层铜布线层。所述硅光芯片200的电连接层与所述重布线层250内的电连接线路连接，所述功能芯片210的电连接层与所述重布线层250内的电连接线路连接，进而能够实现所述硅光芯片200与所述功能芯片210的电互连。同时，所述硅光芯片200的电连接层201还能够通过所述重布线层250与位于所述重布线层端面的引脚251电连接，所述功能芯片210的电连接层211也能够通过所述重布线层250与位于所述重布线层表面的引脚251电连接。所述引脚251将与高速陶瓷衬底或者印刷电路板的基板相连接，对功能芯片进行供电以及用于电信号的输出。在所述重布线层250上制作引脚251为本领域常规结构，不再赘述。
其中，在本实施中，所述重布线层250覆盖所述硅光芯片200、所述功能芯片210裸露的表面及所述塑封体260的下表面，位于所述硅光芯片200的下表面的牺牲层202也被所述重布线层250覆盖。
请参阅步骤S15及图2F，切割形成多个彼此独立的硅光模块单元240，暴露所述牺牲层202。具体地说，切割道至少要经过所述牺牲层202的侧面或者经过所述牺牲层202，以确保所述牺牲层202能够被切割，并在切割后被暴露，以利于后续工艺的进行。
请参阅步骤S16及图2G，去除所述牺牲层202。其中，若所述牺牲层202为有机物，则一般可以通过湿法刻蚀的方法清洗去除。牺牲层202被去除后，在所述牺牲层202的原始位置形成凹口270。由于牺牲层202覆盖所述硅光芯片用于光纤端面耦合的区域200B，则在牺牲层202被去除后，所述硅光芯片用于光纤端面耦合的区域被暴露于所述凹口270。硅光芯片的用于光纤端面耦合的区域就能够与外部光纤相耦合，进行光的输入和输出。所 述凹口270用于支撑光纤，也就是说，当外部光纤与所述硅光芯片200耦合时，所述光纤可插入所述凹口270，所述凹口270起到导向及支撑所述光纤端面的作用。
本发明硅光模块的封装方法是晶圆级扇出形封装的方法，其能够提高带宽、提高集成度、改善散热、降低功耗、降低封装成本；同时该封装方法还形成了用于光纤插入的凹口，其使得光纤能够与硅光模块进行光纤耦合。也就是说，本发明封装方法在提供了良好的封装工艺的同时还能够保证光纤能够与硅光模块耦合。
本发明还提供一种采用上述封装方法制备的硅光模块。图4是本发明硅光模块的结构示意图。请参阅图4，本发明硅光模块包括塑封体400及设置在所述塑封体400上的重布线层410。
所述塑封体400的至少一侧面具有凹口401。所述凹口401朝向所述塑封体400的内部凹陷。所述凹口401允许光纤(附图中未绘示)插入，以进行光的输入与输出。在本实施例中，所述塑封体400的一个侧面具有凹口401，在本发明其他实施例中，所述塑封体400的多个侧面具有凹口401。
至少一硅光芯片402设置在所述塑封体400内。在本实施例中，所述硅光模块包括一个硅光芯片402，在本发明其他实施例中，所述硅光模块也可以包括多个硅光芯片。所述硅光芯片402的至少一侧面具有用于光纤端面耦合的区域402B。所述用于光纤端面耦合的区域402B被暴露于所述凹口401。
进一步，所述硅光芯片402包括衬底层4021及设置在所述衬底层4021上的介质层4022。所述介质层4022中设置有波导层，所述介质层4022的侧面被暴露于所述凹口401，以作为所述硅光芯片用于光纤端面耦合的区域。所述硅光芯片的用于光纤端面耦合的区域402B的结构为本领域硅光芯片的常规结构，不再赘述。进一步，所述衬底层4021的部分侧面也被暴露于所述凹口401，从而使得所述凹口401能够为光纤提供更好的支撑。
至少一功能芯片403设置在所述塑封体400内。在本实施例中，所述硅光模块包括一个功能芯片403，在本发明其他实施例中，所述硅光模块也可以包括多个功能芯片403。所述功能芯片403包括但不限于本领域技术人员熟知的用硅光模块的功能芯片，例如，电驱动芯片。
所述重布线层410与所述硅光芯片402及所述功能芯片403电连接，以将所述硅光芯片402与所述功能芯片403电互连及与外部器件电连接。具体地说，所述重布线层410与所述硅光芯片402的电连接层4023连接，并与所述功能芯片403的电连接层4031电连接， 从而能够实现所述硅光芯片402与所述功能芯片403电互连及所述硅光芯片402与所述功能芯片403与外部器件的电连接。进一步，在所述重布线层410的表面具有多个引脚411，所述硅光芯片402的电连接层4023及所述功能芯片403的电连接层4031通过所述重布线层410连接至所述引脚411。
在本发明中，所述塑封体400侧面形成凹口401，其能够便于光纤与所述硅光模块的结合，从而提高光纤与硅光模块的光耦合性能。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种硅光模块的封装方法，其特征在于，包括如下步骤：
    提供至少一硅光芯片及至少一功能芯片，所述硅光芯片的第一表面具有电连接层，所述硅光芯片的至少一侧面具有用于光纤端面耦合的区域，牺牲层至少覆盖用于光纤端面耦合的区域，所述功能芯片的第一表面具有电连接层；
    将所述硅光芯片及所述功能芯片设置在载体晶圆上，所述硅光芯片的第一表面及所述功能芯片的第一表面与所述载体晶圆接触；
    塑封所述硅光芯片及所述功能芯片，形成至少一硅光模块单元，所述硅光模块单元包括至少一硅光芯片及至少一功能芯片；
    去除所述载体晶圆，以暴露出所述硅光芯片的第一表面及所述功能芯片的第一表面；
    形成重布线层，在硅光模块单元中，所述硅光芯片的电连接层及所述功能芯片的电连接层与所述重布线层电连接，所述重布线层用于将所述硅光芯片与所述功能芯片电连接，并将所述硅光芯片及所述功能芯片与外部器件电连接；
    切割形成多个彼此独立的硅光模块单元，暴露所述牺牲层；
    去除所述牺牲层，形成凹口，以暴露出所述硅光芯片用于光纤端面耦合的区域，且所述凹口用于支撑光纤。
  2. 根据权利要求1所述的硅光模块的封装方法，其特征在于，所述封装方法还包括硅光芯片的制备方法，所述硅光芯片的制备方法包括如下步骤：
    提供硅光晶圆，所述硅光晶圆包括多个硅光芯片单元，所述硅光芯片单元的第一表面具有电连接层，所述硅光芯片单元的至少一侧面具有用于光纤端面耦合的区域；
    在所述硅光晶圆上形成至少一沟槽，所述沟槽至少暴露出所述硅光芯片单元用于光纤端面耦合的区域；
    在所述沟槽中填充牺牲层，所述牺牲层覆盖所述硅光芯片单元用于光纤端面耦合的区域；
    切割所述硅光晶圆，形成所述硅光芯片，其中切割道经过所述沟槽，切割后，暴露所述牺牲层。
  3. 根据权利要求2所述的硅光模块的封装方法，其特征在于，所述硅光晶圆具有衬底层及设置在所述衬底层上的介质层，在所述硅光晶圆上形成至少一沟槽的步骤包括：在相邻的两个硅光芯片单元之间的区域依次去除所述介质层及部分衬底层而形成所述沟槽，所 述沟槽底部位于所述衬底层中，切割所述硅光晶圆后，沟槽底部未被切割的衬底层被保留。
  4. 根据权利要求1～3任意一项所述的硅光模块的封装方法，其特征在于，所述牺牲层还覆盖所述硅光芯片的第一表面，则在去除所述载体晶圆的步骤中，所述硅光芯片的第一表面的牺牲层也被去除。
  5. 根据权利要求1～3任意一项所述的硅光模块的封装方法，其特征在于，所述牺牲层的材料为有机物。
  6. 根据权利要求1～3任意一项所述的硅光模块的封装方法，其特征在于，在将所述硅光芯片及所述功能芯片设置在所述载体晶圆上的步骤之前，还包括将所述硅光芯片及所述功能芯片与所述载体晶圆进行对准的步骤。
  7. 根据权利要求1～3任意一项所述的硅光模块的封装方法，其特征在于，在将所述硅光芯片及所述功能芯片设置在所述载体晶圆上的步骤之前，包括在所述载体晶圆表面形成粘结层的步骤，则所述硅光芯片及所述功能芯片通过所述粘结层粘结在所述载体晶圆表面。
  8. 一种采用权利要求1～7任意一项所述的封装方法制备的硅光模块，其特征在于，包括塑封体及设置在所述塑封体上的重布线层，所述塑封体的至少一侧面具有凹口，所述凹口允许光纤插入，至少一硅光芯片及至少一功能芯片设置在所述塑封体内，所述硅光芯片的至少一侧面具有用于光纤端面耦合的区域，所述用于光纤端面耦合的区域被暴露于所述凹口，所述重布线层与所述硅光芯片及所述功能芯片电连接，以将所述硅光芯片与所述功能芯片电互连及与外部器件电连接。
  9. 根据权利要求8所述的硅光模块，其特征在于，所述硅光芯片包括衬底层及设置在所述衬底层上的介质层，所述介质层中设置有波导层，所述介质层的侧面被暴露于所述凹口，以作为所述硅光芯片用于光纤端面耦合的区域。
  10. 根据权利要求9所述的硅光模块，其特征在于，所述衬底层的部分侧面也被暴露于所述凹口。
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CN114488439A (zh) * 2022-03-07 2022-05-13 青岛海信宽带多媒体技术有限公司 一种光模块
CN114488439B (zh) * 2022-03-07 2023-09-19 青岛海信宽带多媒体技术有限公司 一种光模块
CN117250702A (zh) * 2023-11-20 2023-12-19 之江实验室 一种光电共封装模块及光电共封装方法
CN117250702B (zh) * 2023-11-20 2024-02-23 之江实验室 一种光电共封装模块及光电共封装方法

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