WO2024036450A1 - 填埋式三维扇出封装结构及其制备方法 - Google Patents

填埋式三维扇出封装结构及其制备方法 Download PDF

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Publication number
WO2024036450A1
WO2024036450A1 PCT/CN2022/112590 CN2022112590W WO2024036450A1 WO 2024036450 A1 WO2024036450 A1 WO 2024036450A1 CN 2022112590 W CN2022112590 W CN 2022112590W WO 2024036450 A1 WO2024036450 A1 WO 2024036450A1
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WIPO (PCT)
Prior art keywords
chip
layer
pins
conductive
chip module
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PCT/CN2022/112590
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English (en)
French (fr)
Inventor
郑伟
燕英强
王垚
向迅
崔银花
凌云志
何思亮
胡川
陈志涛
Original Assignee
广东省科学院半导体研究所
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Application filed by 广东省科学院半导体研究所 filed Critical 广东省科学院半导体研究所
Priority to PCT/CN2022/112590 priority Critical patent/WO2024036450A1/zh
Priority to CN202280017505.1A priority patent/CN116918062A/zh
Publication of WO2024036450A1 publication Critical patent/WO2024036450A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor

Definitions

  • the present disclosure relates to the field of semiconductor packaging technology. More specifically, the present disclosure generally relates to a buried three-dimensional fan-out packaging structure and a preparation method thereof.
  • heterogeneous integration is to use advanced packaging technology to integrate multiple electronic components with different functions designed and manufactured individually into higher-level components (such as system-in-package, SiP), providing enhanced functionality overall and improved operating characteristics.
  • higher-level components such as system-in-package, SiP
  • Higher performance, lower latency, smaller size, lighter weight, lower power requirements per function and lower cost are key drivers for the adoption of heterogeneous integration technologies.
  • This technology can continue to increase functional density and reduce the cost required for each function to maintain cost and performance advancements in electronic products and bring advantages to consumers.
  • Heterogeneous integration-based fan-out packaging production requirements challenge lithography and complementary processes, requiring them to perform to a higher standard to support required interconnect and through silicon via (TSV) processing layer requirements .
  • TSV through silicon via
  • equipment costs and reduced productivity or output due to increased complexity are challenges that manufacturers need to address. Pending advances in throughput and process flow, high-end applications will benefit from heterogeneous integration.
  • SMT surface mount mounting
  • This method requires additional wiring equipment on the basis of flip-chip soldering equipment, which increases the cost.
  • it uses traditional wiring-assisted surface packaging methods, which is inconsistent with the development trend of high-density advanced packaging.
  • the preparation method for preparing a buried three-dimensional fan-out packaging structure may include the following steps: providing a multi-sided pin chip, and the pins of the multi-sided pin chip can be distributed at different positions on multiple sides of the multi-sided pin chip; Make a chip module based on a multi-sided pin chip.
  • the pins of the chip module can be located in the same plane; the chip module and other chips are pasted to the temporary carrier board in a flip-chip manner, so that the pins of the chip module and the tubes of other chips
  • the feet can be located in the same plane and connected to the same surface of the temporary carrier board; a plastic sealing layer is formed on the side of the temporary carrier board where the chip module and other chips are pasted, so that the chip module and other chips can be embedded in the plastic sealing layer in; remove the temporary carrier board so that the pins of the chip module and the pins of other chips can be exposed from the first surface of the plastic packaging layer; a rewiring layer can be formed on the first surface of the plastic packaging layer, and the rewiring layer can include A wiring dielectric layer adjacent to the plastic encapsulation layer, a protective dielectric layer disposed on a side of the wiring dielectric layer facing away from the chip module and other chips, and a wiring dielectric layer and a protective dielectric layer embedded in the wiring dielectric layer and connected to the chip.
  • a conductive wiring layer that is electrically connected to the module and another chip may include: lower pins that are electrically connected to pins of the chip module and pins of other chips, and pins that connect the chip module and other chips. interconnection lines of the pins of the chip, first metal pillars respectively extending from the lower pins and the interconnection lines in a direction away from the chip module and other chips and electrically connected to the corresponding lower pins and interconnection lines, and forming an upper pin on an end of the first metal pillar that is away from the chip module and other chips and is electrically connected to the first metal pillar; and an end of the protective dielectric layer in the rewiring layer that is away from the chip module and other chips.
  • Conductive solder balls and/or bumps may be formed on the side, wherein the conductive solder balls and/or bumps may pass through the protective dielectric layer to be electrically connected to the upper pins of the conductive wiring layer.
  • a separate chip module is pre-made based on a multi-faceted pin chip, and the pins of the manufactured chip module are located in the same plane, so that
  • the existing packaging process can be used to realize heterogeneous integrated packaging between the multi-sided pin chip and other chips, without the need to add additional wiring equipment for the lead-out of the pins located at different positions on multiple sides of the multi-sided pin chip. , reduces wiring costs, and does not require the use of traditional wiring-assisted surface packaging methods. Therefore, while meeting the development needs of high-density advanced packaging, it can reduce equipment costs and production costs.
  • manufacturing a chip module based on a multi-sided pin chip may include: providing an insulating frame; forming a first groove and a second groove extending through the insulating frame; and providing a conductive conductive module with a supporting substrate at the bottom.
  • a first adhesive layer can be formed on the top of the conductive layer structure opposite to the supporting substrate; the insulating frame formed with the first groove and the second groove is pasted to the first adhesive layer opposite to the conductive layer structure on one side; remove the portion of the first adhesive layer exposed through the first groove and the second groove to expose the portion of the conductive layer structure opposite to the open ends of the first groove and the second groove; on the conductive layer
  • a metal material layer can be formed on the surface of the part of the structure opposite to the open end of the first groove, and a conductive glue layer can be formed on the side of the metal material layer opposite to the conductive layer structure; the multi-sided pin chip is passed through the conductive glue The layer is pasted in the first groove so that the pins on at least one side of the multi-sided pin chip are electrically connected to the conductive layer structure; and the second groove is filled with a metal material to form a second metal pillar electrically connected to the conductive layer structure. , and a metal pin is formed at the end of the second metal pillar opposite
  • the preparation method for preparing a buried three-dimensional fan-out packaging structure may also include: after making a chip module based on a multi-sided pin chip, providing a heat dissipation frame; fixing the chip module and other chips Place the chip module and other chips in the heat dissipation frame in a flip-chip manner and attach them to the temporary carrier board.
  • a plastic encapsulation layer is formed such that the heat dissipation frame, the chip module and other chips are embedded in the plastic encapsulation layer.
  • fixedly accommodating the chip module and other chips in the heat dissipation frame may include: forming a bottom-closed chip module accommodating groove and a chip accommodating groove on the same side of the heat dissipation frame; A chip module adhesive layer can be provided at the bottom of the chip module accommodating groove, and a chip adhesive layer can be provided at the bottom of the chip module accommodating groove; the chip module is pasted into the chip module accommodating groove through the chip module adhesive layer. , and stick another chip into the chip accommodating groove through the chip adhesive layer, so that the pins of the chip module and the pins of other chips can protrude from the open ends of the chip module accommodating groove and the chip accommodating groove respectively. and are located in the same plane.
  • the heat dissipation frame used in the preparation method for preparing a buried three-dimensional fan-out packaging structure may be a copper frame.
  • making a chip module based on a multi-sided pin chip may include: providing an insulating frame; forming a first groove extending through the insulating frame on the insulating frame; providing a conductive layer structure with a supporting substrate at the bottom; A first adhesive layer is formed on the top of the conductive layer structure opposite to the supporting substrate; the insulating frame formed with the first groove is pasted to the side of the first adhesive layer opposite to the conductive layer structure; on the first A continuous layer of metal material may be formed on the surface of the part of the adhesive layer opposite to the open end of the first groove and on the side wall surface of the first groove, and on the surface of the insulating frame surrounding the open end of the first groove, a continuous layer of metal material may be formed Forming metal pins electrically connected to the metal material layer, the metal pins are used to guide the pins of the multi-sided pin chip to the same plane so that all pins of the chip module are located in the same plane; in the metal material layer and the first A conductive glue layer is
  • making a chip module based on a multi-sided pin chip may include: providing a conductive layer structure with a support substrate at the bottom; forming a first adhesive layer on the top of the conductive layer structure opposite to the support substrate; Forming a conductive glue accommodating groove extending through the first adhesive glue layer in the first adhesive glue layer to expose a portion of the conductive layer structure opposite to the open end of the conductive glue accommodating groove; in the conductive glue accommodating groove Filling the conductive glue to form a conductive glue layer; and pasting the multi-sided pin chip to the conductive glue layer to form a chip stack, wherein the pins on at least one side of the multi-sided pin chip are connected to the conductive layer structure through the conductive glue layer electrical connection; and, the preparation method may include: before forming the rewiring layer on the first surface of the plastic encapsulation layer, pasting the chip stack and additional chips to the temporary carrier in a flip-chip manner, so that the chip stack The pins located on the opposite side to the conductive layer
  • the connecting hole of the plastic sealing layer and the first adhesive layer; and the connecting hole can be filled with metal material to form a guiding metal pillar that is electrically connected to the conductive layer structure, and the guiding metal pillar connects the multi-sided pin chip with the conductive layer Pins of the structural electrical connections are directed to lie in the same plane as pins of the chip stack exposed from the first surface of the molding layer.
  • forming the rewiring layer on the first surface of the plastic encapsulation layer may include: on the first surface of the plastic encapsulation layer, connecting pins of the chip module and other chips exposed on the first surface. At positions corresponding to the pins, metal materials can be used to form lower pins and interconnection lines; a wiring dielectric layer is formed so that the wiring dielectric layer can cover the lower pins, interconnection lines and the first surface; in the wiring dielectric Forming a first via hole at a position of the layer corresponding to the lower pin and the interconnection line, so that the first via hole can extend through the wiring dielectric layer to the lower pin and the interconnection line; filling the first via hole with a metal material hole to form a first metal pillar, so that the first metal pillar can be electrically connected to the lower pin and the interconnection line; use a metal material to form an upper pin at the end of the first metal pillar opposite to the plastic layer, so that the upper tube The pin is electrically connected to the first metal pillar and partially pro
  • the wiring dielectric layer and the protective dielectric layer in the preparation method for preparing a buried three-dimensional fan-out packaging structure may be formed by spin coating or deposition.
  • the conductive solder balls in the preparation method for preparing a buried three-dimensional fan-out packaging structure can be formed by using conductive solder balls or template printing, and the bumps can be formed by evaporation, sputtering, etc. formed by radiation.
  • the grooves, through holes, communication holes and/or openings in the preparation method for preparing the buried three-dimensional fan-out packaging structure may be made by using at least one of photolithography and chemical etching. And formed.
  • the lower pins, interconnect lines and/or upper pins in the preparation method for preparing a buried three-dimensional fan-out packaging structure may be formed of metal materials through electroplating.
  • the metal material used in the preparation method for preparing a buried three-dimensional fan-out packaging structure may include at least one of copper, aluminum, silver, or gold.
  • the buried three-dimensional fan-out packaging structure may include: a plastic encapsulation layer, which may include a first surface and a second surface opposite to the first surface; a chip module embedded in the first surface of the plastic encapsulation layer and another chip, wherein the chip module may include a multi-sided pin chip, the multi-sided pin chip may have pins distributed at different positions on multiple sides, and the pins of the multi-sided pin chip may be guided to the In the same plane, the pins of the chip module and the pins of other chips are located in the same plane as the first surface of the plastic packaging layer; a rewiring layer, which can be disposed on the first surface of the plastic packaging layer, and rewiring
  • the layers may include a wiring dielectric layer adjacent to the molding layer, a protective dielectric layer disposed on a side of the wiring dielectric layer facing away from the chip module and other chips,
  • the chip module may include: a conductive layer structure with a support substrate disposed at the bottom; a first adhesive layer formed on the top of the conductive layer structure opposite to the support substrate; and affixed to the first adhesive layer.
  • the opposite parts of the opening ends of the two grooves may be respectively formed with first adhesive layer through holes and second adhesive layer through holes that penetrate the first adhesive layer; filled in the first adhesive layer through holes;
  • the buried three-dimensional fan-out packaging structure may also include a heat dissipation frame, and the heat dissipation frame, together with the chip module and other chips, may be embedded in the plastic packaging layer, wherein the heat dissipation frame is included in A chip module accommodating groove and a chip accommodating groove with a closed bottom are formed on the same side of the heat dissipation frame.
  • a chip module adhesive layer can be provided at the bottom of the chip module accommodating groove, and a chip module adhesive layer can be provided at the bottom of the chip accommodating groove. There is a chip adhesive layer.
  • the chip module is pasted into the chip module accommodation slot through the chip module adhesive layer. Other chips are pasted into the chip accommodation slot through the chip adhesive layer.
  • the tube of the chip module The pins and pins of other chips may respectively protrude from the chip module accommodating groove and the open ends of the chip accommodating groove and be located in the same plane.
  • the heat dissipation frame in the buried three-dimensional fan-out packaging structure may be a copper frame.
  • the chip module may include: a conductive layer structure with a support substrate disposed at the bottom; a first adhesive layer formed on the top of the conductive layer structure opposite to the support substrate; and affixed to the first adhesive layer.
  • the chip module may include: a chip stack, and the chip stack may include: a conductive layer structure with a support substrate disposed at the bottom; and a first conductive layer structure formed on the top of the conductive layer structure opposite to the support substrate.
  • An adhesive layer in which a conductive glue receiving groove that penetrates the first adhesive glue layer can be formed; a conductive glue layer formed in the conductive glue receiving groove; and a multi-sided pin chip,
  • the multi-sided pin chip can be pasted on the conductive layer structure through the conductive adhesive layer, so that the pins on at least one side of the multi-sided pin chip can be electrically connected to the conductive layer structure, and the multi-sided pin chip is located opposite to the conductive layer structure.
  • the pins on one side can be exposed from the first surface of the plastic encapsulation layer and be located in the same plane as the first surface; guide metal pillars are provided around the chip stack, the guide metal pillars connect the multi-sided pin chip with the conductive layer The pins of the structural electrical connection are guided to be in the same plane as the pins of the chip stack exposed from the first surface of the molding layer, wherein the guiding metal pillars extend from the conductive layer structure and pass through the first adhesive glue formed on The first adhesive layer through hole in the layer and the plastic sealing layer between the first surface and the conductive layer structure.
  • the metal material in the buried three-dimensional fan-out packaging structure may include at least one of copper, aluminum, silver, or gold.
  • the buried three-dimensional fan-out packaging structure prepared according to the preparation method provided by the embodiments of the present disclosure has higher performance, lower delay, smaller size, lighter weight, lower power consumption requirements for each function and more low cost.
  • FIG. 1 is a schematic flow chart illustrating a preparation method for preparing a landfill three-dimensional fan-out packaging structure according to an exemplary embodiment of the present disclosure
  • FIGS. 2a to 2f are illustrative schematic diagrams illustrating the production of a chip module based on a multi-sided pin chip according to an exemplary embodiment of the present disclosure
  • 3a to 3f are illustrative diagrams illustrating providing a heat dissipation frame and embedding the heat dissipation frame together with the chip module and additional chips in a plastic encapsulation layer according to an exemplary embodiment of the present disclosure
  • 4a to 4e are illustrative schematic diagrams illustrating the production of a chip module based on a multi-sided pin chip according to another exemplary embodiment of the present disclosure
  • 5a to 5i are illustrative schematic diagrams illustrating the production of a chip module based on a multi-sided pin chip according to yet another exemplary embodiment of the present disclosure
  • Figure 6 is a schematic flow chart illustrating forming a rewiring layer on the first surface of the plastic encapsulation layer (step S160) in the preparation method shown in Figure 1;
  • FIG. 7a to 7h are illustrative diagrams illustrating the formation of a rewiring layer on the first surface of the plastic encapsulation layer corresponding to various steps of the exemplary embodiment in FIG. 6 according to the present disclosure
  • FIGS. 2 a to 2 f are schematic cross-sectional views illustrating a buried three-dimensional fan-out packaging structure including a chip module fabricated through the process shown in FIGS. 2 a to 2 f according to an exemplary embodiment of the present disclosure
  • FIGS. 9 is a diagram illustrating embedding a heat dissipation frame with a chip module fabricated through the process shown in FIGS. 2a to 2f and additional chips through the process shown in FIGS. 3a to 3f according to an exemplary embodiment of the present disclosure.
  • FIGS. 4a to 4e are schematic cross-sectional views illustrating a buried three-dimensional fan-out packaging structure including a chip module fabricated by the process shown in FIGS. 4a to 4e according to an exemplary embodiment of the present disclosure
  • FIG. 11 is a schematic cross-sectional view illustrating a chip module fabricated by the process shown in FIGS. 5 a to 5 i and a buried three-dimensional fan-out package structure formed by the shown process according to an exemplary embodiment of the present disclosure. .
  • FIG. 1 shows a schematic flow chart of a preparation method for preparing a landfill three-dimensional fan-out packaging structure according to an exemplary embodiment of the present disclosure.
  • a preparation method for preparing a buried three-dimensional fan-out packaging structure may include the following steps:
  • Step S110 Provide a multi-sided pin chip, wherein the pins of the multi-sided pin chip are distributed at different positions on multiple sides of the multi-sided pin chip;
  • Step S120 Make a chip module based on a multi-sided pin chip so that the pins of the chip module are located on the same plane;
  • Step S130 Paste the chip module and other chips to the temporary carrier board in a flip-chip manner, so that the pins of the chip module and the pins of the other chips are located in the same plane and connected to the same surface of the temporary carrier board;
  • Step S140 form a plastic sealing layer on the side of the temporary carrier board where the chip module and other chips are pasted, so that the chip module and other chips are embedded in the plastic sealing layer;
  • Step S150 remove the temporary carrier board so that the pins of the chip module and the pins of other chips are exposed from the first surface of the plastic encapsulation layer;
  • Step S160 forming a rewiring layer on the first surface of the plastic encapsulation layer, where the rewiring layer may include a wiring dielectric layer adjacent to the plastic encapsulation layer, a wiring dielectric layer disposed on the wiring dielectric layer away from the chip module and other chips.
  • first metal pillars extending with interconnection lines and electrically connected to corresponding lower pins and interconnection lines; and upper metal pillars formed on an end of the first metal pillars away from the chip module and other chips and electrically connected to the first metal pillars. pins; and
  • Step S170 forming conductive solder balls and/or bumps on a side of the protective dielectric layer in the rewiring layer away from the chip module and other chips.
  • flip-chip method in this disclosure refers to the flip-chip packaging technology (FC) known in the art, in which the input/output pins or pads of the chip are flipped downward for mounting. operate.
  • FC flip-chip packaging technology
  • a separate chip module is pre-fabricated based on a multi-faceted pin chip, and the pins of the manufactured chip module are Located in the same plane, it is possible to use the existing packaging process to realize heterogeneous integrated packaging between the multi-sided pin chip and other chips, without the need to lead out the pins located at different positions on multiple sides of the multi-sided pin chip.
  • the addition of additional wiring equipment reduces wiring costs and eliminates the need to use traditional wiring-assisted surface packaging methods, thereby meeting the development needs of high-density advanced packaging.
  • manufacturing the chip module 210 based on the multi-sided pin chip may include the following steps: As shown in Figure 2a, an insulating frame 2105 is provided and an extending through insulating frame may be formed on the insulating frame 2105.
  • the first groove 2106 and the second groove 2107 of 2105 as shown in Figure 2b, a conductive layer structure 2103 with a support substrate 2102 at the bottom is provided, wherein a first adhesive layer is formed on the top of the conductive layer structure 2103 opposite to the support substrate 2102.
  • Adhesive layer 2104, and then the insulating frame 2105 formed with the first groove 2106 and the second groove 2107 can be pasted to the side of the first adhesive layer 2104 opposite to the conductive layer structure 2103; as shown in Figure 2c, The portion of the first adhesive layer 2104 exposed through the first groove 2106 and the second groove 2107 is removed to expose the portion of the conductive layer structure 2103 opposite to the open ends of the first groove 2106 and the second groove 2107; as shown in FIG.
  • a metal material layer 2110 is formed on the surface of the portion of the conductive layer structure 2103 opposite to the open end of the first groove 2106, and the second groove 2107 is filled with the metal material to form a third electrically connected to the conductive layer structure 2103.
  • Two metal pillars 2108, and a metal pin 2109 is formed at the end of the second metal pillar 2108 opposite to the conductive layer structure 2103 for guiding the pins of the multi-sided pin chip 2101 to the same plane so that the chip module 210 All the pins are located in the same plane; as shown in Figure 2e, a conductive adhesive layer 2111 is formed on the opposite side of the metal material layer 2110 to the conductive layer structure 2103; and as shown in Figure 2f, the multi-sided pins can be The chip 2101 is pasted in the first groove 2106 through the conductive adhesive layer 2103, so that the pins on at least one side of the multi-sided pin chip 2101 are electrically connected to the conductive layer structure 2103.
  • additional chips in this disclosure may include, but is not limited to, chips.
  • the embedded additional chips also alternatively include other electronic components for heterogeneous integrated packaging, additional fan-out packaging structures already packaged with additional electronic components, etc.
  • the other embedded chip may be a single electronic component or two or more electronic components with the same or different functions.
  • the size, process, function, and/or material of the multiple electronic components may be the same or different depending on the specific application.
  • 3a to 3f show illustrative schematic diagrams of providing a heat dissipation frame and embedding the heat dissipation frame together with the chip module and additional chips in a plastic encapsulation layer in a manufacturing method according to an exemplary embodiment of the present disclosure.
  • the preparation method for preparing a buried three-dimensional fan-out packaging structure also includes manufacturing based on multi-sided pin chips as shown in Figures 2a to 2f
  • the chip module is then provided with a heat dissipation frame 310, and the detailed process is as follows: As shown in Figure 3a, a bottom-sealed chip module accommodation slot 710 and a chip accommodation slot 711 are formed on the same side of the heat dissipation frame 310; as shown in Figure 3b, A chip module adhesive layer 712 is provided at the bottom of the chip module accommodating groove 710, and a chip adhesive layer 712' is provided at the bottom of the chip accommodating groove 711; as shown in Figure 3c, through the chip module adhesive layer 712
  • the chip module 210 is pasted into the chip module receiving slot 710, and the other chip 220 is pasted into the chip receiving slot 711 through the chip adhesive layer 712', so that the pins of the chip module 210 are in contact with the other
  • the pins respectively protrude from the open ends of the chip module accommodating slot 710 and the chip accommodating slot 711 and are located in the same plane; as shown in Figure 3d, the chip module 210 and other chips 220 accommodated in the heat dissipation frame 310 are It is pasted to the temporary carrier board 100 in a flip-chip manner, so that the pins of the chip module 210 and the pins of the other chip 220 are connected to the same surface of the temporary carrier board 100, and the heat dissipation frame 310 is spaced apart from the temporary carrier board 100; as shown in the figure As shown in 3e, a plastic sealing layer 230 is formed on the side of the temporary carrier board 100 where the chip module 210 and another chip 220 are pasted, so that the heat dissipation frame 310, the chip module 210 and the other chips 220 are embedded in the plastic sealing layer 230.
  • the temporary carrier 100 can be subsequently removed to obtain a separate plastic encapsulation layer 230 , so that subsequent encapsulation operations can be performed as described in embodiments of the present disclosure, for example, on the obtained plastic encapsulation layer 230
  • a rewiring layer is formed on the first surface; conductive solder balls and/or bumps are formed on a side of the protective dielectric layer in the rewiring layer away from the chip module and other chips, thereby ultimately forming an embodiment according to the present disclosure.
  • the buried three-dimensional fan-out packaging structure is formed on the first surface; conductive solder balls and/or bumps are formed on a side of the protective dielectric layer in the rewiring layer away from the chip module and other chips, thereby ultimately forming an embodiment according to the present disclosure.
  • the method for preparing a buried three-dimensional fan-out packaging structure may also include embedding a heat dissipation frame in the plastic encapsulation layer. Therefore, in addition to the embodiments shown in Figures 2a to 2f, it has In addition to the advantages, it also has the advantage of improving the thermal conductivity of the plastic sealing layer, thereby improving the heat dissipation efficiency of the entire packaging structure.
  • the heat dissipation frame of the embodiment of the present disclosure may be a copper frame, but it is not limited to the copper frame.
  • the heat dissipation frame can also be made of other metals, or materials with high thermal conductivity or composite materials.
  • the heat dissipation frame in the embodiments of the present disclosure may be more than one heat dissipation frame, and those skilled in the art can perform reasonable design and combination of heat dissipation frames according to actual heat dissipation requirements. .
  • manufacturing the chip module 210' based on the multi-sided pin chip may include: as shown in Figure 4a, providing an insulating frame 2105' and forming an extending through insulating frame on the insulating frame 2105' The first groove 2106' of 2105'; as shown in Figure 4b, provides a conductive layer structure 2103 with a support substrate 2102 at the bottom, wherein a first adhesive layer is formed on the top of the conductive layer structure 2103 opposite to the support substrate 2102 2104, and stick the insulating frame 2105' formed with the first groove 2106' to the side of the first adhesive layer 2104 opposite to the conductive layer structure 2103; as shown in Figure 4c, on the first adhesive layer A continuous metal material layer 2110' is formed on the surface of
  • a metal pin 2109' electrically connected to the metal material layer 2110' is formed on the surface of the open end 2112' of the first groove 2106'.
  • the metal pin 2109' is configured to guide the pins of the multi-sided pin chip 2101 to the same plane so that all the pins of the chip module 210' are located in the same plane; as shown in Figure 4d, a conductive glue layer 2111' is formed on the surface of the portion of the metal material layer 2110' opposite to the open end of the first groove 2106' ; and as shown in Figure 4e, the multi-sided pin chip 2101 is pasted in the first groove 2106' through the conductive adhesive layer 2111', so that the pins on at least one side of the multi-sided pin chip 2101 are in contact with the metal material layer 2110' Electrical connection.
  • the main features of the chip module based on the multi-sided pin chip according to the embodiment shown in FIGS. 4 a to 4 e of the present disclosure are: The difference lies in the interconnection lines made differently.
  • the fabrication of interconnect lines based on the multi-sided pin chip fabrication chip module shown in Figures 4a to 4e does not require the formation of a second groove (for example, the second groove 2107 shown in Figure 2a) on the insulating frame 2105', and also There is no need to remove the adhesive layer at the bottom of the groove (for example, the first adhesive layer 2104 shown in Figure 2b), so it is in addition to one of the advantages of the embodiment shown in Figures 2a to 2f. In addition, it also has simpler manufacturing steps, thereby making the interconnection line manufacturing process with the chip module as shown in Figure 4a to Figure 4e simpler.
  • making a chip module based on a multi-sided pin chip may include: as shown in Figure 5a, providing a conductive layer structure 2103 with a supporting substrate 2102 at the bottom, and in the conductive layer structure 2103 A first adhesive glue layer 2104 is formed on the top opposite to the support substrate 2102; as shown in Figure 5b, a conductive glue receiving groove 2106 extending through the first adhesive glue layer 2104 is formed in the first adhesive glue layer 2104." , to expose the part of the conductive layer structure 2103 opposite to the open end of the conductive glue accommodating groove 2106"; as shown in Figure 5c, the conductive glue is filled in the conductive glue accommodating groove 2106" to form a conductive glue layer 2111"; as shown in Figure 5d, the multi-sided
  • the conductive layer structure 2103 is electrically connected.
  • the preparation method further includes: before forming the rewiring layer on the first surface of the molding layer, as shown in Figure 5e, placing the chip stack 210" and another chip 220 is pasted to the temporary carrier 100 in a flip-chip manner, so that the pins of the chip stack 210′′ on the side opposite to the conductive layer structure 2103 and the pins of the other chip 220 are located in the same plane and with the temporary carrier.
  • a plastic sealing layer 230" is formed on the side of the temporary carrier board 100 where the chip stack 210" and another chip 220 are pasted, so that the chip stack 210" and the other The chip 220 is embedded in the plastic layer 230"; as shown in Figure 5g, the temporary carrier 100 is removed, so that the pins of the chip stack 210" are located on the opposite side to the conductive layer structure 2103 and other The pins of the chip 220 are exposed from the first surface 2301" of the plastic encapsulation layer 230"; as shown in Figure 5h, the chip stack 210" is formed on the first surface 2301" of the plastic encapsulation layer 230" and extends inward through the The plastic encapsulation layer 230" and the communication hole 2107" of the first adhesive layer between the first surface 2301" and the conductive layer structure 2103 of the chip stack 210"; and as shown in Figure 5i, in the communication hole 2107"
  • the metal material is filled to form
  • the guide metal posts 2108" guide the pins of the multi-sided pin chip 2101 that are electrically connected to the conductive layer structure 2103 to the chip stack 210
  • the pins exposed from the first surface 2301" of the plastic sealing layer 230" are located in the same plane.
  • the main features of the chip module based on the multi-sided pin chip according to the embodiment shown in FIGS. 5 a to 5 i of the present disclosure are: The difference lies in the interconnection lines made differently.
  • the chip module based on the multi-sided pin chip shown in Figures 5a to 5i does not need to use an insulating frame (for example, the insulating frame 2105 shown in Figures 2a to 2f), but uses a pre-fabricated chip stack. , further simplifying the production process.
  • the interconnection lines of the multi-sided pin chip 2101 are made on the plastic compound of the plastic layer 230′′. Therefore, in addition to the advantages of the embodiment shown in FIGS. 2a to 2f, the chip module The interconnection line manufacturing process is simpler, thereby making the process of the preparation method of the three-dimensional fan-out packaging structure simpler.
  • FIG. 6 shows a schematic flow chart of forming a rewiring layer on the first surface of the plastic encapsulation layer (step S160 ) in the preparation method shown in FIG. 1 .
  • forming a rewiring layer on the first surface of the plastic encapsulation layer may include the following steps:
  • Step S1601 Use metal material to form lower pins and interconnect lines on the first surface of the plastic encapsulation layer at positions corresponding to the pins of the chip module and the pins of other chips exposed on the first surface;
  • Step S1602 Form a wiring dielectric layer so that the wiring dielectric layer covers the lower pins, interconnect lines and the first surface;
  • Step S1603 forming a first through hole in the wiring dielectric layer at a position corresponding to the lower pin and interconnection line, so that the first through hole extends through the wiring dielectric layer to the lower pin and interconnection line;
  • Step S1604 Fill the first through hole with a metal material to form a first metal pillar so that the first metal pillar is electrically connected to the lower pin and the interconnection line;
  • Step S1605 use a metal material to form an upper pin at the end of the first metal pillar opposite to the plastic encapsulation layer, so that the upper pin is electrically connected to the first metal pillar and partially protrudes above the wiring dielectric layer;
  • Step S1606 forming a protective dielectric layer so that the protective dielectric layer covers the upper pins and the wiring dielectric layer;
  • Step S1607 Form an opening in the protective dielectric layer at a position corresponding to the upper pin, so that the opening extends through the protective dielectric layer and exposes the upper pin.
  • forming the rewiring layer 240 on the first surface 2301 of the plastic encapsulation layer 230 may include: as shown in Figure 7a, on the first surface 2301 of the plastic encapsulation layer 230 and At positions corresponding to the pins of the chip module 210 exposed on the first surface 2301 and the pins of the other chip 220, lower pins 2401 and interconnection lines 2402 are formed with metal materials; as shown in FIG. 7b, a wiring intermediary is formed.
  • a first through hole 2404 is formed at the corresponding position, so that the first through hole 2404 extends through the wiring dielectric layer 2403 to the lower pin 2401 and the interconnection line 2402; as shown in Figure 7d, the first through hole is filled with metal material 2404 to form the first metal pillar 2405, so that the first metal pillar 2405 is electrically connected to the lower pin 2401 and the interconnection line 2402; as shown in Figure 7e, a metal material is used on the first metal pillar 2405 opposite to the plastic layer 230
  • An upper pin 2406 is formed at the end, so that the upper pin 2406 is electrically connected to the first metal pillar 2405 and partially protrudes above the wiring dielectric layer 2403; as shown in Figure 7f, a protective dielectric layer 2407 is formed, so that the protective dielectric layer The electrical layer 2407 covers the upper pin 2406 and the wiring dielectric layer 2403; and as shown in FIG.
  • an opening 2408 is formed in the protective dielectric layer 2407 at a position corresponding to the upper pin 2406, so that the opening 2408 extends through The dielectric layer 2407 is protected and the upper pins 2406 are exposed.
  • FIG. 7h it is also shown that conductive solder balls and/or bumps are subsequently formed on the side of the protective dielectric layer 2407 in the rewiring layer 240 away from the chip module 210 and the other chips 220 (not shown). ( ), in which the conductive solder ball 2409 passes through the protective dielectric layer 2407 and is electrically connected to the upper pin 2406 of the conductive wiring layer.
  • the embodiment in Figure 7h shows conductive solder balls 2409 at openings 2408. It should be noted that, optionally, the conductive solder balls 2409 in the embodiment of Figure 7h may be bumps.
  • FIGS. 8 to 11 are schematic cross-sectional views illustrating a buried three-dimensional fan-out packaging structure including a chip module fabricated according to different exemplary embodiments of fabricating a chip module based on a multi-faceted pin chip of the present disclosure.
  • FIGS. 2a to 2f Steps to make the chip module shows a schematic cross-sectional view of a buried three-dimensional fan-out packaging structure 200 according to an exemplary embodiment of the present disclosure, wherein the buried three-dimensional fan-out packaging structure 200 includes the components shown in FIGS. 2a to 2f Steps to make the chip module.
  • the buried three-dimensional fan-out packaging structure 200 may include: a plastic encapsulation layer 230, which may include a first surface 2301 and a second surface opposite to the first surface; embedded in the plastic encapsulation layer 230
  • the pins of the pin chip 2101 can be guided into the same plane via the metal pins 2109, so that the pins of the chip module 210 and the pins of other chips 220 are located in the same plane as the first surface 2301 of the plastic packaging layer 230; and then Wiring layer 240.
  • the rewiring layer 240 may be disposed on the first surface 2301 of the plastic encapsulation layer 230.
  • the rewiring layer 240 may include a wiring dielectric layer 2403 adjacent to the plastic encapsulation layer 230, and a wiring dielectric layer 2403 disposed away from the chip.
  • the conductive wiring layer may include: lower pins 2401 electrically connected to the pins of the chip module 210 and the pins of another chip 220 respectively, and interconnections connecting the pins of the chip module 210 and the pins of the other chip 220 Line 2402, a first metal pillar 2405 extending from the lower pin 2401 and the interconnection line 2402 respectively in a direction away from the chip module 210 and the other chip 220 and electrically connected to the corresponding lower pin 2401 and the interconnection line 2402, and an upper pin 2406 formed on an end of the first metal pillar 2405 away from the chip module 210 and the other chip 220 and electrically connected to the first metal pillar 2405; and conductive solder balls 2409 and/or bumps (not shown), Conductive sold
  • the upper pins 2406 are electrically connected; and wherein the chip module 210 may include: a conductive layer structure 2103 with a support substrate 2102 at the bottom; a first adhesive layer 2104 formed on the top of the conductive layer structure 2103 opposite to the support substrate 2102 ; An insulating frame 2105 pasted on the side of the first adhesive layer 2104 opposite to the conductive layer structure 2103, wherein the insulating frame 2105 may be formed with first grooves 2106 and second grooves 2107 penetrating the insulating frame 2105, and A first adhesive layer through hole and a second adhesive layer through hole penetrating the first adhesive layer 2103 may be respectively formed on the portion of the first adhesive layer 2103 opposite to the open ends of the first groove 2106 and the second groove 2107.
  • the metal pins 2109 at the opposite end are used to guide the pins of the multi-sided pin chip 2101 to the same plane, so that all the pins of the chip module 210 are located in the same plane.
  • FIG. 9 shows a schematic cross-sectional view of another landfill three-dimensional fan-out packaging structure 300 according to an embodiment of the present disclosure.
  • the buried three-dimensional fan-out packaging structure 300 includes a plastic encapsulation layer structure obtained through the steps shown in Figures 3a to 3f, in which the heat dissipation frame and the chip module made through the steps shown in Figures 2a to 2f are combined. Additional chips are embedded in the plastic encapsulation layer together.
  • the main difference between the buried three-dimensional fan-out packaging structure 300 shown in Figure 9 and the buried three-dimensional fan-out packaging structure 200 shown in Figure 8 is that a heat dissipation frame 310 is also provided, and the heat dissipation frame 310 and The chip module 210 and other chips 220 are embedded in the plastic encapsulation layer 230 . Therefore, for the convenience of description, the same parts of the buried three-dimensional fan-out packaging structure 300 shown in FIG. 9 and the buried three-dimensional fan-out packaging structure 200 shown in FIG. 8 will not be described again here. For details, refer to FIG. The corresponding content and related descriptions shown in 8.
  • the buried three-dimensional fan-out packaging structure 300 may also include a heat dissipation frame 310 , which is embedded in the plastic encapsulation layer 230 together with the chip module 210 and additional chips 220 , wherein the heat dissipation frame 310 includes A bottom-closed chip module accommodating groove 710 and a chip accommodating groove 711 are formed on the same side of the heat dissipation frame 310.
  • a chip module adhesive layer 712 is provided at the bottom of the chip module accommodating groove 710.
  • a chip adhesive layer 712' is provided at the bottom of the groove 711.
  • the chip module is pasted into the chip module receiving groove 710 through the chip module adhesive layer 712. Other chips are pasted through the chip adhesive layer 712'.
  • the pins of the chip module and the pins of other chips protrude from the open ends of the chip module accommodating groove 710 and the chip accommodating groove 711 respectively and are located in the same plane.
  • Figure 10 shows a schematic cross-sectional view of a buried three-dimensional fan-out packaging structure 400 according to yet another embodiment of the present disclosure.
  • the buried three-dimensional fan-out packaging structure 400 includes fabricating through the steps shown in Figures 4a to 4e Made of chip modules.
  • the main differences between the buried three-dimensional fan-out packaging structure 400 in the embodiment shown in Figure 10 and the buried three-dimensional fan-out packaging structure 200 shown in Figure 8 are: in Figure 10
  • the structure of the chip module 210' is different from that of the chip module in FIG. 8 , in that the interconnection lines made in the chip module are different, that is, in the embodiment shown in FIG. 10 , the chip module 410 does not need to be as shown in FIG.
  • a second groove (eg, the second groove 2107 shown in FIG. 2 a ) is made on the insulating frame 2105 of the chip module 210 to form interconnect lines. Therefore, for the convenience of description, the same parts of the buried three-dimensional fan-out packaging structure 400 shown in FIG. 10 and the buried three-dimensional fan-out packaging structure 200 shown in FIG. 8 will not be described again here. For details, refer to FIG. The corresponding content and related descriptions shown in 8.
  • the chip module 410 may include: a conductive layer structure 2103 with a support substrate 2102 at the bottom; a first adhesive layer 2104 formed on the top of the conductive layer structure 2103 opposite to the support substrate 2102; An insulating frame 2105' on an adhesive layer 2104 on the side opposite to the conductive layer structure 2103, wherein the insulating frame 2105' can be formed with a first groove 2106' penetrating the insulating frame 2105'; formed on the first adhesive layer a continuous metal material layer 2110' on the surface of the portion of the gel layer 2104 opposite to the open end 2112' of the first groove 2106' and on the surface of the side wall 2114' of the first groove 2106', and on the insulating frame 2105 'A metal pin 2109' formed on the surface surrounding the open end 2112' of the first groove 2106' and electrically connected to the metal material layer 2110'; on the surface of the metal material layer 2110' opposite to the open end 2112' of the first groove
  • Figure 11 shows a schematic cross-sectional view of a buried three-dimensional fan-out packaging structure 500 according to yet another embodiment of the present disclosure.
  • the buried three-dimensional fan-out packaging structure 500 includes fabricating through the steps shown in Figures 5a to 5i The plastic sealing layer formed.
  • the difference between the buried three-dimensional fan-out packaging structure 500 of the embodiment shown in Figure 11 and the buried three-dimensional fan-out packaging structure 200 shown in Figure 8 is that the three-dimensional fan-out packaging structure shown in Figure 11
  • the arrangement structure of the chip stack and the additional chips embedded in the plastic layer is different from the arrangement of the chip module 210 embedded in the plastic layer and the additional chips in the plastic layer shown in FIG.
  • the interconnect lines made in the chip modules are different.
  • the interconnect lines of the chip stack 210 ′′ (chip module) need not be in an insulating frame (eg, the insulating frame 2105 shown in FIG. 8 ) but rather in the insulating frame 2105 shown in FIG. 11 .
  • the plastic layer 230′′ shown is formed in the plastic material.
  • bumps 2410 are formed in FIG. 11 instead of the conductive solder balls 2409 in FIG. 8 . Therefore, for the convenience of description, the same parts of the buried three-dimensional fan-out packaging structure 500 shown in FIG. 11 and the structure 200 shown in FIG. 8 will not be described again here.
  • the chip module may include: a chip stack 210".
  • the chip stack 210" may include: a conductive layer structure 2103 with a support substrate 2102 at the bottom; and a support substrate 2102 formed on the conductive layer structure 2103.
  • a conductive glue receiving groove 2106" that penetrates the first adhesive layer 2104 may be formed in the first adhesive layer 2104; formed in the conductive glue receiving groove 2106" the conductive adhesive layer 2111" in the conductive adhesive layer 2111”; Can be electrically connected to the conductive layer structure 2103, and the pins of the multi-sided pin chip 2101 on the opposite side to the conductive layer structure 2103 can be exposed from the first surface 2301" of the plastic encapsulation layer 230" and connected to the first surface 2301" Located in the same plane; the guide metal pillars 2108" provided around the chip stack 210" are used to guide the pins of the multi-sided pin chip 2101 that are electrically connected to the conductive layer structure 2103
  • the exposed pins of the first surface 2301" of the plastic encapsulation layer 230" are located in the same plane, wherein the guide metal pillars 2108" extend from the conductive layer structure 2103 and pass through the first bond formed in the first adhesive layer 2104 The glue layer through holes and the plastic sealing layer between the first surface 2301′′ and the conductive layer structure 2103.
  • metal pins may also be formed at the ends opposite to the conductive layer structure 2103 of the guide metal pillars 2108" disposed around the chip stack 210" (FIG. 11 (not shown), the metal pin is electrically connected to the guide metal post 2108" for guiding the pin of the multi-sided pin chip 2101 that is electrically connected to the conductive layer structure 2103 to the plastic package of the chip stack 210"
  • the exposed pins of the first surface 2301" of the layer 230" are located in the same plane.
  • the process of forming conductive solder balls may be alternatively configured as a process of forming bumps; and the process of forming bumps may also be alternatively configured as forming conductive solder balls. ball process.
  • the first through hole, the opening, the first groove, the second groove, the through hole of the adhesive layer, the communication hole, the chip module accommodating groove and the chip accommodating groove are formed.
  • the process or process is non-limiting in this disclosure.
  • at least one of photolithography and chemical etching may be used to form the first through hole, the opening, the first groove, the second groove, the adhesive layer through hole, the communication hole, Chip module receiving slot and chip receiving slot.
  • the manner of forming the grooves or holes is not limited thereto, but may be any method known in the art.
  • the process or process of filling the first through hole, the first groove, the second groove, the adhesive layer through hole, and the communication hole is non-limiting in the present disclosure.
  • the lower pins, the interconnection lines and/or the upper pins may be formed of metal materials through electroplating.
  • the manner of forming the upper/lower pins and interconnection lines is not limited thereto, but may be any method known in the art.
  • the process or process of forming the wiring dielectric layer and the protective dielectric layer is not limited in the present disclosure.
  • the wiring dielectric layer and the protective dielectric layer may be formed by spin coating or deposition.
  • the manner of forming the wiring dielectric layer and the protective dielectric layer is not limited thereto, and may be any method known in the art.
  • the process or process of forming conductive solder balls or forming bumps is not limited in this disclosure.
  • ball placement/stencil printing can be used to form conductive solder balls; and bumps can be formed by evaporation and sputtering.
  • the manner of forming conductive solder balls or forming bumps is not limited thereto, and may be any method known in the art.
  • the selection of metal materials is non-limiting in this disclosure.
  • the metallic material may include at least one of copper, aluminum, silver, or gold.
  • the present disclosure provides a method for preparing a buried three-dimensional fan-out packaging structure.
  • the method includes: providing a multi-sided pin chip, wherein the pins of the multi-sided pin chip are distributed at different positions on multiple sides of the multi-sided pin chip; based on Multi-sided pin chips are used to make chip modules, and the pins of the chip module are located on the same plane; the chip module and other chips are pasted to the temporary carrier board in a flip-chip manner, so that the pins of the chip module and the pins of other chips are located on the same plane.
  • a plastic sealing layer is formed on the side of the temporary carrier board where the chip module and other chips are pasted, so that the chip module and other chips are embedded in the plastic sealing layer; remove the temporary A carrier board, so that the pins of the chip module and the pins of other chips are exposed from the first surface of the plastic encapsulation layer; forming a rewiring layer on the first surface of the plastic encapsulation layer; and a protective dielectric layer in the rewiring layer Conductive solder balls and/or bumps are formed on the side away from the chip module and other chips, wherein the conductive solder balls and/or bumps pass through the protective dielectric layer and are electrically connected to the upper pins of the conductive wiring layer.
  • a separate chip module is pre-made based on a multi-faceted pin chip, and the pins of the manufactured chip module are located in the same plane, so that
  • the existing packaging process can be used to realize heterogeneous integrated packaging between the multi-sided pin chip and other chips, and this method does not require additional equipment for the lead-out of the pins located at different positions on multiple sides of the multi-sided pin chip.
  • Wire equipment reduces the cost of wire bonding and does not require the traditional wire bonding auxiliary surface packaging method, thereby meeting the development needs of high-density advanced packaging.
  • the buried three-dimensional fan-out packaging structure and its preparation method provided by the present disclosure are reproducible and can be used in a variety of industrial applications.
  • the buried three-dimensional fan-out packaging structure and its preparation method provided by the present disclosure can be applied to the field of semiconductor packaging technology.

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Abstract

本申请公开了填埋式三维扇出封装结构及其制备方法。填埋式三维扇出封装结构的制备方法包括：提供多面管脚芯片，其中多面管脚芯片的管脚分布于多面管脚芯片的多个侧面的不同位置；基于多面管脚芯片制作芯片模块，芯片模块的管脚位于同一平面内；将芯片模块和另外的芯片以倒装的方式粘贴至临时载板，使得芯片模块的管脚和另外的芯片的管脚位于同一平面内并且与临时载板的同一表面相连；在临时载板的粘贴有芯片模块和另外的芯片的一侧形成塑封层，使得芯片模块和另外的芯片被嵌埋在塑封层中；去除临时载板，以使芯片模块的管脚和另外的芯片的管脚从塑封层的第一表面露出；在塑封层的第一表面上形成再布线层；以及在再布线层中的保护介电层的背离芯片模块和另外的芯片的一侧形成导电焊球和/或凸点，其中导电焊球和/或凸点穿过保护介电层而与导电布线层的上管脚电连接。

Description

填埋式三维扇出封装结构及其制备方法 技术领域
本公开涉及半导体封装技术领域。更具体地，本公开总体上涉及一种填埋式三维扇出封装结构及其制备方法。
背景技术
本部分提供了与本公开有关的背景信息，但是这些信息并不必然构成现有技术。
随着5G时代的到来，系统处理的数据急剧增多，这就要求电子器件具有更快的处理速度和更高的计算密度。而与之相反，随着芯片工艺走向7纳米、5纳米、3纳米甚至更超前，量子隧穿效应使得晶体管微缩变得十分困难。整个半导体产业都感到物理极限的逼近。在单片集成电路上容纳更多芯片变得越来越困难和昂贵。为此半导体行业寻求各种技术解决方案来提高成本性能，同时通过集成增加更多功能。此时，先进封装技术成为研究者感兴趣的方向。先进封装技术被认为是进一步提高算力密度的有效方法。先进封装不采用传统的封装工艺，比如说一般情况下先进封装不会采用传统封装里最常用的键合线(Bonding Wire)，所以先进封装的集成度非常地高、封装体积很小。另外先进封装里面的互连线非常短，系统性能会提高很多。
近年来，先进封装技术随着芯片与电子器件中高性能、小尺寸、高可靠性以及超低功耗的要求而不断突破发展，同时随着人工智能、自动驾驶、5G网络、物联网等新兴产业的发展而向着系统集成、高速、高频、三维方向发展，特别地，三维(3D)集成先进封装的需求越来越强烈。为此，先进封装技术本身不断创新发展，以应对更加复杂的三维集成需求。当前，高密度硅通孔(TSV)技术/扇出(Fan-Out)封装技术由于其灵活性、高密度、适于系统集成，而成为目前先进封装的核心技术。其中，一个颇具吸引力的方案就是基于异构集成的扇出封装技术。异构集成的基本思想是使用先进的封装技术来将单独设计和制造的多个具有不同功能的电子部件集成到更高级别的组件(例如系统级封装，SiP)中，总体上提供增强的功能和改进的操作特性。更高性能、更低延迟、更小尺寸、更轻重量、更低每个功能的功耗要求和更低成本是采用异构集成技术的关键驱动因素。这种技术能够持续增加功能密度并降低每个功能所需的成本，以保持电子产品的成本和性能进步，为消费者带来优势。
基于异构集成的扇出封装生产需求对光刻和补充工艺提出了挑战，要求它们以更高的标准执行，以支持所需的互连和硅通孔(Through Silicon Via，TSV)处理层要求。在这里，设备成本和由于复杂性增加而降低的生产率或产量是制造商需要解决的挑战。在产量和工艺流程的进步之前，高端应用将从异构集成中获益。
目前在本领域中，将具有位于多个侧面不同位置处的管脚的芯片进行表面贴装(SMT)是一种典型的扇出封装。为了适应目前的倒装焊工艺，需要将不同位置的管脚引导至同一平面。最常用的做法是采用打线的方式。即采用传统的打线工艺，将其他侧面上的管脚用引线引出，使其与某侧的管脚位于同一平面，随后再进行表面封装，将其贴装到封装基板。
这种方法，需要在倒装焊设备的基础上，另外添置打线设备，提高了成本，同时采用传统打线辅助表面封装的方式，与高密度先进封装的发展趋势不符。
因此，存在对于既能够符合高密度先进封装技术的发展趋势，又能够使成本降低的用以实现多面管脚芯片与另外的芯片之间的异构集成封装的方法。
发明内容
本部分提供本公开的一般概要，而不是本公开的全部范围或全部特征的全面披露。
本公开的一方面提供了一种用于制备填埋式三维扇出封装结构的制备方法。所述用于制备填埋式三维扇出封装结构的制备方法可以包括下述步骤：提供多面管脚芯片，多面管脚芯片的管脚可以分布于多面管脚芯片的多个侧面的不同位置；基于多面管脚芯片制作芯片模块，芯片模块的管脚可以位于同一平面内；将芯片模块和另外的芯片以倒装的方式粘贴至临时载板，使得芯片模块的管脚和另外的芯片的管脚可以位于同一平面内并且与临时载板的同一表面相连；在临时载板的粘贴有芯片模块和另外的芯片的一侧形成塑封层，使得芯片模块和另外的芯片可以被嵌埋在塑封层中；去除临时载板，以使芯片模块的管脚和另外的芯片的管脚可以从塑封层的第一表面露出；在塑封层的第一表面上可以形成再布线层，再布线层可以包括与塑封层邻接的布线介电层、设置在布线介电层的背离芯片模块和另外的芯片的一侧的保护介电层、以及嵌设在布线介电层和保护介电层中并且与芯片模块和另外的芯片电连接的导电布线层，其中，导电布线层可以包括：分别与芯片模块的管脚和另外的芯片的管脚电连接的下管脚、连接芯片模块的管脚与另外的芯片的管脚的互连线、沿背离芯片模块和另外的芯片的方向分别从下管脚和互连线延伸并且与相应的下管脚和互连线电连接的第一金属柱、以及形成于第一金属柱的远离芯片模块和另外的芯片的一端并且与第一金属柱电连接的上管脚；以及，在再布线层中的保护介电层的背离芯片模块和另外的芯片的一侧可以形成导电焊球和/或凸点，其中，导电焊球和/或凸点可以穿过保护介电 层而与导电布线层的上管脚电连接。
根据本公开所提供的用于制备填埋式三维扇出封装结构的制备方法，通过基于多面管脚芯片预先制作单独的芯片模块，并且使制成的芯片模块的管脚位于同一平面内，使得能够利用现有封装工艺实现多面管脚芯片与另外的芯片之间的异构集成封装，而不需要为多面管脚芯片的位于多个侧面不同位置处的管脚的引出而另外添置打线设备，降低了打线成本，同时也不需要采用传统打线辅助表面封装的方式，因而在满足了高密度先进封装的发展需求的同时，能够降低设备成本及生产成本。
在一些可选的实施方式中，基于多面管脚芯片制作芯片模块可以包括：提供绝缘框架；绝缘框架上可以形成延伸贯穿绝缘框架的第一槽和第二槽；提供底部设置有支撑基板的导电层结构；在导电层结构的与支撑基板相反的顶部可以形成第一粘结胶层；将形成有第一槽和第二槽的绝缘框架粘贴到第一粘结胶层的与导电层结构相反的一侧上；去除第一粘结胶层的经由第一槽和第二槽而暴露的部分，以露出导电层结构的与第一槽和第二槽的开口端相对的部分；在导电层结构的与第一槽的开口端相对的部分的表面上可以形成金属材料层，并且在金属材料层的与导电层结构相反的一侧上可以形成导电胶层；将多面管脚芯片通过导电胶层而粘贴在第一槽中，使得多面管脚芯片的至少一个侧面上的管脚与导电层结构电连接；以及用金属材料填充第二槽以形成与导电层结构电连接的第二金属柱，并且在第二金属柱的与导电层结构相反的端部处形成金属引脚，以用于将多面管脚芯片的管脚引导至同一平面以使得芯片模块的所有管脚位于同一平面内。
在一些可选的实施方式中，用于制备填埋式三维扇出封装结构的制备方法还可以包括：在基于多面管脚芯片制作芯片模块之后，提供散热框架；将芯片模块和另外的芯片固定地容置于散热框架中，使得芯片模块的管脚和另外的芯片的管脚位于同一平面内；将容置于散热框架中的芯片模块和另外的芯片以倒装的方式粘贴至临时载板，使得芯片模块的管脚和另外的芯片的管脚与临时载板的同一表面相连，而散热框架与临时载板间隔开；以及在临时载板的粘贴有芯片模块和另外的芯片的一侧形成塑封层，使得散热框架与芯片模块和另外的芯片一起被嵌埋在塑封层中。
在一些可选的实施方式中，将芯片模块和另外的芯片固定地容置于散热框架中可以包括：在散热框架的同一侧上形成底部封闭的芯片模块容置槽和芯片容置槽；在芯片模块容置槽的底部可以设置芯片模块粘结胶层，并且在芯片容置槽的底部可以设置芯片粘结胶层；通过芯片模块粘结胶层将芯片模块粘贴至芯片模块容置槽中，并且通过芯片粘结胶层将另外的芯片粘贴至芯片容置槽中，使得芯片模块的管脚和另外的芯片的管脚可以分别从芯片模块容置槽和芯片容置槽的开口端突出并且位于同一平面内。
在一些可选的实施方式中，用于制备填埋式三维扇出封装结构的制备方法中的散热框架可以是铜框架。
在一些可选的实施方式中，基于多面管脚芯片制作芯片模块可以包括：提供绝缘框架；在绝缘框架上可以形成延伸贯穿绝缘框架的第一槽；提供底部设置有支撑基板的导电层结构；在导电层结构的与支撑基板相反的顶部形成第一粘结胶层；将形成有第一槽的绝缘框架粘贴到第一粘结胶层的与导电层结构相反的一侧上；在第一粘结胶层的与第一槽的开口端相对的部分的表面上以及第一槽的侧壁表面上可以形成连续的金属材料层，并且在绝缘框架的围绕第一槽的开口端的表面上可以形成与金属材料层电连接的金属引脚，金属引脚用于将多面管脚芯片的管脚引导至同一平面以使得芯片模块的所有管脚位于同一平面内；在金属材料层的与第一槽的开口端相对的部分的表面上形成导电胶层；以及将多面管脚芯片通过导电胶层而粘贴在第一槽中，使得多面管脚芯片的至少一个侧面上的管脚可以与金属材料层电连接。
在一些可选的实施方式中，基于多面管脚芯片制作芯片模块可以包括：提供底部设置有支撑基板的导电层结构；在导电层结构的与支撑基板相反的顶部形成第一粘结胶层；在第一粘结胶层中形成延伸贯穿第一粘结胶层的导电胶容置槽，以露出导电层结构的与导电胶容置槽的开口端相对的部分；在导电胶容置槽中填充导电胶以形成导电胶层；以及将多面管脚芯片粘贴至导电胶层以形成芯片叠置件，其中，多面管脚芯片的至少一个侧面上的管脚经由导电胶层而与导电层结构电连接；并且，该制备方法可以包括：在塑封层的第一表面上形成再布线层之前，将芯片叠置件和另外的芯片以倒装的方式粘贴至临时载板，使得芯片叠置件的位于与导电层结构相反的一侧的管脚和另外的芯片的管脚位于同一平面内并且与临时载板的同一表面相连；在临时载板的粘贴有芯片叠置件和另外的芯片的一侧可以形成塑封层，使得芯片叠置件和另外的芯片可以被嵌埋在塑封层中；去除临时载板，以使芯片叠置件的位于与导电层结构相反的一侧的管脚和另外的芯片的管脚可以从塑封层的第一表面露出；围绕芯片叠置件在塑封层的第一表面上形成向内延伸穿过位于第一表面与芯片叠置件的导电层结构之间的塑封层和第一粘结胶层的连通孔；以及在该连通孔中可以填充金属材料以形成与导电层结构电连接的引导金属柱，该引导金属柱将多面管脚芯片的与导电层结构电连接的管脚引导成与芯片叠置件的从塑封层的第一表面露出的管脚位于同一平面内。
在一些可选的实施方式中，在塑封层的第一表面上形成再布线层可以包括：在塑封层的第一表面上的与暴露于第一表面的芯片模块的管脚和另外的芯片的管脚相对应的位置处，用金属材料可以形成下管脚和互连线；形成布线介电层， 使得布线介电层可以覆盖下管脚和互连线以及第一表面；在布线介电层的与下管脚和互连线相对应的位置处形成第一通孔，使得第一通孔可以延伸穿过布线介电层直至下管脚和互连线；用金属材料填充第一通孔以形成第一金属柱，使得第一金属柱可以与下管脚和互连线电连接；用金属材料在第一金属柱的与塑封层相反的端部处形成上管脚，使得上管脚与第一金属柱电连接且部分地突出到布线介电层上方；形成保护介电层，使得保护介电层可以覆盖上管脚和布线介电层；以及在保护介电层的对应于上管脚的位置处形成开孔，使得开孔延伸穿过保护介电层并使上管脚露出。
在一些可选的实施方式中，用于制备填埋式三维扇出封装结构的制备方法中的布线介电层和保护介电层可以是通过旋涂或沉积而形成的。
在一些可选的实施方式中，用于制备填埋式三维扇出封装结构的制备方法中的导电焊球可以是采用导电焊球或模板印刷形成的，以及凸点可以是通过蒸镀、溅射形成的。
在一些可选的实施方式中，用于制备填埋式三维扇出封装结构的制备方法中的槽、通孔、连通孔和/或开孔可以是使用光刻和化学蚀刻中的至少一者而形成的。
在一些可选的实施方式中，用于制备填埋式三维扇出封装结构的制备方法中的下管脚、互连线和/或上管脚可以是用金属材料通过电镀方式形成的。
在一些可选的实施方式中，用于制备填埋式三维扇出封装结构的制备方法中的金属材料可以包括铜、铝、银或金中的至少一种。
本公开的另一方面提供了一种根据上述的制备方法制成的填埋式三维扇出封装结构。根据本公开的填埋式三维扇出封装结构可以包括：塑封层，该塑封层可以包括第一表面和与第一表面相反的第二表面；嵌埋在塑封层的第一表面中的芯片模块和另外的芯片，其中，芯片模块可以包括多面管脚芯片，多面管脚芯片可以具有分布于多个侧面的不同位置的管脚，多面管脚芯片的管脚可以经由引导金属柱而被引导至同一平面内，使得芯片模块的管脚和另外的芯片的管脚与塑封层的第一表面位于同一平面内；再布线层，该再布线层可以设置在塑封层的第一表面上，再布线层可以包括与塑封层邻接的布线介电层、设置在布线介电层的背离芯片模块和另外的芯片的一侧的保护介电层、以及嵌设在布线介电层和保护介电层中并且与芯片模块和另外的芯片电连接的导电布线层，其中，导电布线层可以包括：分别与芯片模块的管脚和另外的芯片的管脚电连接的下管脚、连接芯片模块的管脚与另外的芯片的管脚的互连线、沿背离芯片模块和另外的芯片的方向分别从下管脚和互连线延伸并且与相应的下管脚和互连线电连接的第一金属柱、以及形成于第一金属柱的远离芯片模块和另外的芯片的一端并且与第一金属柱电连接的上管脚；以及导电焊球和/或凸点，导电焊球和/或凸点可以设置在再布线层中的保护介电层的背离芯片模块和另外的芯片的一侧并且穿过保护介电层而与导电布线层的上管脚电连接。
在一些可选的实施方式中，芯片模块可以包括：底部设置有支撑基板的导电层结构；形成于导电层结构的与支撑基板相反的顶部的第一粘结胶层；粘贴在第一粘结胶层的与导电层结构相反的一侧上的绝缘框架，其中，绝缘框架可以形成有贯穿绝缘框架的第一槽和第二槽，并且在第一粘结胶层的与第一槽和第二槽的开口端相对的部分可以分别形成有贯穿第一粘结胶层的第一粘结胶层通孔和第二粘结胶层通孔；填充在第一粘结胶层通孔中并且与导电层结构电连接的金属材料层；形成于金属材料层的与导电层结构相反的一侧上的导电胶层；通过导电胶层而粘贴在第一槽中的多面管脚芯片，其中，多面管脚芯片的至少一个侧面上的管脚可以经由导电胶层和金属材料层而与导电层结构电连接；填充在绝缘框架的第二槽和第二粘结胶层通孔中的第二金属柱，以及形成于第二金属柱的与导电层结构相反的端部处的金属引脚，用于将多面管脚芯片的管脚引导至同一平面，以使得芯片模块的所有管脚位于同一平面内。
在一些可选的实施方式中，所述填埋式三维扇出封装结构还可以包括散热框架，散热框架与芯片模块和另外的芯片可以一起被嵌埋在塑封层中，其中，散热框架包括在散热框架的同一侧上形成的底部封闭的芯片模块容置槽和芯片容置槽，在芯片模块容置槽的底部可以设置有芯片模块粘结胶层，并且在芯片容置槽的底部可以设置有芯片粘结胶层，芯片模块通过芯片模块粘结胶层而被粘贴至芯片模块容置槽中，另外的芯片通过芯片粘结胶层而被粘贴至芯片容置槽中，芯片模块的管脚和另外的芯片的管脚可以分别从芯片模块容置槽和芯片容置槽的开口端突出并且位于同一平面内。
在一些可选的实施方式中，填埋式三维扇出封装结构中的散热框架可以是铜框架。
在一些可选的实施方式中，芯片模块可以包括：底部设置有支撑基板的导电层结构；形成于导电层结构的与支撑基板相反的顶部的第一粘结胶层；粘贴在第一粘结胶层上的与导电层结构相反的一侧上的绝缘框架，其中，绝缘框架可以形成有贯穿绝缘框架的第一槽；形成于第一粘结胶层的与第一槽的开口端相对的部分的表面上以及第一槽的侧壁表面上的连续的金属材料层，和在绝缘框架的围绕第一槽的开口端的表面上形成的与金属材料层电连接的金属引脚；在金属材料层的与第一槽的开口端相对的部分的表面上形成的导电胶层；以及多面管脚芯片，多面管脚芯片可以通过导电胶层而粘贴在第一槽中，使得多面管脚芯片的至少一个侧面上的管脚与金属材料层电连接。
在一些可选的实施方式中，芯片模块可以包括：芯片叠置件，芯片叠置件可以包括：底部设置有支撑基板的导电层结构；形成于导电层结构的与支撑基板相反的顶部的第一粘结胶层，在第一粘结胶层中可以形成有贯穿第一粘结胶层的导电胶容置槽；形成于导电胶容置槽中的导电胶层；以及多面管脚芯片，多面管脚芯片可以通过导电胶层而粘贴在导电层结构上，使得多面管脚芯片的至少一个侧面上的管脚可以与导电层结构电连接，且多面管脚芯片的位于与导电层结构相反的一侧上的管脚可以从塑封层的第一表面露出且与第一表面位于同一平面中；围绕芯片叠置件设置的引导金属柱，该引导金属柱将多面管脚芯片的与导电层结构电连接的管脚引导成与芯片叠置件的从塑封层的第一表面露出的管脚位于同一平面内，其中，引导金属柱从导电层结构延伸并穿过形成于第一粘结胶层中的第一粘结胶层通孔以及介于第一表面与导电层结构之间的塑封层。
在一些可选的实施方式中，填埋式三维扇出封装结构中的金属材料可以包括铜、铝、银或金中的至少一种。
根据本公开的实施方式所提供制备方法而制备出的填埋式三维扇出封装结构具有更高性能、更低延迟、更小尺寸、更轻重量、更低每个功能的功耗要求和更低成本。
附图说明
为了更清楚地说明本公开的技术方案，下面将对其中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本公开的某些实现方式，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它相关的附图。
通过以下参照附图的描述，本申请的实施方式的特征和优点将变得更加容易理解，附图并非按比例绘制，并且一些特征被放大或缩小以显示特定部件的细节，在附图中：
图1为示出了根据本公开的示例性实施方式的用于制备填埋式三维扇出封装结构的制备方法的示意性流程图；
图2a至图2f为示出了根据本公开的一示例性实施方式的基于多面管脚芯片制作芯片模块的说明性示意图；
图3a至图3f为示出了根据本公开的示例性实施方式的提供散热框架并将散热框架与芯片模块和另外的芯片一起嵌埋在塑封层中的说明性示意图；
图4a至图4e为示出了根据本公开的另一示例性实施方式的基于多面管脚芯片制作芯片模块的说明性示意图；
图5a至图5i为示出了根据本公开的又一示例性实施方式的基于多面管脚芯片制作芯片模块的说明性示意图；
图6为示出了在图1中所示的制备方法中的在塑封层的第一表面上形成再布线层(步骤S160)的示意性流程图；
图7a至图7h为示出了根据本公开的与图6中的示例性实施方式的各个步骤对应的在塑封层的第一表面上形成再布线层的说明性示意图；
图8为示出了根据本公开的示例性实施方式的包括通过图2a至图2f所示的过程制作的芯片模块的填埋式三维扇出封装结构的示意性截面图；
图9为示出了根据本公开的示例性实施方式的通过图3a至图3f所示的过程将散热框架与通过图2a至图2f所示的过程制作的芯片模块和另外的芯片一起嵌埋在塑封层中的填埋式三维扇出封装结构的示意性截面图；
图10为示出了根据本公开的示例性实施方式的包括通过图4a至图4e所示的过程制作的芯片模块的填埋式三维扇出封装结构的示意性截面图；
图11为示出了根据本公开的示例性实施方式的包括通过图5a至图5i所示的过程制作的芯片模块和所示的过程形成的填埋式三维扇出封装结构的示意性截面图。
具体实施方式
下面将参照附图借助于示例性实施方式对本公开进行详细描述。要注意的是，对本公开的以下详细描述仅仅是出于说明目的，而绝不是对本公开的限制。此外，在各个附图中采用相同的附图标记来表示相同的部件。
还需要说明的是，为了清楚起见，在说明书和附图中并未描述和示出实际的特定实施方式的所有特征，并且，为了避免不必要的细节模糊了本公开关注的技术方案，在附图和说明书中仅描述和示出了与本公开的技术方案密切相关的装置结构，而省略了与本公开的技术内容关系不大的且本领域技术人员已知的其他细节。
接下来，将参照附图对根据本公开的示例性实施方式所提供的用于制备填埋式三维扇出封装结构的制备方法以及根据该制备方法所制备的填埋式三维扇出封装结构进行详细的描述。
首先参照图1。图1示出了根据本公开的示例性实施方式的用于制备填埋式三维扇出封装结构的制备方法的示意性流程图。
根据图示的示例性实施方式，用于制备填埋式三维扇出封装结构的制备方法可以包括以下步骤：
步骤S110，提供多面管脚芯片，其中，该多面管脚芯片的管脚分布于多面管脚芯片的多个侧面的不同位置；
步骤S120，基于多面管脚芯片制作芯片模块，使得芯片模块的管脚位于同一平面内；
步骤S130，将芯片模块和另外的芯片以倒装的方式粘贴至临时载板，使得芯片模块的管脚和另外的芯片的管脚位于同一平面内并且与临时载板的同一表面相连；
步骤S140，在临时载板的粘贴有芯片模块和另外的芯片的一侧形成塑封层，使得芯片模块和另外的芯片被嵌埋在塑封层中；
步骤S150，去除临时载板，以使芯片模块的管脚和另外的芯片的管脚从塑封层的第一表面露出；
步骤S160，在塑封层的第一表面上形成再布线层，其中，该再布线层可以包括与塑封层邻接的布线介电层、设置在布线介电层的背离芯片模块和另外的芯片的一侧的保护介电层、以及嵌设在布线介电层和保护介电层中并且与芯片模块和另外的芯片电连接的导电布线层，并且其中，导电布线层可以包括：分别与芯片模块的管脚和另外的芯片的管脚电连接的下管脚、连接芯片模块的管脚与另外的芯片的管脚的互连线、沿背离芯片模块和另外的芯片的方向分别从下管脚和互连线延伸并且与相应的下管脚和互连线电连接的第一金属柱、以及形成于第一金属柱的远离芯片模块和另外的芯片的一端并且与第一金属柱电连接的上管脚；以及
步骤S170，在再布线层中的保护介电层的背离芯片模块和另外的芯片的一侧形成导电焊球和/或凸点。
应当指出的是，本公开中的用语“倒装的方式”是指本领域公知的倒装芯片封装技术(FC)中的将芯片的输入/输出引脚或焊盘翻转向下进行贴装的操作。在本申请的文件中对此操作的具体内容不再赘述以免混淆对本申请的各个实施方式的描述。
根据本公开的上述示例性实施方式所提供的用于制备填埋式三维扇出封装结构的制备方法，通过基于多面管脚芯片预先制作单独的芯片模块，并且使制成的芯片模块的管脚位于同一平面内，使得能够利用现有封装工艺实现多面管脚芯片与另外的芯片之间的异构集成封装，而不需要为多面管脚芯片的位于多个侧面不同位置处的管脚的引出而另外添置打线设备，降低了打线成本，同时也不需要采用传统打线辅助表面封装的方式，因而满足了高密度先进封装的发展需求。
图2a至图2f示出了根据本公开的一种示例性实施方式的制备方法中基于多面管脚芯片制作芯片模块210的说明性示意图。参照图2a至图2f，根据图示的实施方式，基于多面管脚芯片制作芯片模块210可以包括以下步骤：如图2a所示，提供绝缘框架2105并在绝缘框架2105上可以形成延伸贯穿绝缘框架2105的第一槽2106和第二槽2107；如图2b所示，提供底部设置有支撑基板2102的导电层结构2103，其中，在导电层结构2103的与支撑基板2102相反的顶部形成第一粘结胶层2104，然后可以将形成有第一槽2106和第二槽2107的绝缘框架2105粘贴到第一粘结胶层2104的与导电层结构2103相反的一侧上；如图2c所示，去除第一粘结胶层2104的经由第一槽2106和第二槽2107而暴露的部分，以露出导电层结构2103的与第一槽2106和第二槽2107的开口端相对的部分；如图2d所示，在导电层结构2103的与第一槽2106的开口端相对的部分的表面上形成金属材料层2110，并且用金属材料填充第二槽2107以形成与导电层结构2103电连接的第二金属柱2108，并且在第二金属柱2108的与导电层结构2103相反的端部处形成金属引脚2109，以用于将多面管脚芯片2101的管脚引导至同一平面以使得芯片模块210的所有管脚位于同一平面内；如图2e所示，在金属材料层2110的与导电层结构2103相反的一侧上形成导电胶层2111；以及如图2f所示，可以将多面管脚的芯片2101通过导电胶层2103而粘贴在第一槽2106中，使得多面管脚芯片2101的至少一个侧面上的管脚与导电层结构2103电连接。
应当指出的是，本领域的技术人员可以理解，本公开中的用语“另外的芯片”可以包括但不限于芯片。在一些实施方式中，所嵌入的另外的芯片也替代性地包括用于进行异构集成封装的其他电子部件、已经封装有另外的电子部件的另外的扇出封装结构等。还应当指出的是，根据本公开的实施方式，对于嵌入在填埋式三维扇出封装结构中的所述“另外的芯片”的数量和/或功能不作限制。例如，所嵌入的另外的芯片可以为单个电子部件，也可以为两个以上的相同或不同功能的电子部件。例如，当在填埋式三维扇出封装结构中嵌入有多个电子部件时，根据具体的应用，多个电子部件中的尺寸、制程、功能、和/或材质可以相同或不同。
此外，本领域的技术人员可以理解的是，在本申请所公开上述以及以下的各种实施方式中，所示出的各个步骤和/过程的顺序仅仅出于便于描述的目的，而不应视为是限制性的。虽然已经参照示例性实施方式对本公开进行了描述，但是应当理解，本公开中的各个步骤和/过程的顺序并不局限于文中详细描述和示出的具体实施方式。在不偏离本公开的权利要求书所限定的范围的情况下，本领域技术人员可以对各个步骤和/过程的顺序做出各种改变。
图3a至图3f示出了根据本公开的示例性实施方式的制备方法中提供散热框架并将散热框架与芯片模块和另外的芯片一起嵌埋在塑封层中的说明性示意图。具体地，在图3a至图3f中，根据图示的实施方式，用于制备填埋式三维扇出封装结构的制备方法还包括在如图2a至图2f所示的基于多面管脚芯片制作芯片模块之后提供散热框架310，其详细过程如下：如图3a所示，在散热框架310的同一侧上形成底部封闭的芯片模块容置槽710和芯片容置槽711；如图3b所示，在芯片 模块容置槽710的底部设置芯片模块粘结胶层712，并且在芯片容置槽711的底部设置芯片粘结胶层712’；如图3c所示，通过芯片模块粘结胶层712将芯片模块210粘贴至芯片模块容置槽710中，并且通过芯片粘结胶层712’将另外的芯片220粘贴至芯片容置槽711中，使得芯片模块210的管脚和另外的芯片220的管脚分别从芯片模块容置槽710和芯片容置槽711的开口端突出并且位于同一平面内；如图3d所示，将容置于散热框架310中的芯片模块210和另外的芯片220以倒装的方式粘贴至临时载板100，使得芯片模块210的管脚和另外的芯片220的管脚与临时载板100的同一表面相连，而散热框架310与临时载板100间隔开；如图3e所示，在临时载板100的粘贴有芯片模块210和另外的芯片220的一侧形成塑封层230，使得散热框架310与芯片模块210和另外的芯片220一起被嵌埋在塑封层230中。此外，如图3f所示，随后可以去除临时载板100以得到单独的塑封层230，从而可以按照本公开的实施方式中所述的进行后续的封装操作，例如，在得到的塑封层230的第一表面上形成再布线层；在再布线层中的保护介电层的背离芯片模块和另外的芯片的一侧形成导电焊球和/或凸点等，从而最终形成根据本公开的实施方式的填埋式三维扇出封装结构。
根据本公开的实施方式所提供的制备填埋式三维扇出封装结构的制备方法还可以包括在塑封层中嵌埋散热框架，因而其除了如图2a至图2f中所示的实施方式所具有的优点之外，还具有可以提高塑封层的导热性的优点，从而能够提高整个封装结构的散热效率。
应当指出的是，本公开的实施方式的散热框架可以是铜框架，但是其并不限于铜框架。在一些实施方式中，该散热框架也可以由其他金属、或者高导热性的材料或复合材料制成。
此外，根据本公开的实施例，可以理解的是，本公开的实施方式中的散热框架可以是不止一个散热框架，本领域的技术人员可以根据实际的散热需求进行合理的散热框架的设计和组合。
图4a至图4e为示出了根据本公开的另一示例性实施方式的制备方法中基于多面管脚芯片制作芯片模块210’的说明性示意图。参照图4a至图4e，根据图示的实施方式，基于多面管脚芯片制作芯片模块210’可以包括：如图4a所示，提供绝缘框架2105’并在绝缘框架2105’上形成延伸贯穿绝缘框架2105’的第一槽2106’；如图4b所示，提供底部设置有支撑基板2102的导电层结构2103，其中，在导电层结构2103的与支撑基板2102相反的顶部形成第一粘结胶层2104，并且将形成有第一槽2106’的绝缘框架2105’粘贴到第一粘结胶层2104的与导电层结构2103相反的一侧上；如图4c所示，在第一粘结胶层2104的与第一槽2106’的开口端2112’相对的部分的表面上以及第一槽2106’的侧壁2114’的表面上形成连续的金属材料层2110’，并且在绝缘框架2105’的围绕第一槽2106’的开口端2112’的表面上形成与金属材料层2110’电连接的金属引脚2109’，金属引脚2109’构造成用于将多面管脚芯片2101的管脚引导至同一平面以使得芯片模块210’的所有管脚位于同一平面内；如图4d所示，在金属材料层2110’的与第一槽2106’的开口端相对的部分的表面上形成导电胶层2111’；以及如图4e所示，将多面管脚芯片2101通过导电胶层2111’而粘贴在第一槽2106’中，使得多面管脚芯片2101的至少一个侧面上的管脚与金属材料层2110’电连接。
根据本公开的图4a至图4e中所示的实施方式的基于多面管脚芯片制作芯片模块与图2a至图2f中所示的实施方式中的基于多面管脚芯片制作芯片模块相比主要的区别在于制作的互连线不同。图4a至图4e中所示的基于多面管脚芯片制作芯片模块的互连线制作不需要在绝缘框架2105’上形成第二槽(例如，图2a中所示的第二槽2107)，也无需对该槽底部的粘结胶层(例如，图2b中所示的第一粘结胶层2104)进行去除，因而其除了如图2a至图2f中所示的实施方式所具有的优点之外，还具有更加简洁的制作步骤，从而使具有如图4a至图4e所示的芯片模块的互连线制作工艺更加简捷。
图5a至图5i为示出了根据本公开的又一示例性实施方式的制备方法中基于多面管脚芯片制作芯片模块的说明性示意图。参照图5a至图5i，根据图示的实施方式，基于多面管脚芯片制作芯片模块可以包括：如图5a所示，提供底部设置有支撑基板2102的导电层结构2103，并且在导电层结构2103的与支撑基板2102相反的顶部形成第一粘结胶层2104；如图5b所示，在第一粘结胶层2104中形成延伸贯穿第一粘结胶层2104的导电胶容置槽2106”，以露出导电层结构2103的与导电胶容置槽2106”的开口端相对的部分；如图5c所示，在导电胶容置槽2106”中填充导电胶以形成导电胶层2111”；如图5d所示，将多面管脚芯片2101粘贴至导电胶层2111”以形成芯片叠置件210”，其中，多面管脚芯片2101的至少一个侧面上的管脚经由导电胶层2111”而与导电层结构2103电连接。根据图示的实施方式，制备方法还包括：在塑封层的第一表面上形成再布线层之前，如图5e所示，将芯片叠置件210”和另外的芯片220以倒装的方式粘贴至临时载板100，使得芯片叠置件210”的位于与导电层结构2103相反的一侧的管脚和另外的芯片220的管脚位于同一平面内并且与临时载板100的同一表面相连；如图5f所示，在临时载板100的粘贴有芯片叠置件210”和另外的芯片220的一侧形成塑封层230”，使得芯片叠置件210”和另外的芯片220被嵌埋在塑封层230”中；如图5g所示，去除临时载板100，以使芯片叠置件210”的位于与导电层结构2103相反的一侧的管脚和另外的芯片220的管脚从塑封层230”的第一表面2301”露出；如图5h所示，围绕芯片叠置件210”在塑封层230”的第一表面2301”上形成向内延伸穿过位于第一表面2301”与芯片叠 置件210”的导电层结构2103之间的塑封层230”和第一粘结胶层的连通孔2107”；以及如图5i所示，在连通孔2107”中填充金属材料以形成与导电层结构2103电连接的引导金属柱2108”，该引导金属柱2108”将多面管脚芯片2101的与导电层结构2103电连接的管脚引导成与芯片叠置件210”的从塑封层230”的第一表面2301”露出的管脚位于同一平面内。
根据本公开的图5a至图5i中所示的实施方式的基于多面管脚芯片制作芯片模块与图2a至图2f中所述的实施方式中的基于多面管脚芯片制作芯片模块相比主要的区别在于制作的互连线不同。图5a至图5i中所示的基于多面管脚芯片制作的芯片模块无需采用绝缘框架(例如，图2a至图2f中所示的绝缘框架2105)，而是采用预先制作芯片叠置件的方式，进一步简化了制作工艺。此外，多面管脚芯片2101的互连线在塑封层230”的塑封料上制作而成，因而其除了如图2a至图2f中所示的实施方式所具有的优点之外，还由于芯片模块的互连线制作工艺更加简捷，从而使得三维扇出封装结构的制备方法的工艺更加简单。
图6示出了图1中所示的制备方法中的在塑封层的第一表面上形成再布线层(步骤S160)的示意性流程图。如图6所示，根据本公开的示例性实施方式，在塑封层的第一表面上形成再布线层可以包括以下的步骤：
步骤S1601，在塑封层的第一表面上的与暴露于第一表面的芯片模块的管脚和另外的芯片的管脚相对应的位置处，用金属材料形成下管脚和互连线；
步骤S1602，形成布线介电层，使得布线介电层覆盖下管脚和互连线以及第一表面；
步骤S1603，在布线介电层的与下管脚和互连线相对应的位置处形成第一通孔，使得第一通孔延伸穿过布线介电层直至下管脚和互连线；
步骤S1604，用金属材料填充第一通孔以形成第一金属柱，使得第一金属柱与下管脚和互连线电连接；
步骤S1605，用金属材料在第一金属柱的与塑封层相反的端部处形成上管脚，使得上管脚与第一金属柱电连接且部分地突出到布线介电层上方；
步骤S1606，形成保护介电层，使得保护介电层覆盖上管脚和布线介电层；以及
步骤S1607，在保护介电层的对应于上管脚的位置处形成开孔，使得开孔延伸穿过保护介电层并使上管脚露出。
图7a至图7h为示出了根据本公开的与图6中所示的在塑封层的第一表面上形成再布线层的各个步骤相对应的图示性示意图。参照图7a至图7h，根据本公开的实施方式，在塑封层230的第一表面2301上形成再布线层240可以包括：如图7a所示，在塑封层230的第一表面2301上的与暴露于第一表面2301的芯片模块210的管脚和另外的芯片220的管脚相对应的位置处，用金属材料形成下管脚2401和互连线2402；如图7b所示，形成布线介电层2403，使得布线介电层2403覆盖下管脚2401和互连线2402以及第一表面2301；如图7c所示，在布线介电层2403的与下管脚2401和互连线2402相对应的位置处形成第一通孔2404，使得第一通孔2404延伸穿过布线介电层2403直至下管脚2401和互连线2402；如图7d所示，用金属材料填充第一通孔2404以形成第一金属柱2405，使得第一金属柱2405与下管脚2401和互连线2402电连接；如图7e所示，用金属材料在第一金属柱2405的与塑封层230相反的端部处形成上管脚2406，使得上管脚2406与第一金属柱2405电连接且部分地突出到布线介电层2403上方；如图7f所示，形成保护介电层2407，使得保护介电层2407覆盖上管脚2406和布线介电层2403；以及如图7g所示，在保护介电层2407的对应于上管脚2406的位置处形成开孔2408，使得开孔2408延伸穿过保护介电层2407并使上管脚2406露出。此外，如图7h所示，还示出了随后在再布线层240中的保护介电层2407的背离芯片模块210和另外的芯片220的一侧形成导电焊球和/或凸点(未示出)的说明性示意图，其中导电焊球2409穿过保护介电层2407而与导电布线层的上管脚2406电连接。
此外，图7h中的实施方式示出了在开孔2408处的导电焊球2409。应当指出的是，可选地，图7h中的实施方式中的导电焊球2409可以是凸点。
接下来将参照附图8至图11对利用根据本公开的前述制备方法所制备出的填埋式三维扇出封装结构进行描述。图8至图11为示出了包括根据本公开的不同的基于多面管脚芯片制作芯片模块的示例性实施方式制作的芯片模块的填埋式三维扇出封装结构的示意性截面图。
图8示出了根据本公开的示例性实施方式的填埋式三维扇出封装结构200的示意性截面图，其中，填埋式三维扇出封装结构200包括通过图2a至图2f所示的步骤制作的芯片模块。如图8所示，该填埋式三维扇出封装结构200可以包括：塑封层230，该塑封层230可以包括第一表面2301和与第一表面相反的第二表面；嵌埋在塑封层230的第一表面2301中的芯片模块210和另外的芯片220，其中，芯片模块210可以包括多面管脚芯片2101，多面管脚芯片2101可以具有分布于多个侧面的不同位置的管脚，多面管脚芯片2101的管脚可以经由金属引脚2109而被引导至同一平面内，使得芯片模块210的管脚和另外的芯片220的管脚与塑封层230的第一表面2301位于同一平面内；再布线层240，该再布线层240可以设置在塑封层230的第一表面2301上，再布线层240可以包括与塑封层230邻接的布线介电层2403、设置在布线介 电层2403的背离芯片模块210和另外的芯片220的一侧的保护介电层2407、以及嵌设在布线介电层2403和保护介电层2407中并且与芯片模块210和另外的芯片220电连接的导电布线层，其中，导电布线层可以包括：分别与芯片模块210的管脚和另外的芯片220的管脚电连接的下管脚2401和连接芯片模块210的管脚与另外的芯片220的管脚的互连线2402、沿背离芯片模块210和另外的芯片220的方向分别从下管脚2401和互连线2402延伸并且与相应的下管脚2401和互连线2402电连接的第一金属柱2405、以及形成于第一金属柱2405的远离芯片模块210和另外的芯片220的一端并且与第一金属柱2405电连接的上管脚2406；以及导电焊球2409和/或凸点(未示出)，导电焊球2409和/或凸点可以设置在再布线层240中的保护介电层2407的背离芯片模块210和另外的芯片220的一侧并且穿过保护介电层2407而与导电布线层的上管脚2406电连接；并且其中，芯片模块210可以包括：底部设置有支撑基板2102的导电层结构2103；形成于导电层结构2103的与支撑基板2102相反的顶部的第一粘结胶层2104；粘贴在第一粘结胶层2104的与导电层结构2103相反的一侧上的绝缘框架2105，其中，绝缘框架2105可以形成有贯穿绝缘框架2105的第一槽2106和第二槽2107，并且在第一粘结胶层2103的与第一槽2106和第二槽2107的开口端相对的部分可以分别形成有贯穿第一粘结胶层2103的第一粘结胶层通孔和第二粘结胶层通孔；填充在第一粘结胶层通孔中并且与导电层结构2103电连接的金属材料层2110；形成于金属材料层2110的与导电层结构2103相反的一侧上的导电胶层2111；通过导电胶层2111而粘贴在第一槽2106中的多面管脚芯片2101，其中，多面管脚芯片2101的至少一个侧面上的管脚可以经由导电胶层2110和金属材料层2111而与导电层结构2103电连接；填充在绝缘框架2105的第二槽2107和第二粘结胶层通孔中的第二金属柱2408，以及形成于第二金属柱2408的与导电层结构2103相反的端部处的金属引脚2109，用于将多面管脚芯片2101的管脚引导至同一平面，以使得芯片模块210的所有管脚位于同一平面内。
图9示出了根据本公开的实施方式的另一填埋式三维扇出封装结构300的示意性截面图。填埋式三维扇出封装结构300包括通过图3a至图3f所示的步骤获得的塑封层结构，其中，将散热框架与通过图2a至图2f所示的步骤所制作而成的芯片模块和另外的芯片一起嵌埋在塑封层中。图9中所示的填埋式三维扇出封装结构300与图8中所示的填埋式三维扇出封装结构200的不同之处主要在于：还提供有散热框架310，该散热框架310与芯片模块210和另外的芯片220一起嵌埋在塑封层230中。因此，为了便于描述，图9中所示的填埋式三维扇出封装结构300与图8中所示的填埋式三维扇出封装结构200相同的部分在此不再赘述，具体可参照图8所示的相应内容及相关描述。
如图9所示，填埋式三维扇出封装结构300还可以包括散热框架310，散热框架310与芯片模块210和另外的芯片220一起被嵌埋在塑封层230中，其中，散热框架310包括在散热框架310的同一侧上形成的底部封闭的芯片模块容置槽710和芯片容置槽711，在芯片模块容置槽710的底部设置有芯片模块粘结胶层712，并且在芯片容置槽711的底部设置有芯片粘结胶层712’，芯片模块通过芯片模块粘结胶层712而被粘贴至芯片模块容置槽710中，另外的芯片通过芯片粘结胶层712’而被粘贴至芯片容置槽711中，芯片模块的管脚和另外的芯片的管脚分别从芯片模块容置槽710和芯片容置槽711的开口端突出并且位于同一平面内。
现在参照图10。图10示出了根据本公开的又一实施方式的填埋式三维扇出封装结构400的示意性截面图，填埋式三维扇出封装结构400包括通过图4a至图4e所示的步骤制作而成的芯片模块。应当指出的是，图10中所示的实施方式中的填埋式三维扇出封装结构400与图8中所示的填埋式三维扇出封装结构200的不同之处主要在于：图10中芯片模块210’的结构不同于图8中的芯片模块的结构，其中，芯片模块中制作的互连线不同，即，在图10中所示的实施方式中，芯片模块410不需要如图8中所示的在芯片模块210的绝缘框架2105上制作第二槽(例如，图2a中所示的第二槽2107)来形成互连线。因此，为了便于描述，图10中所示的填埋式三维扇出封装结构400与图8中所示的填埋式三维扇出封装结构200相同的部分在此不再赘述，具体可参照图8所示的相应内容及相关描述。
如图10所示，芯片模块410可以包括：底部设置有支撑基板2102的导电层结构2103；形成于导电层结构2103的与支撑基板2102相反的顶部的第一粘结胶层2104；粘贴在第一粘结胶层2104上的与导电层结构2103相反的一侧上的绝缘框架2105’，其中，绝缘框架2105’可以形成有贯穿绝缘框架2105’的第一槽2106’；形成于第一粘结胶层2104的与第一槽2106’的开口端2112’相对的部分的表面上以及第一槽2106’的侧壁2114’的表面上的连续的金属材料层2110’，和在绝缘框架2105’的围绕第一槽2106’的开口端2112’的表面上形成的与金属材料层2110’电连接的金属引脚2109’；在金属材料层2110’的与第一槽的开口端2112’相对的部分的表面上形成的导电胶层2111’；以及多面管脚芯片2101，多面管脚芯片2101可以通过导电胶层2111’而粘贴在第一槽2106’中，使得多面管脚芯片2101的至少一个侧面上的管脚与金属材料层2110’电连接。
现在参照图11。图11示出了根据本公开的再一实施方式的填埋式三维扇出封装结构500的示意性截面图，填埋式三维扇出封装结构500包括通过图5a至图5i所示的步骤制作而成的塑封层。应当指出的是，图11所示的实施方式的填埋 式三维扇出封装结构500与图8中所示的填埋式三维扇出封装结构200的不同之处在于，图11中示出的嵌埋在塑封层中的芯片叠置件和另外的芯片在塑封层中的布置结构不同于图8中示出的嵌埋在塑封层中的芯片模块210和另外的芯片在塑封层中的布置结构，特别地，芯片模块中制作的互连线不同。在图11中所示的实施方式中，芯片叠置件210”(芯片模块)的互连线不需要在绝缘框架(例如，图8中所示的绝缘框架2105)而是在图11中所示的塑封层230”的塑封料中形成，此外不同之处还有图11中形成凸点2410代替图8中的导电焊球2409。因此，为了便于描述，图11中所示的填埋式三维扇出封装结构500与图8中所示的结构200相同的部分在此不再赘述，具体可参照图8所示的相应内容及相关描述。
如图11所示，芯片模块可以包括：芯片叠置件210”，芯片叠置件210”可以包括：底部设置有支撑基板2102的导电层结构2103；形成于导电层结构2103的与支撑基板2102相反的顶部的第一粘结胶层2104，在第一粘结胶层2104中可以形成有贯穿第一粘结胶层2104的导电胶容置槽2106”；形成于导电胶容置槽2106”中的导电胶层2111”；以及多面管脚芯2101，多面管脚芯片2101可以通过导电胶层2111”而粘贴在导电层结构2103上，使得多面管脚芯片2101的至少一个侧面上的管脚可以与导电层结构2103电连接，且多面管脚芯片2101的位于与导电层结构2103相反的一侧上的管脚可以从塑封层230”的第一表面2301”露出且与第一表面2301”位于同一平面中；围绕芯片叠置件210”设置的引导金属柱2108”，用于将多面管脚芯片2101的与导电层结构2103电连接的管脚引导成与芯片叠置件210”的从塑封层230”的第一表面2301”露出的管脚位于同一平面内，其中，引导金属柱2108”从导电层结构2103延伸并穿过形成于第一粘结胶层2104中的第一粘结胶层通孔以及介于第一表面2301”与导电层结构2103之间的塑封层。
在本公开的上述实施方式中，可选地，在围绕芯片叠置件210”设置的引导金属柱2108”的与导电层结构2103相反的端部处还可以形成有金属引脚(图11中未示出)，该金属引脚与引导金属柱2108”电连接，以用于将多面管脚芯片2101的与导电层结构2103电连接的管脚引导成与芯片叠置件210”的从塑封层230”的第一表面2301”露出的管脚位于同一平面内。
应当指出的是，在本公开示出的一些实施方式中，形成导电焊球的过程可以替代性地设置为形成凸点的过程；以及形成凸点的过程也可以替代性地设置为形成导电焊球的过程。
尽管未示出，但应当指出的是，形成第一通孔、开孔、第一槽、第二槽、粘结胶层的通孔、连通孔、芯片模块容置槽和芯片容置槽的工艺或过程在本公开中是非限制性的。在根据本公开的一些实施方式中，可以使用光刻和化学蚀刻中的至少一者来形成第一通孔、开孔、第一槽、第二槽、粘结胶层通孔、连通孔、芯片模块容置槽和芯片容置槽。然而，形成所述槽或孔的方式不局限于此，而可以是本技术领域已知的任意方法。
填充第一通孔、第一槽、第二槽、粘结胶层通孔以及连通孔的工艺或过程在本公开中是非限制性的。在根据本公开的一些实施方式中，可以用金属材料通过电镀方式形成下管脚、互连线和/或上管脚。然而，形成上/下管脚和互连线的方式不局限于此，而可以是本技术领域已知的任意方法。
另外，应当指出的是，形成布线介电层和保护介电层的工艺或过程在本公开中是非限制性的。在根据本公开的一些实施方式中，可以通过旋涂或沉积而形成布线介电层和保护介电层。然而，形成布线介电层和保护介电层的方式不局限于此，而可以是本技术领域已知的任意方法。
此外，形成导电焊球或形成凸点的工艺或过程在本公开中是非限制性的。在根据本公开的一些实施方式中，可以采用植球/模板印刷而形成导电焊球；以及可以通过蒸镀、溅射而形成凸点。然而，形成导电焊球或形成凸点的方式不局限于此，而可以是本技术领域已知的任意方法。
尽管未示出，但可以理解的是，金属材料的选取在本公开中是非限制性的。在根据本公开的一些实施方式中，金属材料可以包括铜、铝、银或金中的至少一种。
在本公开的上下文中，术语“前”、“后”、“左”、“右”、“上”、“下”、“顶部”和“底部”等方位术语的使用仅仅出于便于描述的目的，而不应视为是限制性的。虽然已经参照示例性实施方式对本公开进行了描述，但是应当理解，本公开并不局限于文中详细描述和示出的具体实施方式。在不偏离本公开的权利要求书所限定的范围的情况下，本领域技术人员可以对示例性实施方式做出各种改变。
在以上对本公开的示例性实施方式的描述中所提及和/或示出的特征可以以相同或类似的方式结合到一个或更多个其他实施方式中，与其他实施方式中的特征相组合或替代其他实施方式中的相应特征。这些经组合或替代所获得的技术方案也应当被视为包括在本公开的保护范围内。
工业实用性
本公开提供一种填埋式三维扇出封装结构的制备方法，该方法包括：提供多面管脚芯片，其中多面管脚芯片的管脚 分布于多面管脚芯片的多个侧面的不同位置；基于多面管脚芯片制作芯片模块，芯片模块的管脚位于同一平面内；将芯片模块和另外的芯片以倒装的方式粘贴至临时载板，使得芯片模块的管脚和另外的芯片的管脚位于同一平面内并且与临时载板的同一表面相连；在临时载板的粘贴有芯片模块和另外的芯片的一侧形成塑封层，使得芯片模块和另外的芯片被嵌埋在塑封层中；去除临时载板，以使芯片模块的管脚和另外的芯片的管脚从塑封层的第一表面露出；在塑封层的第一表面上形成再布线层；以及在再布线层中的保护介电层的背离芯片模块和另外的芯片的一侧形成导电焊球和/或凸点，其中导电焊球和/或凸点穿过保护介电层而与导电布线层的上管脚电连接。根据本公开所提供的用于制备填埋式三维扇出封装结构的制备方法，通过基于多面管脚芯片预先制作单独的芯片模块，并且使制成的芯片模块的管脚位于同一平面内，使得能够利用现有封装工艺实现多面管脚芯片与另外的芯片之间的异构集成封装，而该方法不需要为多面管脚芯片的位于多个侧面不同位置处的管脚的引出而另外添置打线设备，降低了打线成本，同时也不需要采用传统打线辅助表面封装的方式，因而满足了高密度先进封装的发展需求。
此外，可以理解的是，本公开所提供的填埋式三维扇出封装结构及其制备方法是可以重现的，并且可以用在多种工业应用中。例如，本公开所提供的填埋式三维扇出封装结构及其制备方法可以应用于半导体封装技术领域。

Claims (20)

  1. 一种用于制备填埋式三维扇出封装结构的制备方法，其特征在于，所述制备方法包括下述步骤：
    提供多面管脚芯片，其中，所述多面管脚芯片的管脚分布于所述多面管脚芯片的多个侧面的不同位置；
    基于所述多面管脚芯片制作芯片模块，所述芯片模块的管脚位于同一平面内；
    将所述芯片模块和另外的芯片以倒装的方式粘贴至临时载板，使得所述芯片模块的管脚和所述另外的芯片的管脚位于同一平面内并且与所述临时载板的同一表面相连；
    在所述临时载板的粘贴有所述芯片模块和所述另外的芯片的一侧形成塑封层，使得所述芯片模块和所述另外的芯片被嵌埋在所述塑封层中；
    去除所述临时载板，以使所述芯片模块的管脚和所述另外的芯片的管脚从所述塑封层的第一表面露出；
    在所述塑封层的所述第一表面上形成再布线层，所述再布线层包括与所述塑封层邻接的布线介电层、设置在所述布线介电层的背离所述芯片模块和所述另外的芯片的一侧的保护介电层、以及嵌设在所述布线介电层和所述保护介电层中并且与所述芯片模块和所述另外的芯片电连接的导电布线层，其中，所述导电布线层包括：分别与所述芯片模块的管脚和所述另外的芯片的管脚电连接的下管脚、连接所述芯片模块的管脚与所述另外的芯片的管脚的互连线、沿背离所述芯片模块和所述另外的芯片的方向分别从所述下管脚和所述互连线延伸并且与相应的下管脚和互连线电连接的第一金属柱、以及形成于所述第一金属柱的远离所述芯片模块和所述另外的芯片的一端并且与所述第一金属柱电连接的上管脚；以及
    在所述再布线层中的所述保护介电层的背离所述芯片模块和所述另外的芯片的一侧形成导电焊球和/或凸点，其中，所述导电焊球和/或凸点穿过所述保护介电层而与所述导电布线层的所述上管脚电连接。
  2. 根据权利要求1所述的制备方法，其特征在于，基于所述多面管脚芯片制作芯片模块包括：
    提供绝缘框架；
    在所述绝缘框架上形成延伸贯穿所述绝缘框架的第一槽和第二槽；
    提供底部设置有支撑基板的导电层结构；
    在所述导电层结构的与所述支撑基板相反的顶部形成第一粘结胶层；
    将形成有所述第一槽和所述第二槽的所述绝缘框架粘贴到所述第一粘结胶层的与所述导电层结构相反的一侧上；
    去除所述第一粘结胶层的经由所述第一槽和所述第二槽而暴露的部分，以露出所述导电层结构的与所述第一槽和所述第二槽的开口端相对的部分；
    在所述导电层结构的与所述第一槽的开口端相对的部分的表面上形成金属材料层，并且在所述金属材料层的与所述导电层结构相反的一侧上形成导电胶层；
    将所述多面管脚芯片通过所述导电胶层而粘贴在所述第一槽中，使得所述多面管脚芯片的至少一个侧面上的管脚与所述导电层结构电连接；以及
    用金属材料填充所述第二槽以形成与所述导电层结构电连接的第二金属柱，并且在所述第二金属柱的与所述导电层结构相反的端部处形成金属引脚，以用于将所述多面管脚芯片的管脚引导至同一平面以使得所述芯片模块的所有管脚位于同一平面内。
  3. 根据权利要求1或2所述的制备方法，其特征在于，所述方法还包括：
    在基于所述多面管脚芯片制作芯片模块之后，提供散热框架；
    将所述芯片模块和所述另外的芯片固定地容置于所述散热框架中，使得所述芯片模块的管脚和所述另外的芯片的管脚位于同一平面内；
    将容置于所述散热框架中的所述芯片模块和所述另外的芯片以倒装的方式粘贴至临时载板，使得所述芯片模块的管脚和所述另外的芯片的管脚与所述临时载板的同一表面相连，而所述散热框架与所述临时载板间隔开；以及
    在所述临时载板的粘贴有所述芯片模块和所述另外的芯片的一侧形成塑封层，使得所述散热框架与所述芯片模块和所述另外的芯片一起被嵌埋在所述塑封层中。
  4. 根据权利要求3所述的制备方法，其特征在于，将所述芯片模块和所述另外的芯片固定地容置于所述散热框架中包括：
    在所述散热框架的同一侧上形成底部封闭的芯片模块容置槽和芯片容置槽；
    在所述芯片模块容置槽的底部设置芯片模块粘结胶层，并且在所述芯片容置槽的底部设置芯片粘结胶层；
    通过所述芯片模块粘结胶层将所述芯片模块粘贴至所述芯片模块容置槽中，并且通过所述芯片粘结胶层将所述另外的芯片粘贴至所述芯片容置槽中，使得所述芯片模块的管脚和所述另外的芯片的管脚分别从所述芯片模块容置槽和所述 芯片容置槽的开口端突出并且位于同一平面内。
  5. 根据权利要求4所述的制备方法，其特征在于，所述散热框架是铜框架。
  6. 根据权利要求1所述的制备方法，其特征在于，基于所述多面管脚芯片制作芯片模块包括：
    提供绝缘框架；
    在所述绝缘框架上形成延伸贯穿所述绝缘框架的第一槽；
    提供底部设置有支撑基板的导电层结构；
    在所述导电层结构的与所述支撑基板相反的顶部形成第一粘结胶层；
    将形成有所述第一槽的所述绝缘框架粘贴到所述第一粘结胶层的与所述导电层结构相反的一侧上；
    在所述第一粘结胶层的与所述第一槽的开口端相对的部分的表面上以及所述第一槽的侧壁表面上形成连续的金属材料层，并且在所述绝缘框架的围绕所述第一槽的开口端的表面上形成与所述金属材料层电连接的金属引脚，所述金属引脚用于将所述多面管脚芯片的管脚引导至同一平面以使得所述芯片模块的所有管脚位于同一平面内；
    在所述金属材料层的与所述第一槽的开口端相对的部分的表面上形成导电胶层；以及
    将所述多面管脚芯片通过所述导电胶层而粘贴在所述第一槽中，使得所述多面管脚芯片的至少一个侧面上的管脚与所述金属材料层电连接。
  7. 根据权利要求1所述的制备方法，其特征在于，基于所述多面管脚芯片制作芯片模块包括：
    提供底部设置有支撑基板的导电层结构；
    在所述导电层结构的与所述支撑基板相反的顶部形成第一粘结胶层；
    在所述第一粘结胶层中形成延伸贯穿所述第一粘结胶层的导电胶容置槽，以露出所述导电层结构的与所述导电胶容置槽的开口端相对的部分；
    在所述导电胶容置槽中填充导电胶以形成导电胶层；以及
    将所述多面管脚芯片粘贴至所述导电胶层以形成芯片叠置件，其中，所述多面管脚芯片的至少一个侧面上的管脚经由所述导电胶层而与所述导电层结构电连接；
    并且，所述制备方法包括：在所述塑封层的第一表面上形成再布线层之前，
    将所述芯片叠置件和另外的芯片以倒装的方式粘贴至临时载板，使得所述芯片叠置件的位于与所述导电层结构相反的一侧的管脚和所述另外的芯片的管脚位于同一平面内并且与所述临时载板的同一表面相连；
    在所述临时载板的粘贴有所述芯片叠置件和所述另外的芯片的一侧形成塑封层，使得所述芯片叠置件和所述另外的芯片被嵌埋在所述塑封层中；
    去除所述临时载板，以使所述芯片叠置件的位于与所述导电层结构相反的一侧的管脚和所述另外的芯片的管脚从所述塑封层的第一表面露出；
    围绕所述芯片叠置件在所述塑封层的所述第一表面上形成向内延伸穿过位于所述第一表面与所述芯片叠置件的所述导电层结构之间的塑封层和第一粘结胶层的连通孔；以及
    在所述连通孔中填充金属材料以形成与所述导电层结构电连接的引导金属柱，所述引导金属柱将所述多面管脚芯片的与所述导电层结构电连接的管脚引导成与所述芯片叠置件的从所述塑封层的第一表面露出的管脚位于同一平面内。
  8. 根据权利要求1至7中的任一项所述的制备方法，其特征在于，在所述塑封层的所述第一表面上形成再布线层包括：
    在所述塑封层的所述第一表面上的与暴露于所述第一表面的所述芯片模块的管脚和所述另外的芯片的管脚相对应的位置处，用金属材料形成所述下管脚和所述互连线；
    形成所述布线介电层，使得所述布线介电层覆盖所述下管脚和所述互连线以及所述第一表面；
    在所述布线介电层的与所述下管脚和所述互连线相对应的位置处形成第一通孔，使得所述第一通孔延伸穿过所述布线介电层直至所述下管脚和所述互连线；
    用金属材料填充所述第一通孔以形成所述第一金属柱，使得所述第一金属柱与所述下管脚和所述互连线电连接；
    用金属材料在所述第一金属柱的与所述塑封层相反的端部处形成所述上管脚，使得所述上管脚与所述第一金属柱电连接且部分地突出到所述布线介电层上方；
    形成所述保护介电层，使得所述保护介电层覆盖所述上管脚和所述布线介电层；以及
    在所述保护介电层的对应于所述上管脚的位置处形成开孔，使得所述开孔延伸穿过所述保护介电层并使所述上管脚露出。
  9. 根据权利要求1至8中的任一项所述的制备方法，其特征在于，所述布线介电层和所述保护介电层是通过旋涂或沉积而形成的。
  10. 根据权利要求1至9中的任一项所述的制备方法，其特征在于，所述导电焊球是采用导电焊球或模板印刷形成的，以及所述凸点是通过蒸镀、溅射形成的。
  11. 根据权利要求8所述的制备方法，其特征在于，所述槽、所述通孔、所述连通孔和/或所述开孔是使用光刻和化学蚀刻中的至少一者而形成的。
  12. 根据权利要求8所述的制备方法，其特征在于，所述下管脚、所述互连线和/或所述上管脚是用金属材料通过电镀方式形成的。
  13. 根据权利要求12所述的制备方法，其特征在于，所述金属材料包括铜、铝、银或金中的至少一种。
  14. 一种根据权利要求1至13中的任一项所述的制备方法制成的填埋式三维扇出封装结构，其特征在于，所述填埋式三维扇出封装结构包括：
    塑封层，所述塑封层包括第一表面和与所述第一表面相反的第二表面；
    嵌埋在所述塑封层的第一表面中的芯片模块和另外的芯片，其中，所述芯片模块包括多面管脚芯片，所述多面管脚芯片具有分布于多个侧面的不同位置的管脚，所述多面管脚芯片的管脚经由引导金属柱而被引导至同一平面内，使得所述芯片模块的管脚和所述另外的芯片的管脚与所述塑封层的第一表面位于同一平面内；
    再布线层，所述再布线层设置在所述塑封层的所述第一表面上，所述再布线层包括与所述塑封层邻接的布线介电层、设置在所述布线介电层的背离所述芯片模块和所述另外的芯片的一侧的保护介电层、以及嵌设在所述布线介电层和所述保护介电层中并且与所述芯片模块和所述另外的芯片电连接的导电布线层，其中，所述导电布线层包括：分别与所述芯片模块的管脚和所述另外的芯片的管脚电连接的下管脚、连接所述芯片模块的管脚与所述另外的芯片的管脚的互连线、沿背离所述芯片模块和所述另外的芯片的方向分别从所述下管脚和所述互连线延伸并且与相应的下管脚和互连线电连接的第一金属柱、以及形成于所述第一金属柱的远离所述芯片模块和所述另外的芯片的一端并且与所述第一金属柱电连接的上管脚；以及
    导电焊球和/或凸点，所述导电焊球和/或凸点设置在所述再布线层中的所述保护介电层的背离所述芯片模块和所述另外的芯片的一侧并且穿过所述保护介电层而与所述导电布线层的所述上管脚电连接。
  15. 根据权利要求14所述的填埋式三维扇出封装结构，其特征在于，所述芯片模块包括：
    底部设置有支撑基板的导电层结构；
    形成于所述导电层结构的与所述支撑基板相反的顶部的第一粘结胶层；
    粘贴在所述第一粘结胶层的与所述导电层结构相反的一侧上的绝缘框架，其中，所述绝缘框架形成有贯穿所述绝缘框架的第一槽和第二槽，并且在所述第一粘结胶层的与所述第一槽和所述第二槽的开口端相对的部分分别形成有贯穿所述第一粘结胶层的第一粘结胶层通孔和第二粘结胶层通孔；
    填充在所述第一粘结胶层通孔中并且与所述导电层结构电连接的金属材料层；
    形成于所述金属材料层的与所述导电层结构相反的一侧上的导电胶层；
    通过所述导电胶层而粘贴在所述第一槽中的所述多面管脚芯片，其中，所述多面管脚芯片的至少一个侧面上的管脚经由所述导电胶层和所述金属材料层而与所述导电层结构电连接；
    填充在所述绝缘框架的所述第二槽和所述第二粘结胶层通孔中的第二金属柱，以及形成于所述第二金属柱的与所述导电层结构相反的端部处的金属引脚，用于将所述多面管脚芯片的管脚引导至同一平面，以使得所述芯片模块的所有管脚位于同一平面内。
  16. 根据权利要求14或15所述的填埋式三维扇出封装结构，其特征在于，所述填埋式三维扇出封装结构还包括散热框架，所述散热框架与所述芯片模块和所述另外的芯片一起被嵌埋在所述塑封层中，其中，
    所述散热框架包括在所述散热框架的同一侧上形成的底部封闭的芯片模块容置槽和芯片容置槽，在所述芯片模块容置槽的底部设置有芯片模块粘结胶层，并且在所述芯片容置槽的底部设置有芯片粘结胶层，所述芯片模块通过所述芯片模块粘结胶层而被粘贴至所述芯片模块容置槽中，所述另外的芯片通过所述芯片粘结胶层而被粘贴至所述芯片容置槽中，所述芯片模块的管脚和所述另外的芯片的管脚分别从所述芯片模块容置槽和所述芯片容置槽的开口端突出并且位于同一平面内。
  17. 根据权利要求16所述的填埋式三维扇出封装结构，其特征在于，所述散热框架是铜框架。
  18. 根据权利要求14所述的填埋式三维扇出封装结构，其特征在于，所述芯片模块包括：
    底部设置有支撑基板的导电层结构；
    形成于所述导电层结构的与所述支撑基板相反的顶部的第一粘结胶层；
    粘贴在所述第一粘结胶层上的与所述导电层结构相反的一侧上的绝缘框架，其中，所述绝缘框架形成有贯穿所述绝缘框架的第一槽；
    形成于所述第一粘结胶层的与所述第一槽的开口端相对的部分的表面上以及所述第一槽的侧壁表面上的连续的金属材料层，和在所述绝缘框架的围绕所述第一槽的开口端的表面上形成的与所述金属材料层电连接的金属引脚；
    在所述金属材料层的与所述第一槽的开口端相对的部分的表面上形成的导电胶层；以及
    所述多面管脚芯片，所述多面管脚芯片通过所述导电胶层上而粘贴在所述第一槽中，使得所述多面管脚芯片的至少一个侧面上的管脚与所述金属材料层电连接。
  19. 根据权利要求14所述的填埋式三维扇出封装结构，其特征在于，所述芯片模块包括：
    芯片叠置件，所述芯片叠置件包括：
    底部设置有支撑基板的导电层结构；
    形成于所述导电层结构的与所述支撑基板相反的顶部的第一粘结胶层，在所述第一粘结胶层中形成有贯穿所述第一粘结胶层的导电胶容置槽；
    形成于所述导电胶容置槽中的导电胶层；以及
    所述多面管脚芯片，所述多面管脚芯片通过所述导电胶层而粘贴在所述导电层结构上，使得所述多面管脚芯片的至少一个侧面上的管脚与所述导电层结构电连接，且所述多面管脚芯片的位于与所述导电层结构相反的一侧上的管脚从所述塑封层的第一表面露出且与所述第一表面位于同一平面中；
    围绕所述芯片叠置件设置的引导金属柱，所述引导金属柱将所述多面管脚芯片的与所述导电层结构电连接的管脚引导成与所述芯片叠置件的从所述塑封层的第一表面露出的管脚位于同一平面内，其中，所述引导金属柱从所述导电层结构延伸并穿过形成于所述第一粘结胶层中的第一粘结胶层通孔以及介于所述第一表面与所述导电层结构之间的塑封层。
  20. 根据权利要求15至18中的任一项所述的填埋式三维扇出封装结构，其特征在于，所述金属材料包括铜、铝、银或金中的至少一种。
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