CN111128990A - 集成电路封装件 - Google Patents

集成电路封装件 Download PDF

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Publication number
CN111128990A
CN111128990A CN201911052148.9A CN201911052148A CN111128990A CN 111128990 A CN111128990 A CN 111128990A CN 201911052148 A CN201911052148 A CN 201911052148A CN 111128990 A CN111128990 A CN 111128990A
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China
Prior art keywords
package
die
layer
protective layer
redistribution
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Pending
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CN201911052148.9A
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English (en)
Inventor
郭丰维
周淳朴
陈硕懋
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN111128990A publication Critical patent/CN111128990A/zh
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Abstract

一种将光子管芯(oDie)和电子管芯(eDie)集成的集成电路封装件。更确切地说，集成电路封装件可包含以通信方式耦合到光子管芯和/或电子管芯中的至少一个的多个重分布层，其中模塑材料至少部分地包围光子管芯和/或电子管芯中的至少一个。

Description

集成电路封装件
技术领域
本发明实施例是涉及集成电路封装件及其制作方法。
背景技术
常规封装技术大致上包含分割晶片且随后将单独管芯封装在经切割的晶片上。由于在已切割晶片之后封装单独管芯，因此封装件大小往往会显著大于管芯大小。相比之下，在标准晶片级封装技术中，在使晶片的部分静止时封装集成电路，且随后切割晶片。因此，所得封装件通常与管芯自身大小相同。然而，由于可容纳于有限封装件占据面积中的外部接触件的数量有限，因此有封装件较小的优点也有不利方面。在一些情况下，这可以在考虑需要大量接触件的复杂半导体器件时变成明显的限制。
发明内容
在一实施例中，一种集成电路封装件，包括：光子管芯(oDie)，包含至少一个光学组件；电子管芯(eDie)；衬底，多个重分布层，所述多个重分布层通信耦合到所述光子管芯和/或所述电子管芯中的至少一个，其中所述衬底包括模塑部分，所述模塑部分至少部分地包围所述光子管芯和/或所述电子管芯中的所述至少一个；以及接续段，将所述光子管芯和/或电子管芯中的所述至少一个电耦合到至少一个重分布层，所述至少一个重分布层定位成邻近于所述集成电路封装件的最上层。
附图说明
当结合附图阅读时，从以下详细描述最好地理解本公开的各方面。应注意，根据业界中的标准惯例，各个特征未按比例绘制。实际上，为了论述清楚起见，可以任意增大或减小各种特征的尺寸。
图1描绘根据一些实施例的光子封装件的第一实例的横截面图。
图2A到图2B描绘根据一些实施例的光子封装件的第二实例的横截面图。
图3A到图3B描绘根据一些实施例的光子封装件的第三实例的横截面图。
图4A到图4B描绘根据一些实施例的光子封装件的第四实例的横截面图。
图5A到图5B描绘根据一些实施例的光子封装件的第五实例的横截面图。
图6描绘根据一些实施例的并入光子封装件的系统。
图7描绘根据一些实施例的用于形成光子封装件的方法的流程图。
图8A到图8P说明根据一些实施例的用于制造光子封装件的工艺的步骤。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同实施例或实例。下文描述组件和布置的特定实例来简化本公开。当然，这些只是实例且并不意欲为限制性的。举例来说，在以下描述中，第一特征在第二特征上方或上的形成可包括第一特征和第二特征直接接触地形成的实施例，且还可包括额外特征可在第一特征与第二特征之间形成以使得第一特征和第二特征可不直接接触的实施例。另外，本公开可在各个实例中重复附图标号和/或字母。这种重复是出于简单和清晰的目的，且本身并不指示所论述的各种实施例和/或配置之间的关系。
另外，在本文中为易于描述，可使用例如“在……下”、“在……下方”、“下部”、“在……上方”、“上部”以及类似术语的空间相对术语来描述如图中所说明的一个元件或特征与另一元件或特征的关系。除了图中所描绘的定向之外，空间相对术语意图涵盖器件在使用或操作中的不同定向。设备可以其它方式定向(旋转90度或处于其它定向)，且本文中所使用的空间相对描述词可同样相应地进行解释。
当将例如激光器、光学调节器、光学检测器以及光学开关的光学组件并入到封装电子模块中时，常规封装技术和标准晶片级(wafer level)封装技术通常可导致低密度引脚计数、更大的外观尺寸以及更高的成本。举例来说，集成电路可经由微凸块附接到例如硅插入件的插入件且随后经由导电胶连接到印刷电路板。当光纤阵列位于插入件上时，来自与光纤阵列介接的集成电路的连接、电源和/或数据，通过插入件内的一或多个轨线和导线接合的连接，从微凸块布线到位于PCB处的外部衬垫。当导线接合可具成本效益和为灵活的时，导线接合技术可遭受安全性问题且通常导致封装件大小更大。
包含一或多个光学模块的多芯片模块可包含与光学模块通信的集成电路。在一些情况下，可采用倒装芯片封装技术，使得集成电路和光学模块以通信方式彼此耦合且利用一或多个凸块附接到衬底。在一些情况下，插入件可驻留在集成电路与光学模块之间，使得连接(例如耦合到集成电路和/或光学模块且耦合到衬底的连接)可散布到更宽的间距且/或将连接重布线到不同的连接。在一些情况下，插入件可利用硅穿孔(through-siliconvia；TSV)来将插入件连接到衬底，同时集成电路和光学模块可利用现有连接方法(例如凸块连接)附接到插入件。在一些情况下，插入件可为用于将光从例如激光器的光源导向和/或导引到封装件中的另一位置的光子插入件。这类多芯片模块通常具有更大的外观尺寸、更高的成本，且通常具有较低的密度和引脚计数。
本文中所描述的实施例公开了将光子管芯(photonic die；oDie)和电子管芯(electronic die；eDie)集成到一个封装件中的先进封装技术。在一些情况下，除了oDie和eDie之外的组件也可包含于封装件中。举例来说，封装件可包含oDie、eDie以及形成内连线封装件的开关ASIC。eDie的组件可包含但不限于以下中的至少一个：一或多个串行器/并行器(串行并行器(serde))、一或多个收发信机、时钟电路以及控制逻辑和电路。eDie与开关ASIC的集成可以缩短串行并行器与开关逻辑之间的距离，这反过来可以减小串行并行器的大小和功率消耗。在一些情况下，硅穿孔可用于衬底中以电连接各种组件。在本文中所描述的其它实施例中，oDie可与一种或多种额外的光子组件集成于单个集成电路封装件中。eDie随后可经由一或多个凸块附接到集成电路封装件。
如本文中所描述，封装件可利用集成扇出型(Integrated Fan-Out；InFO)技术来将可包含光子集成电路应用的多个管芯集成到集成电路封装件封装件(又称为晶片级封装件)中。因此，可获得能够操控高引脚计数(例如具有高引脚和组件密度)同时具有小外观尺寸的先进封装件。由于可利用InFO技术，因此这种封装件可高度集成且可比传统封装技术制造成本更低。先进的封装件可适用于高速电路。
至少由于扇出型封装利用单独管芯且将其包埋于例如环氧树脂模塑化合物或其它材料的材料中以及针对额外I/O连接点在每一管芯之间分配空间，InFO封装技术不同于其它封装技术。因此，可避免使用硅基板面来容纳更高引脚计数。此外，重分布层可用以将一些I/O连接布线/重布线到边缘区域，进一步增加到更高封装件引脚计数密度和接触件利用率。
图1描绘根据本公开的一些实施例的第一封装件104的横截面图。更确切地说，第一封装件可利用集成电路封装技术(如InFO封装技术)且提供耦合到光学内连线117的光纤112，其中光学内连线117可特定地配置成接收光且将所接收光提供到oDie 116以用于进一步处理。也就是说，当经由光纤在第一封装件104处接收光时，第一封装件104配置成将光转换成电信号。一或多个光学内连线117可接收光，且经由光学波导将光导向或导引到定位于oDie 116处的一或多个检测器。oDie 116的一或多个检测器可检测光且随后将光转换成一或多个对应的电信号。一或多个电信号可流动通过重分布层120到例如eDie 108，其中eDie108可进一步处理所接收的一或多个电信号。oDie 116可经由重分布层120和一或多个凸块(例如oDie 116的微凸块124和eDie 108的微凸块128)耦合到eDie 108。eDie 108可处理一或多个电信号且经由重分布层120和硅穿孔136将一或多个处理过的电信号提供到凸块132以用于连接到另一管芯的印刷电路板。
第一封装件104可包含一或多个部分。举例来说，第一封装件104可包含eDie 108、光纤112以及oDie封装部分140。oDie封装部分140可包含第一连接部分144、一或多个重分布层120、一或多个oDie 116、一或多个硅层148、一或多个硅穿孔136以及一或多个第二连接部分152。一个或多个第一连接部分144可包含一或多个如先前所论述的凸块124；一或多个第二连接部分152可包含一或多个凸块132。eDie 108、oDie封装部分140以及光纤112可封装于保护材料156中，其中可暴露一或多个第二连接部分152中的一或多个凸块132以用于连接到印刷电路板、其它管芯和/或外部连接。举例来说，第一封装件104可耦合到日志和/或存储器。
图2A描绘根据本公开的实施例的第二封装件200的横截面图。图2B描绘图2A中所描绘的第二封装件200的放大部分。类似于第一封装件104，第二封装件200可利用集成电路封装技术，如InFO封装技术。第二封装件可包含衬底204。衬底204可包含模具材料、硅材料和/或其它基本上绝缘的或半导体材料。封装件200可包含形成于衬底204顶部上、直接接触衬底204且/或布置在衬底204上的保护层212。保护层212可包含聚酰亚胺和/或聚苯并恶唑材料。保护层212可为在封装之前用作保护层或“缓冲涂层”或用作重分布层252的应力消除涂层。在形成保护层212之前，一或多个重分布层208可形成于衬底204顶部上、直接接触衬底204且/或布置在衬底204的至少一部分上。另一保护层216可形成于保护层212和重分布层252的至少一部分上。在一些实施例中，一或多个通孔218可形成于保护层216和/或保护层212内。在一些情况下，第一通孔可在形成第一保护层212之后形成，而第二通孔可在形成第二保护层216之后形成。或者或另外，第一通孔和/或第二通孔可在已形成保护层212和保护层216之后形成。举例来说，可移除保护层216的一或多个部分；例如，可蚀刻、钻孔所述一或多个部分和/或使其曝露于光，以在保护层212和/或保护层216中形成第一孔。绝缘材料随后可置于第一孔内以加衬所述孔的侧边。最终，导电材料可置于所述孔中，由此形成一或多个通孔218。
封装件200可包含一或多个重分布层220，所述重分布层形成于保护层216上、形成于保护层216顶部上、直接接触保护层216或以其它方式布置在保护层216上。在一实施例中，保护层224可形成于保护层216上、形成于保护层216顶部上、直接接触保护层216或以其它方式布置在保护层216上。可移除保护层224的一或多个部分。举例来说，可将所述一或多个部分蚀刻、钻孔、曝露于光等，且由此在保护层224中形成孔。随后，重分布层220可形成于重分布层220的一或多个孔内。最后，一或多个凸块下金属化层228可形成于重分布层220上；所述一或多个凸块下金属化层228可配置成接收焊球和/或连接件232A到连接件232C，以形成例如球栅阵列。
如先前所论述，封装件200可包含重分布层208；重分布层208可提供经由介接部分276从光学管芯(optical die；oDie)240和/或一或多个eDie 236中的一或多个到连接件232A到连接件232C中的一或多个的信号路径。连接部分244可包含重分布层286A和/或重分布层286B、一或多个衬垫284A和衬垫284B、一或多个导电部分270以及一或多个绝缘部分282中的一或多个。集成电路封装穿孔(through integrated circuit package via)或绝缘体穿孔(through insulator via；TIV)272可形成于衬底204中。举例来说，TIV 272可将重分布层208耦合到背侧重分布层246。举例来说，背侧重分布层246可将重分布层208耦合到一或多个重分布层252。因此，可形成将重分布层252耦合到一或多个铜重分布层286A和/或铜重分布层286B的通孔248。重分布层268A和/或重分布层286B可形成于衬垫284A和/或衬垫284B正上方或以其它方式布置在衬垫284A和/或衬垫284B上。衬垫284A和/或衬垫284B可布置在包含绝缘材料的绝缘部分282内；因此，衬垫284A和/或衬垫284B中的一或多个可经由导电部分270耦合到oDie和/或eDie 236。
如先前所论述，oDie 240可耦合到光学内连线264，所述光学内连线可配置成接收来自光纤260的光和/或将所述光传送到oDie 240的检测器部分。因此，开口可存在于封装件200的光纤阵列接收侧。oDie 240可将光转换成一或多个电信号并将所述一或多个电信号传输或以其它方式提供到eDie 236和/或外部连接，例如连接件232A到连接件232C中的一或多个。可通过封装件200经由重分布层、一或多个通孔、一或多个TIV、一或多个衬垫284A和/或衬垫284B以及一或多个导电部分270中的一或多个传输一或多个电信号。
根据本公开的一些实施例，oDie 240和eDie 236可驻留在封装件200内。举例来说，空腔、孔或其它部分可形成或以其它方式存在于衬底204中。一或多个oDie 240和/或一或多个eDie 236中的每一个可驻留在例如横截面图中的两侧上的TIV之间。此外，衬底材料204可包含环氧基或另外为环氧基。在一些实施例中，oDie 240和/或eDie 236可直接连接到导电部分270中的一或多个或以其它方式布置在所述导电部分中的一或多个上。
图3A描绘根据本公开的实施例的第三封装件300的横截面图。图3B描绘图3A中所描绘的第三封装件300的放大部分。类似于第一封装件104和第二封装件200，第三封装件300可利用集成电路封装技术。第三封装件可包含衬底304。衬底304可包含模具材料、硅材料和/或其它基本上绝缘的或半导体材料。封装件300可包含形成于衬底304顶部上、直接接触衬底304且/或布置在衬底304上的保护层312。保护层312可包含聚酰亚胺和/或聚苯并恶唑材料。保护层312可为在封装之前用作保护层或“缓冲涂层”或用作重分布层352的应力消除涂层。在形成保护层312之前，一或多个重分布层308可形成于衬底304顶部上、直接接触衬底304且/或布置在衬底304的至少一部分上。另一保护层316可形成于保护层312和重分布层352的至少一部分上。在一些实施例中，一或多个通孔318可形成于保护层316和/或保护层312内。在一些情况下，第一通孔可在形成第一保护层312之后形成，而第二通孔可在形成第二保护层316之后形成。或者或另外，第一通孔和/或第二通孔可在已形成保护层312和保护层316之后形成。举例来说，可移除保护层316的一或多个部分；例如，可蚀刻、钻孔所述一或多个部分和/或使其曝露于光，以在保护层312和/或保护层316中形成第一孔。绝缘材料随后可置于第一孔内以加衬所述孔的侧边。最终，导电材料可置于所述孔中，由此形成一或多个通孔318。
封装件300可包含一或多个重分布层320，所述重分布层形成于保护层316上、形成于保护层316顶部上、直接接触保护层316或以其它方式布置在保护层316上。在一实施例中，保护层324可形成于保护层316上、形成于保护层316顶部上、直接接触保护层316或以其它方式布置在保护层316上。可移除保护层324的一或多个部分。举例来说，可将所述一或多个部分蚀刻、钻孔、曝露于光等，且由此在保护层324中形成孔。随后，重分布层320可形成于重分布层320的一或多个孔内。最后，一或多个凸块下金属化层328可形成于重分布层320上；所述一或多个凸块下金属化层328可配置成接收焊球和/或连接件332A到连接件332C，以形成例如球栅阵列。
如先前所论述，封装件300可包含重分布层308；重分布层308可提供经由介接部分376从光学管芯(oDie)340和/或一或多个eDie 336中的一或多个到连接件332A到连接件332C中的一或多个的信号路径。连接部分344可包含重分布层386A和/或重分布层386B中的一或多个、一或多个衬垫384A和衬垫384B、一或多个导电部分370以及一或多个绝缘部分382。集成电路封装穿孔(TIV)或绝缘体穿孔372可形成于衬底304中。举例来说，TIV 372可将重分布层308耦合到背侧重分布层346。举例来说，背侧重分布层346可将重分布层308耦合到一或多个重分布层352。因此，可形成将重分布层352耦合到一或多个重分布层386A和/或重分布层386B的通孔348。重分布层368A和/或重分布层386B可形成于衬垫384A和/或衬垫384B正上方或以其它方式布置在衬垫384A和/或衬垫384B上。衬垫384A和/或衬垫384B可布置在包含绝缘材料的绝缘部分382内；因此，衬垫384A和/或衬垫384B中的一或多个可经由导电部分370耦合到eDie 336。
oDie 340可耦合到光学内连线364，所述光学内连线可配置成接收来自光纤360的光和/或将所述光传送到oDie 340的检测器部分。因此，开口可存在于封装件300的光纤阵列接收侧。oDie 340可将光转换成一或多个电信号并将所述一或多个电信号传输或以其它方式提供到eDie 336和/或外部连接，例如连接件332A到连接件332C中的一或多个。可通过封装件300经由重分布层、一或多个通孔、一或多个TIV、一或多个衬垫384A和/或衬垫384B以及一或多个导电部分370中的一或多个传输一或多个电信号。
根据本公开的一些实施例，oDie 340和eDie 336可驻留在封装件300内。举例来说，空腔、孔或其它部分可形成或以其它方式存在于衬底304中。一或多个oDie 340和/或一或多个eDie 336中的每一个可驻留在例如横截面图中的两侧上的TIV之间。此外，衬底材料304可包含环氧基或另外为环氧基，使得衬底材料可在eDie 336、oDie 340以及一或多个TIV中的一或多个之间。在一些实施例中，eDie 336可直接连接到导电部分370和绝缘部分382中的一或多个或以其它方式布置在所述导电部分和所述绝缘部分中的一或多个上。
如图3A到图3B中进一步描绘，eDie 336可定位于oDie 340与绝缘部分382之间。因此，oDie 340可经由一或多个通孔388和一或多个凸块390耦合到eDie 336。根据至少一个实例，oDie 340可经倒装芯片接合到eDie 346，而封装件300采用集成电路封装技术。
图4A描绘根据本公开的实施例的第四封装件400的横截面图。图4B描绘图4A中所描绘的第四封装件400的放大部分。类似于第一封装件104、第二封装件200以及第三封装件300，第四封装件400可利用集成电路封装技术。第四封装件可包含衬底404。衬底404可包含模具材料、硅材料和/或其它基本上绝缘的或半导体材料。封装件400可包含形成于衬底404顶部上、直接接触衬底404且/或布置在衬底404上的保护层412。保护层412可包含聚酰亚胺和/或聚苯并恶唑材料。保护层412可为在封装之前用作保护层或“缓冲涂层”或用作重分布层452的应力消除涂层。在形成保护层412之前，一或多个重分布层408可形成于衬底404顶部上、直接接触衬底404且/或布置在衬底404的至少一部分上。另一保护层416可形成于保护层412和重分布层452的至少一部分上。在一些实施例中，一或多个通孔418可形成于保护层416和/或保护层412内。在一些情况下，第一通孔可在形成第一保护层412之后形成，而第二通孔可在形成第二保护层416之后形成。或者或另外，第一通孔和/或第二通孔可在已形成保护层412和保护层416之后形成。举例来说，可移除保护层416的一或多个部分；例如，可蚀刻、钻孔所述一或多个部分和/或使其曝露于光，以在保护层412和/或保护层416中形成第一孔。绝缘材料随后可置于第一孔内以加衬所述孔的侧边。最终，导电材料可置于所述孔中，由此形成一或多个通孔418。
封装件400可包含一或多个重分布层420，所述重分布层形成于保护层416上、形成于保护层416顶部上、直接接触保护层416或以其它方式布置在保护层416上。在一实施例中，保护层424可形成于保护层416上、形成于保护层416顶部上、直接接触保护层416或以其它方式布置在保护层416上。可移除保护层424的一或多个部分。举例来说，可将所述一或多个部分蚀刻、钻孔、曝露于光等，且由此在保护层424中形成孔。随后，重分布层420可形成于重分布层420的一或多个孔内。最后，一或多个凸块下金属化层428可形成于重分布层420上；所述一或多个凸块下金属化层428可配置成接收焊球和/或连接件432A到连接件432C，以形成例如球栅阵列。
如先前所论述，封装件400可包含重分布层408；重分布层408可提供经由介接部分476从光学管芯(oDie)440和/或一或多个eDie 436中的一或多个到连接件432A到连接件432C中的一或多个的信号路径。连接部分可包含重分布层486A和/或重分布层486B中的一或多个、一或多个衬垫484A和衬垫484B、一或多个导电部分470以及一或多个绝缘部分482。绝缘体穿孔(TIV)472(或集成电路封装穿孔)可形成于衬底404中。举例来说，TIV 472可将重分布层408耦合到背侧重分布层446。举例来说，背侧重分布层446可将重分布层408耦合到一或多个重分布层452。因此，可形成将重分布层452耦合到一或多个重分布层486A和/或重分布层486B的通孔448。重分布层468A和/或重分布层486B可形成于衬垫484A和/或衬垫484B正上方或以其它方式布置在衬垫484A和/或衬垫484B上。衬垫484A和/或衬垫484B可布置在包含绝缘材料的绝缘部分482内；因此，衬垫484A和/或衬垫484B中的一或多个可经由导电部分470耦合到oDie 440。
oDie 440可耦合到光学内连线464，所述光学内连线可配置成接收来自光纤460的光和/或将所述光传送到oDie 440的检测器部分。因此，开口可存在于封装件400的光纤阵列接收侧。oDie 440可将光转换成一或多个电信号并将所述一或多个电信号传输或以其它方式提供到eDie 436和/或外部连接，例如连接件432A到连接件432C中的一或多个。可通过封装件400经由重分布层、一或多个通孔、一或多个TIV、一或多个衬垫484A和/或衬垫484B以及一或多个导电部分470中的一或多个传输一或多个电信号。
根据本公开的一些实施例，oDie 440和eDie 436可驻留在封装件400内。举例来说，空腔、孔或其它部分可形成或以其它方式存在于衬底404中。一或多个oDie 440和/或一或多个eDie 436中的每一个可驻留在例如横截面图中的两侧上的TIV之间。此外，衬底材料404可包含环氧基或另外为环氧基，使得衬底材料可在eDie 436、oDie 440以及一或多个TIV中的一或多个之间。在一些实施例中，oDie 440可直接连接到导电部分470和绝缘部分482中的一或多个或以其它方式布置在所述导电部分和所述绝缘部分中的一或多个上。
如图4A到图4B中进一步描绘，oDie 440可定位于eDie 436与绝缘部分482之间。因此，eDie 436可利用一或多个凸块490耦合到oDie 440。一或多个通孔488可促进oDie 440与导电部分470和/或eDie 436的连接。根据至少一个实例，eDie 436可经倒装芯片接合到oDie 440，而封装件400采用集成电路封装技术。
图5A描绘根据本公开的实施例的第五封装件500的横截面图。图5B描绘图5A中所描绘的第五封装件500的放大部分。类似于第一封装件104、第二封装件200、第三封装件300以及第四封装件400，第五封装件500可利用集成电路封装技术。第五封装件可包含衬底504。衬底504可包含模具材料、硅材料和/或其它基本上绝缘的或半导体材料。封装件500可包含形成于衬底504顶部上、直接接触衬底504且/或布置在衬底504上的保护层512。保护层512可包含聚酰亚胺和/或聚苯并恶唑材料。保护层512可为在封装之前用作保护层或“缓冲涂层”或用作重分布层552的应力消除涂层。在形成保护层512之前，一或多个重分布层508可形成于衬底504顶部上、直接接触衬底504且/或布置在衬底504的至少一部分上。另一保护层516可形成于保护层512和重分布层552的至少一部分上。在一些实施例中，一或多个通孔518可形成于保护层516和/或保护层512内。在一些情况下，第一通孔可在形成第一保护层512之后形成，而第二通孔可在形成第二保护层516之后形成。或者或另外，第一通孔和/或第二通孔可在已形成保护层512和保护层516之后形成。举例来说，可移除保护层516的一或多个部分；例如，可蚀刻、钻孔所述一或多个部分和/或使其曝露于光，以在保护层512和/或保护层516中形成第一孔。绝缘材料随后可置于第一孔内以加衬所述孔的侧边。最终，导电材料可置于所述孔中，由此形成一或多个通孔518。
封装件500可包含一或多个重分布层520，所述重分布层形成于保护层516上、形成于保护层516顶部上、直接接触保护层516或以其它方式布置在保护层516上。在一实施例中，保护层524可形成于保护层516上、形成于保护层516顶部上、直接接触保护层516或以其它方式布置在保护层516上。可移除保护层524的一或多个部分。举例来说，可将所述一或多个部分蚀刻、钻孔、曝露于光等，且由此在保护层524中形成孔。随后，重分布层520可形成于重分布层520的一或多个孔内。最后，一或多个凸块下金属化层528可形成于重分布层520上；所述一或多个凸块下金属化层528可配置成接收焊球和/或连接件532A到连接件532C，以形成例如球栅阵列。
如先前所论述，封装件500可包含重分布层508；重分布层508可提供经由介接部分576从光学管芯(oDie)540和/或一或多个eDie 536中的一或多个到连接件532A到连接件532C中的一或多个的信号路径。连接部分可包含重分布层586A和/或重分布层586B中的一或多个、一或多个衬垫584A和衬垫584B、一或多个导电部分570以及一或多个绝缘部分582。绝缘体穿孔(TIV)572可形成于衬底504中。举例来说，TIV 572可将重分布层508耦合到背侧重分布层546。举例来说，背侧重分布层546可将重分布层508耦合到一或多个重分布层552。因此，可形成将重分布层552耦合到一或多个重分布层586A和/或重分布层586B的通孔548。重分布层568A和/或重分布层586B可形成于衬垫584A和/或衬垫584B正上方或以其它方式布置在衬垫584A和/或衬垫584B上。衬垫584A和/或衬垫584B可布置在包含绝缘材料的绝缘部分582内；因此，衬垫584A和/或衬垫584B中的一或多个可将可耦合oDie 540和eDie 536的插入件588耦合到导电部分570。
oDie 540可耦合到光学内连线564，所述光学内连线可配置成接收来自光纤560的光和/或将所述光传送到oDie 540的检测器部分。因此，开口可存在于封装件500的光纤阵列接收侧。oDie 540可将光转换成一或多个电信号并将所述一或多个电信号传输或以其它方式提供到eDie 536和/或外部连接，例如连接件532A到连接件532C中的一或多个。可通过封装件500经由重分布层、一或多个通孔、一或多个TIV、一或多个衬垫584A和/或衬垫584B以及一或多个导电部分570中的一或多个传输一或多个电信号。
根据本公开的一些实施例，oDie 540和eDie 536可连同插入件588驻留在封装件500内。举例来说，空腔、孔或其它部分可形成或以其它方式存在于衬底504中。一或多个oDie 540、一或多个eDie 536以及插入件588中的每一个可驻留在例如横截面图中的两侧上的TIV之间。此外，衬底材料504可包含环氧基或另外为环氧基，使得衬底材料可在eDie536、oDie 540以及一或多个TIV中的一或多个之间。在一些实施例中，oDie 540和eDie 536可利用一或多个凸块590和凸块592连接到插入件588，而插入件588直接连接到导电部分570和绝缘部分582中的一或多个或以其它方式布置在所述导电部分和所述绝缘部分中的一或多个上。如图5A到图5B中进一步描绘，eDie588可定位于oDie 540和/或eDie 536与绝缘部分582之间。根据至少一个实例，eDie 536和/或oDie 540可经倒装芯片接合到封装件500中的插入件588，所述封装件采用集成电路封装技术。
图1到图5B中所示的封装件的前述实施例中的一或多个可包含于系统或器件中。更确切地说，图6绘示包含光子封装件604的系统600。系统600还包含处理子系统608(具有一或多个处理器)和存储器子系统612(具有存储器)。
一般来说，系统600可使用硬件和/或软件的组合实施。因此，系统600可包含存储于存储器子系统612(例如DRAM或另一类型的易失性计算机可读存储器或非易失性计算机可读存储器)中的一或多个程序模块或指令集，所述程序模块或指令集在操作期间可由处理子系统608执行。
系统600可包含：开关、集线器、桥接器、路由器、通信系统(例如波分复用通信系统)、存储区域网络、数据中心、网络(例如区域网络)和/或计算机系统(例如多核心处理器计算机系统)。此外，计算机系统可包含但不限于：服务器(例如多插口、多机架服务器)、笔记本电脑、通信器件或系统、个人计算机、工作站、主机计算机、叶片(blade)、企业计算机、数据中心、平板计算机、超级计算机、网络附接存储(network-attached-storage；NAS)系统、存储区域网络(storage-areanetwork；SAN)系统、媒体播放器(例如MP3播放器)、电器设备、子笔记本/上网本、平板计算机、智能电话、蜂窝电话、网络设备、机顶盒、个人数字助理(personal digital assistant；PDA)、玩具、控制器、数字信号处理器、游戏控制台、器件控制器、电器设备内的计算引擎、消费者电子器件、便携式计算器件或便携式电子器件、个人助理和/或另一电子器件。
此外，光子封装件604可以用于广泛多种应用中，例如：通信(例如，用于收发信机、光学内连线或光学链路中，例如用于晶片内通信或晶片间通信)、射频滤波器、生物传感器、医学(例如诊断技术或外科手术)、条形码扫描器、计量(例如距离的精确测量)、制造(切割或焊接)、光刻工艺、数据存储装置(例如光学存储器件或系统)和/或娱乐(激光展示)。
图7描绘根据一些实施例的用于形成光子封装件的第一实例方法的流程图。在一实施例中，图7的过程可用于构建图1到图5B中绘示的光子封装件。首先，一或多个oDie116、eDie 108和/或插入件588在步骤704中接合在一起，使得所得定向导致有源表面向下。举例来说，一或多个oDie、eDie和/或插入件如图1到5B中所指示接合在一起。倒装芯片接合技术可应用于接合一或多个oDie、eDie和/或插入件。使用临时粘合剂将所得接合管芯和/或插入件固定到临时载体晶片，所述临时载体晶片可包含一或多个接续段(connectionsection)。通过在步骤708中分配模塑化合物来形成中间封装件以包封oDie、eDie和/或插入件，且可对分配的模塑化合物执行压缩和固化操作以在步骤712中产生中间封装件。可在步骤716中对中间封装件执行反向研磨操作以揭示oDie、eDie和/或插入件的背侧。在步骤720中，绝缘体通孔(TIV)形成于中间封装件中。在步骤724中，重分布层(redistributionlayer；RDL)220形成于通过反向研磨操作而暴露的表面的一或多个部分上，其中RDL有助于将信号从通孔布线到焊球。在一些实施例中，可形成一或多个衬垫、额外的RDL以及更多保护层。在步骤728中移除临时载体晶片，并且翻转所得中间封装件以暴露oDie和/或eDie的有源表面。在步骤732中，含有光学波导的一或多个光学连接件可安装到中间封装件，以使得光学波导光学耦合到oDie。
图8A到图8P说明根据一些实施例的用于制造光子封装件的示例制造工艺。当步骤8A到步骤8P描绘为单独的步骤时，应理解，一或多个步骤可与另一步骤组合且/或分成多个额外步骤。制造工艺可开始于图8A，其中膜802(例如PBO膜)可施加于载体衬底，例如玻璃载体衬底804。作为一个实例，可经由光传递热量转换处理来施加膜802。根据本公开的实施例，膜802施加于玻璃载体衬底804的背侧，如将从所制造的光子封装件中显而易见。在图8B处，例如Ti/Cu的晶种层可施加于膜804，接着是导电层以及光图案化和湿式酸蚀刻，以形成重分布层(RDL)806、RDL 808以及RDL 810。举例来说，晶种层Ti/CU可为1K/5KA厚，且导电层可为7微米厚。当然，涵盖了Ti/CU层的其它厚度。在图8C处，光刻胶层812可施加于膜802和/或RDL 806、RDL 808以及RDL 810。举例来说，光刻胶层812可为180微米到250微米厚。当然，涵盖了光刻胶层812的其它厚度。在施加光刻胶层812之后，一或多个绝缘体穿孔(TIV)814、TIV 816、TIV 818、TIV 820以及TIV 822可产生于光刻胶层812中。TIV 814、TIV 816、TIV818、TIV 820以及TIV 822为可能产生的TIV的实例；如位置、定向以及定尺般在本文中涵盖了更多或更少的TIV。举例来说，TIV可包含12微米直径的孔。孔中的每一个可包含或可不包含加衬孔内部的绝缘部分。在一些情况下，绝缘部分仅可加衬孔的一部分。在一些情况下，绝缘部分可能不存在。
在图8D处，可使用导电材料824填充孔。导电材料824可包含铜或其它导电材料。在一些情况下，可使用例如但不限于Cu-ECP的电化学镀敷工艺来形成导电材料824。在图8E处，可移除多余的铜从而暴露光刻胶层812。举例来说，可使用化学机械平坦化(Cu-CMP)工艺来移除多余的铜。当然，涵盖了其它移除工艺。在图8F处，可剥除光刻胶层812，留下TIV。此外，管芯附接膜(die attach film；DAF)828可用以固定光学内连线832、O-Die 830以及E-Die 834。O-Die 830、E-Die 834以及光学内连线832可与先前描述的O-Die、E-Die以及本文中先前所描述的光学内连线相同或类似。在一些情况下，DAF 828可预胶合到已知良好的管芯且使用取放式单元放置。在一些实例中，DAF 828可利用已知良好的管芯取放10次。在一些实例中，DAF 828可小于或大于10微米厚。在图8G处，可施加过度模塑化合物(moldingcompound；MC)836；MC 836可为50微米厚；在一些实例中，MC 836可小于或大于50微米厚。如图8H中所描绘，可移除过量的MC 836；例如可经由研磨和/或化学机械平坦化移除多余的MC836。
根据实施例，导电材料838可施加于MC 836的表面。在一些实例中，导电材料838可与导电材料824相同或类似。在一些实例中，可利用例如但不限于Cu-ECP的电化学镀敷工艺。导电材料824可电耦合到导电材料824，且在一些情况下电耦合到RDL 806、RDL 808以及RDL 810中的一或多个。如图8J中所描绘，可移除导电材料838的一或多个部分且保护层840可形成于MC 836的顶部和导电材料838的一或多个部分上。在一些实例中，导电材料838可为7微米厚。在一些实例中，保护层840可为4.5微米厚；在其它实例中，保护层840的厚度可小于或大于4.5微米厚。保护层可与例如但不限于先前所描述的保护层412的保护层相同或类似。在一些实例中，保护层840可包含PBO材料。
如图8J中所描绘，一些实例可包含RDL 842、RDL 844、RDL 846、RDL 848以及RDL850。RDL 842、RDL 844、RDL 845、RDL 846、RDL 848以及RDL 850可包含例如铜的导电材料，且可利用例如但不限于Cu-ECP图案化工艺的工艺。如图8K中所描绘，保护层841可施加于保护层840和RDL 842、RDL 844、RDL 846、RDL 848以及RDL 850的一或多个部分。根据一些实例，可将形成RDL 852、RDL 854以及RDL 856的导电材料图案化到保护层841上。如图8L中所描绘，另一保护层858可设置于保护层840和RDL 852、RDL 854以及RDL 856上。保护层858可为PBO层。可利用光掩模和图案化工艺且随后继之以例如湿式酸蚀刻的蚀刻工艺来施加RDL852、RDL 854以及RDL 856，。在一些实例中，可经由旋转涂布来施加保护层858。图8M描绘下凸块安装件(under bump mount；UBM)860、UBM 862以及UBM 864。可使用光掩模图案化工艺继之以例如但不限于湿式酸蚀刻的蚀刻工艺来施加UBM 860、UBM 862以及UBM 864。随后可沉积UBM 860、UBM 862以及UBM 864；在一些实例中，UBM 860、UBM 862以及UBM 864可为铜，且可利用Cu-ECP工艺进行沉积。如图8N中所描绘，凸块866、凸块868以及凸块870可形成于对应的UBM 860、UBM 862以及UBM 864的顶部上。
如图8O中所描绘，可在UV曝光于LTHC之后移除玻璃载体804，其中保护层802充当已组装封装件的最终保护层。如图8P中所描绘，可移除背侧区域的部分872以容纳光纤阵列874。虽然已利用多个步骤绘示了制造工艺，但是这些步骤和/或这些步骤的顺序不应被视为具限制性。
在一实施例中，一种集成扇出型(InFO)封装件提供成一种集成电路封装件，所述集成电路封装件可包含：光子管芯(oDie)，包含至少一个光学组件；电子管芯(eDie)；以及模塑部分，其中所述模塑部分包含以通信方式耦合到oDie和/或eDie中的至少一个的多个重分布层，且其中所述模塑部分至少部分地包围oDie和/或eDie中的至少一个。
在一实施例中，一种集成电路封装件，包括：光子管芯(oDie)，包含至少一个光学组件；电子管芯(eDie)；衬底，包含多个重分布层，所述多个重分布层通信耦合到所述光子管芯和/或所述电子管芯中的至少一个，其中所述衬底包括模塑部分，所述模塑部分至少部分地包围所述光子管芯和/或所述电子管芯中的所述至少一个；以及接续段，将所述光子管芯和/或电子管芯中的所述至少一个电耦合到至少一个重分布层，所述至少一个重分布层定位成邻近于所述集成电路封装件的最上层。
在一实施例中，所述光子管芯光学耦合到至少一个光纤。在一实施例中，所述光子管芯布置在所述电子管芯与所述接续段之间。在一实施例中，所述电子管芯布置在所述光子管芯与所述接续段之间。在一实施例中，所述集成电路封装件的第一侧包含一或多个凸块下金属化层，且与所述集成电路封装件的所述第一侧相对的所述集成电路封装件的第二侧包含所述光子管芯和/或电子管芯中的所述至少一个的暴露表面。在一实施例中，更包括所述第一侧与至少一个封装穿孔(TIV)之间的至少一个重分布层，所述封装穿孔将所述重分布层耦合到所述接续段。在一实施例中，所述接续段包含一或多个重分布层和一或多个通孔，所述一或多个重分布层和所述一或多个通孔将定位于所述集成电路封装件的所述第一侧处的焊料凸块耦合到所述光子管芯和/或电子管芯中的所述一或多个。在一实施例中，所述光子管芯和/或电子管芯中的所述至少一个直接耦合到所述接续段。在一实施例中，更包括布置在所述光子管芯和/或所述电子管芯中的所述至少一个与所述接续段之间的插入件。在一实施例中，所述光子管芯经由一或多个焊料凸块耦合到所述电子管芯。
在一实施例中，一种器件包含电耦合到所述集成电路封装件的逻辑和/或存储器组件中的至少一个。
在另一实施例中，提供一种包括光子管芯(oDie)和电子管芯(eDie)的封装件，所述oDie包含至少一个光学组件。封装件可包含具有第一侧和第二侧的模塑部分，其中所述模塑部分包含一或多个重分布层，所述一或多个重分布层将与模塑部分一起定位于封装件的第一侧处的oDie和/或eDie中的至少一个耦合到定位于封装件的第二侧处的导电部分。
在另一实施例中，一种封装件包括：光子管芯(oDie)，包含至少一个光学组件；电子管芯(eDie)；以及模塑部分，具有第一侧和第二侧，所述模塑部分包含一或多个重分布层，所述一或多个重分布层将定位于所述封装件的所述第一侧处的所述模塑部分中的所述光子管芯和/或所述电子管芯中的至少一个耦合到定位于所述封装件的所述第二侧处的导电部分。
在另一实施例中，所述模塑部分至少部分地包围所述光子管芯和/或所述电子管芯中的所述至少一个。在另一实施例中，更包含将所述光子管芯和/或电子管芯中的所述至少一个电耦合到至少一个重分布层的接续段，所述至少一个重分布层定位成邻近于所述封装件的所述第二侧。在另一实施例中，所述光子管芯布置在所述电子管芯与所述接续段之间。在另一实施例中，所述电子管芯布置在所述光子管芯与所述接续段之间。在另一实施例中，更包括布置在所述光子管芯和/或所述电子管芯中的所述至少一个与所述接续段之间的插入件。
在另一实施例中，一种器件包含电耦合到根所述的集成电路封装件的逻辑和/或存储器组件中的至少一个。
在一些实施例中，提供一种制作例如集成电路(InFO)封装件的集成电路封装件的方法。所述方法可包含：将至少一个光学管芯(oDie)电耦合到电子管芯(eDie)；在oDie的一部分和eDie的一部分周围形成包括模塑部分的中间封装件；以及移除所述模塑部分的至少一部分。随后，可在对应于移除部分的模塑部分的位置处形成至少一个重分布层，且可在至少一个重分布层上形成至少一个保护层，其中定位于模塑部分与集成电路封装件的第一侧之间的至少一个重分布层将oDie和/或eDie中的至少一个耦合到定位于集成电路封装件的第一侧处的导电部分。
在一些实施例中，更包括：形成多个封装通孔，其中所述封装通孔定位于所述模塑部分的一部分中，以使得所述光子管芯和/或所述电子管芯中的所述至少一个定位于横截面图中的所述多个封装通孔中的两个封装通孔之间。
前文概述若干实施例的特征以使得本领域的技术人员可更好地理解本公开的方面。本领域的技术人员应了解，其可很容易地将本公开用作设计或修改用于实现本文引入的实施例的相同目的及/或达成相同优势的其它工艺和结构的基础。本领域的技术人员还应认识到，这类等效构造并不脱离本公开的精神和范围，且其可在不脱离本公开的精神和范围的情况下在本文中进行各种改变、替代以及更改。

Claims (1)

1.一种集成电路封装件，包括：
光子管芯，包含至少一个光学组件；
电子管芯；
衬底，包含多个重分布层，所述多个重分布层通信耦合到所述光子管芯和/或所述电子管芯中的至少一个，其中所述衬底包括模塑部分，所述模塑部分至少部分地包围所述光子管芯和/或所述电子管芯中的所述至少一个；以及
接续段，将所述光子管芯和/或电子管芯中的所述至少一个电耦合到至少一个重分布层，所述至少一个重分布层定位成邻近于所述集成电路封装件的最上层。
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