CN112086445A - 混合封装组件 - Google Patents

混合封装组件 Download PDF

Info

Publication number
CN112086445A
CN112086445A CN201910836161.7A CN201910836161A CN112086445A CN 112086445 A CN112086445 A CN 112086445A CN 201910836161 A CN201910836161 A CN 201910836161A CN 112086445 A CN112086445 A CN 112086445A
Authority
CN
China
Prior art keywords
die
dielectric layer
waveguide
hybrid
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910836161.7A
Other languages
English (en)
Inventor
余振华
吴俊毅
夏兴国
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN112086445A publication Critical patent/CN112086445A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
    • G02B6/136—Integrated optical circuits characterised by the manufacturing method by etching
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02002—Arrangements for conducting electric current to or from the device in operations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12083—Constructional arrangements
    • G02B2006/121—Channel; buried or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0635—Acrylic polymer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Electromagnetism (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Optical Integrated Circuits (AREA)

Abstract

一种实施例混合封装组件包含：第一介电层；第一光子管芯和第二光子管芯，邻近第一介电层的第一侧安置；波导，将第一光子管芯光学耦合到第二光子管芯，波导安置在第一介电层与第一光子管芯之间以及第一介电层与第二光子管芯之间；第一集成电路管芯和第二集成电路管芯，邻近第一介电层的第一侧安置；导电构件，穿过第一介电层且沿第一介电层的第二侧延伸，导电构件将第一光子管芯电性耦合到第一集成电路管芯，导电构件将第二光子管芯电性耦合到第二集成电路管芯；以及第二介电层，邻近第一介电层的第二侧安置。

Description

混合封装组件
技术领域
本发明的实施例是有关于一种混合封装组件。
背景技术
电信令(signaling)和处理(processing)是一种用于信号传输和处理的技术。近年来已在越来越多的应用中使用光学信令和处理，具体地说是归因于用于信号传输的光纤相关应用的使用。光学信令和处理通常与电信令和处理进行组合以提供成熟的应用。举例来说，光纤可用于长程信号传输，且电信号可用于短程信号传输以及处理和控制。因此，整合光学组件和电性组件的装置形成以在光信号与电信号之间进行转换以及处理光信号和电信号。因此，封装可包含：包含光学装置的光学(光子)管芯和包含电子装置的电子管芯两者。
发明内容
本发明实施例提供一种混合封装组件，包括第一介电层、第一光子管芯、第二光子管芯、波导、第一集成电路管芯、第二集成电路管芯、导电构件以及第二介电层。第一光子管芯邻近第一介电层的第一侧安置。第二光子管芯邻近第一介电层的第一侧安置。波导将第一光子管芯光学耦合到第二光子管芯。波导安置在第一介电层与第一光子管芯之间以及第一介电层与第二光子管芯之间。第一集成电路管芯邻近第一介电层的第一侧安置。第二集成电路管芯邻近第一介电层的第一侧安置。导电构件穿过第一介电层且沿第一介电层的第二侧延伸。导电构件将第一光子管芯电性耦合到第一集成电路管芯。导电构件将第二光子管芯电性耦合到第二集成电路管芯。第二介电层邻近第一介电层的第二侧安置。
本发明实施例提供一种混合封装组件的制作方法，包括以下步骤。在载体衬底上方形成波导。在波导上方及周围沉积第一介电层。对来自第一介电层的第一侧的导线进行镀覆。去除载体衬底以暴露波导及第一介电层的第二侧。形成延伸穿过第一介电层以耦合导线的导电构件。将第一光子管芯及第二光子管芯附接到波导及第一介电层的第二侧。以及，将第一集成电路管芯及第二集成电路管芯附接到导电构件及第一介电层的第二侧。
本发明实施例提供一种混合封装组件的制作方法，包括以下步骤。形成混合重布线结构。在形成混合重布线结构之后，将第一光子管芯及第二光子管芯附接到混合重布线结构。以及，将第一集成电路管芯及第二集成电路管芯附接到混合重布线结构。形成混合重布线结构的步骤，包括在载体衬底上形成波导。在波导上方及周围沉积第一介电层。形成穿过第一介电层且沿第一介电层的主表面延伸的导电构件。以及，在导电构件及第一介电层的主表面上方沉积第二介电层。第一光子管芯通过波导光学耦合到第二光子管芯。第一集成电路管芯通过导电构件电性耦合到第一光子管芯。第二集成电路管芯通过导电构件电性耦合到第二光子管芯。
附图说明
结合附图阅读以下详细说明，会最好地理解本公开的各个方面。应注意，根据本行业中的标准惯例，各种特征未按比例绘制。实际上，为了论述清楚起见，可任意增大或减小各种特征的尺寸。
图1是根据一些实施例的混合封装组件的俯视示意图。
图2是根据一些实施例的集成电路封装的剖视图。
图3是根据一些实施例的电子管芯的剖视图。
图4是根据一些实施例的光子管芯的剖视图。
图5、图6、图7、图8、图9、图10、图11、图12、图13、图14、图15、图16、图17、图18、图19、图20、图21、图22、图23以及图24是在用于形成根据一些实施例的混合封装组件的工艺期间的中间步骤的剖视图。
图25A和图25B是根据一些实施例的混合封装组件的剖视图。
图26示出根据一些其它实施例的包含混合封装组件的系统。
图27示出根据一些其它实施例的包含混合封装组件的系统。
[附图标号说明]
100：混合封装组件；
100A：第一封装区域；
102：集成电路封装；
104：混合重布线结构；
106：电子管芯；
108、108A、108B：外部连接件；
110、110A、110B、224、228、232、236：金属化图案；
112：光子管芯；
114：波导；
114A：平直部分；
114B：倾斜部分；
118：逻辑管芯；
120：存储器装置；
122：重布线结构；
124：连接件；
126：包封体；
128、132、244：衬底；
130、134：管芯连接件；
136：光学输入/输出端口；
202：载体衬底；
203：释放层；
204、218、222、226、230、234、238：介电层；
208、212：波导包覆层；
210：波导芯层；
214、220：导线；
214A：导线的第一子组；
216、248：导通孔；
246：衬底芯；
254：包封体；
256：开口；
260：底填充料；
240、252A、252B：凸块下金属；
242、258：导电连接件；
248A：导电材料；
248B：填充材料；
25、9：区域；
250A、250B：重布线结构；
253A、253B：焊料抗蚀剂；
300：封装衬底；
302：接合衬垫；
D1、D2、D3、D4：距离；
T1、T2、T3：厚度；
θ1：锐角。
具体实施方式
以下公开内容提供用于实施本发明的不同特征的许多不同实施例或实例。下文描述组件和布置的特定实例以简化本公开。当然，这些特定实例只是实例且不意图为限制性的。举例来说，在以下描述中，第一特征在第二特征上方或第二特征上形成可包含第一特征与第二特征直接接触地形成的实施例，且还可包含可在第一特征与第二特征之间形成额外特征以使得第一特征与第二特征可以不直接接触的实施例。另外，本公开可在各种实例中重复附图标记和/或字母。此重复是出于简单和清楚的目的，且本身并不规定所论述的各种实施例和/或配置之间的关系。
此外，为易于描述，可在本文中使用如“在…下面(beneath)”、“在…下方(below)”、“下部(lower)”、“在…上方(above)”、“上部(upper)”等空间相对术语，以描述如图中所示出的一个元件或特征与另一元件或特征的关系。除图中所描绘的定向之外，空间相对术语意图涵盖装置在使用或操作中的不同定向。设备可以其它方式定向(旋转90度或处于其它定向)，且本文中所使用的空间相对描述词同样可相应地进行解释。
根据一些实施例，混合封装组件形成为具有电子集成电路管芯和光子集成电路管芯。混合封装组件具有混合重布线结构，所述混合重布线结构将电子管芯电性耦合到光子管芯，且光学耦合光子集成电路管芯。因此，电子集成电路管芯之间的信号路径包含光信号路径和电信号路径。因此，可减少混合重布线结构中的导电构件的量。在制造之后，光子集成电路管芯附接到混合重布线结构，从而使得混合封装组件的制造灵活性得到改善。
图1是根据一些实施例的混合封装组件100的俯视示意图。混合封装组件100包含集成电路封装102、混合重布线结构104、电子管芯106以及光子管芯112。集成电路封装102(下文进一步论述)包含用于形成计算系统的一个或多个集成电路管芯。混合重布线结构104(下文进一步论述)具有用于从集成电路封装102到外部连接件108进行重布线和/或扇出连接的导电构件和光子构件。具体地说，混合重布线结构104包含金属化图案110和波导114(下文进一步论述)。
金属化图案110A的第一子组将集成电路封装102电性耦合到外部连接件108A的第一子组。集成电路封装102与外部连接件108A之间的信号路径是连续电信号路径。金属化图案110B的第二子组和波导114将集成电路封装102光学且电性地耦合到外部连接件108B的第二子组。金属化图案110B将光子管芯112电性地连接到集成电路封装102和外部连接件108B。光子管芯112在波导114上进行光学通信，且光学耦合电子管芯106。电子管芯106(下文进一步论述)将光子管芯112介接到集成电路封装102，且还将光子管芯112介接到外部连接件108B。集成电路封装102与外部连接件108B之间的信号路径是非连续电性和光信号路径。具体地说，集成电路封装102与外部连接件108B之间的信号路径包含光子管芯112之间的光信号路径(例如在波导114上)以及往返行进于光信号路径的电信号路径。
根据一些实施例，金属化图案110和波导114是混合重布线结构104的部分。金属化图案110和波导114嵌入混合重布线结构104的绝缘构件中，且光子管芯112附接到混合重布线结构104，接近集成电路封装102和外部连接件108B。金属化图案110A用于短连接，如具有在约0.5毫米到约5毫米范围内的长度的连接。金属化图案110B和波导114用于长连接，如具有在约1毫米到约150毫米范围内的长度的连接。使用光子构件进行长连接可避免或减少插入损耗和/或那些连接上的串扰。具体地说，当混合封装组件100是大封装(如大于60毫米乘60毫米正方形的封装)时，插入损耗和/或串扰可能恶化串行通信。利用串行通信的大封装可适用于需要高数据传输速率和低延迟的高性能计算(high performance computing；HPC)应用，如高级网络、数据中心、人工智能(artificial intelligence；AI)以及类似物。通过减少插入损耗和/或串扰，可进一步提升串行通信的数据传送速率。此外，光子构件的使用减少了混合重布线结构104中所形成的导电构件的总量。可减少信号路由的量，进而增加混合封装组件100的制造产率。
图2是根据一些实施例的集成电路封装102的剖视图。集成电路封装102包含用于形成计算系统的一个或多个集成电路管芯。在所示实施例中，集成电路封装102包含逻辑管芯118、存储器装置120以及电子管芯106。逻辑管芯118可以是例如中央处理单元(centralprocessing unit；CPU)、图形处理单元(graphics processing unit；GPU)、单晶片系统(system-on-a-chip；SoC)、应用处理器(application processor；AP)、微处理器或类似物。逻辑管芯118可包括衬底，具有形成于衬底的有源表面处的有源装置；以及衬底上的互连结构，用于将有源装置互连以形成集成电路。存储器装置120可以是例如动态随机存取存储器(dynamic random access memory；DRAM)管芯、静态随机存取存储器(static randomaccess memory；SRAM)管芯、混合存储立方体(hybrid memory cube；HMC)装置、高带宽存储器(high bandwidth memory；HBM)装置或类似物。存储器装置120可包括多个衬底，具有有源装置；以及衬底上的多个互连结构，用于将有源装置互连以形成集成电路。电子管芯106将逻辑管芯118电性介接到混合重布线结构104的光子管芯112中的一个或多个。逻辑管芯118、存储器装置120以及电子管芯106附接到重布线结构122且由所述重布线结构互连。重布线结构122可以是例如内插器或类似物，且具有用于外部连接的连接件124。可在重布线结构122上以及逻辑管芯118、存储器装置120以及电子管芯106周围形成包封体126，进而保护集成电路封装102的各种组件。
图3是根据一些实施例的电子管芯106的剖视图。电子管芯106各自包含衬底128和管芯连接件130(图2中未示出)。装置在衬底128的表面处形成。装置可包含需要将逻辑管芯118与光子管芯112介接的电子电路，以及需要将光子管芯112与外部连接件108B(见图1)介接的电子电路。举例来说，电子管芯106可包含控制器、CMOS驱动器、跨阻放大器以及类似物。电子管芯106根据从逻辑管芯118接收到的电信号(数字或模拟)来控制光子管芯112的高频信令。电子管芯106可以是电子集成电路(electronic integrated circuit；EIC)。管芯连接件130耦合到衬底128的装置，且用于电性连接到逻辑管芯118和/或外部连接件108B(见图1)。
图4是根据一些实施例的光子管芯112的剖视图。光子管芯112发射并接收光信号。具体地说，光子管芯112将电信号转换成光信号以沿波导114进行传输，且将来自波导114的光信号转换成电信号。因此，光子管芯112负责光信号向/从波导114的输入/输出(input/output；I/O)。光子管芯112可以是光子集成电路(photonic integrated circuit；PIC)。光子管芯112包含具有形成于其中/其上的信号传输装置的衬底132。光子管芯112更包含管芯连接件134，用于电性连接到电子管芯106；以及光学I/O端口136，用于光学连接到波导114。
图5到图24是在用于形成根据一些实施例的混合封装组件100的工艺期间的中间步骤的剖视图。图5到图15示出混合重布线结构104(见图15)的形成。混合重布线结构104包含介电层、导电构件以及光子构件。导电构件可包含金属化图案(其也可称作重布线层或重布线线路)和凸块下金属(under-bump metallurgy；UBM)。在混合重布线结构104的形成期间，将波导114嵌入混合重布线结构104中。光子管芯112附接到混合重布线结构104且使用波导114进行通信，进而减少混合重布线结构104中的长迹线的量。虽然示出了一对光子管芯112和单个波导114的形成，但应了解，混合重布线结构104可包含任何数量的光子管芯112和波导114。图16到图24示出来自混合重布线结构104(见图24)的混合封装组件100的形成。混合封装组件100包含由混合重布线结构104的导电构件和光子构件两者互连的多个集成电路管芯。
混合封装组件100形成为重建晶片的部分。示出了重建晶片的第一封装区域100A。应了解，多个封装区域形成于重建晶片中，且混合封装组件100形成于封装区域中的每一个中。
在图5中，设置载体衬底202，且在载体衬底202上形成释放层203。载体衬底202可以是玻璃载体衬底、陶瓷载体衬底或类似物。载体衬底202可以是晶片，以使得可同时在载体衬底202上形成多个封装。释放层203可由聚合物类材料形成，所述材料可与载体衬底202一起从将在后续步骤中形成的上覆结构去除。在一些实施例中，释放层203是环氧树脂类热释放材料，所述材料在加热时失去其粘合特性，例如光热转换(light-to-heat-conversion；LTHC)释放涂层。在其它实施例中，释放层203可以是紫外线(ultra-violet；UV)胶，其在暴露于UV光下时损失其粘合特性。释放层203可分配为液体并固化，可以是层压到载体衬底202上的层压膜，或可以是类似物。释放层203的顶部表面可以是水平的，且可具有高平面度。
在图6中，波导包覆层208在载体衬底202上方形成。波导包覆层208将成为波导114的部分，所述波导114光学耦合一对后续附接的光子管芯112(见图23)。波导包覆层208可由适用于光学器件的聚合物形成，如塑料或层压物。适用于光学器件的聚合物的实施例包含丙烯酸酯(例如POLYGUIDETM)、卤化丙烯酸酯、氘化聚硅氧烷、氟化聚酰亚胺(例如UltradelTM)、聚醚酰亚胺(例如UltemTM)、全氟环丁烷、苯并环丁烯、全氟乙烯基醚环聚合物、四氟乙烯和全氟乙烯基醚共聚物(例如TeflonTMAF)、聚碳酸酯(例如BeamBoxTM)、氟化聚(伸芳基醚硫化物)、无机聚合物玻璃、聚(甲基丙烯酸甲酯)共聚物、含有CLD-1发色团的聚碳酸酯、含有FTC发色团的聚碳酸酯以及含有CLD-1发色团的聚(甲基丙烯酸甲酯)。在一些实施例中，波导包覆层208在所要位置中选择性形成。举例来说，波导材料可通过模板印刷而形成。在一些实施例中，波导包覆层208通过以下操作而形成：形成波导材料的共形层；以及随后对所述层进行蚀刻以使得波导材料保持在所要位置中。举例来说，波导材料可通过旋涂、层压、化学气相沉积(chemical vapor deposition；CVD)或类似操作而形成，且可随后利用可接受的光刻和蚀刻技术进行图案化。
在图7中，波导芯层210在波导包覆层208上方形成。波导芯层210将成为波导114的部分，所述波导114光学耦合一对后续附接的光子管芯112(见图23)。波导芯层210可由波导包覆层208的候选材料形成，且可通过形成波导包覆层208的候选方法而形成。
在图8中，波导包覆层212在波导芯层210上方形成。波导包覆层212将成为波导114的部分，所述波导114光学耦合一对后续附接的光子管芯112(见图23)。波导包覆层212可由波导包覆层208的候选材料形成，且可通过形成波导包覆层208的候选方法而形成。
在形成之后，波导114包含波导包覆层208和波导包覆层212以及波导芯层210。波导包覆层208与波导包覆层212可由相同材料形成，且相较于波导芯层210由不同材料形成。具体地说，波导包覆层208和波导包覆层212相较于波导芯层210由具有不同折射率的材料形成。在一实施例中，波导芯层210的材料的折射率高于波导包覆层208和波导包覆层212的材料的折射率。举例来说，波导芯层210的材料的折射率可在约1到约2的范围内，且波导包覆层208和波导包覆层212的材料的折射率可在约1到约2的范围内，其中波导芯层210的材料的折射率以在约0.05与约1的范围内的量大于波导包覆层208和波导包覆层212的材料的折射率。因此，波导包覆层208和波导包覆层212具有高内部反射以使得在操作期间将光约束在波导芯层210中。举例来说，波导包覆层208和波导包覆层212可由卤化丙烯基形成，且波导芯层210可由卤化丙烯基形成，其中对所述层中的一个或多个进行改性以改变其折射率，如用溴化交联剂进行改性。
图9示出来自图8的区域9的详细视图，其绘示波导114的额外特征。波导包覆层208和波导包覆层212形成为厚度T1，且波导芯层210形成为较大厚度T2。举例来说，厚度T1可在约4微米到约5微米的范围内，且厚度T2可在约6微米到约7微米的范围内。波导包覆层208和波导包覆层212还形成为第一宽度(未示出，垂直于厚度T1)，且波导芯层210形成为较小第二宽度(未示出，垂直于厚度T2)。举例来说，第一宽度可在约8微米到约25微米的范围内，且第二宽度可在约6微米到约7微米的范围内。
此外，波导114包含平直部分114A和倾斜部分114B。平直部分114A与倾斜部分114B一起形成光传输路径。平直部分114A平行于载体衬底202的主表面，且将平行于所得混合重布线结构104的主表面。倾斜部分114B与载体衬底202的主表面形成锐角θ1，且将与所得混合重布线结构104的主表面形成锐角θ1。锐角θ1足够大以确保入射光的充分传输，而又足够小以避免从反射中损失。举例来说，锐角θ1可在约20度到约30度的范围内。
在图10中，介电层204在载体衬底202和波导114上方形成。介电层204可以是光敏聚合物，如聚苯并恶唑(polybenzoxazole；PBO)、聚酰亚胺、苯并环丁烯(benzocyclobutene；BCB)或类似物；氮化物，如氮化硅或类似物；氧化物，如氧化硅、磷硅玻璃(phosphosilicate glass；PSG)、硼硅玻璃(borosilicate glass；BSG)、硼掺杂磷硅玻璃(boron-doped phosphosilicate glass；BPSG)或类似物；类似物；或其组合。介电层204可例如通过旋涂、层压、化学气相沉积(CVD)或类似操作而形成。因为介电层204和波导114都安置在载体衬底202上方，所以其可具有呈水平的表面。举例来说，介电层204的主表面可与波导114的底部表面齐平(例如为平面的)。
在图11中，导线214在介电层204上形成。作为形成导线214的实例，在介电层204上方形成晶种层。在一些实施例中，晶种层是金属层，其可以是单个层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。晶种层可使用例如物理气相沉积(physical vapor deposition；PVD)或类似操作而形成。随后在晶种层上形成并图案化光刻胶。光刻胶可通过旋涂或类似操作而形成，且可暴露于光下以进行图案化。光刻胶的图案对应于导线214。所述图案化形成穿过光刻胶的开口以暴露晶种层。随后在光刻胶的开口中且在晶种层的暴露部分上形成导电材料。导电材料可通过镀覆(plating)形成，如电镀(electroplating)或无电式镀覆或类似方法。导电材料可包括金属，如铜、钛、钨、铝或类似物。晶种层的导电材料与底层部分的组合形成导线214。去除光刻胶和晶种层上未形成导电材料的部分。光刻胶可通过可接受的灰化或剥离工艺去除，如使用氧等离子或类似物。一旦将光刻胶去除，便将晶种层的暴露部分去除，如通过使用可接受蚀刻工艺，如通过湿式或干式蚀刻来进行。
在图12中，导通孔216在导线214上形成且从导线214延伸。作为形成导通孔216的实例，晶种层在导线214和介电层204上方形成。在一些实施例中，晶种层是金属层，其可以是单个层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。晶种层可使用例如PVD或类似操作而形成。随后在晶种层上形成并图案化光刻胶。光刻胶可通过旋涂或类似操作而形成，且可暴露于光下以进行图案化。光刻胶的图案对应于导通孔216。所述图案化形成穿过光刻胶的开口以暴露晶种层。随后在光刻胶的开口中且在晶种层的暴露部分上形成导电材料。导电材料可通过镀覆形成，如电镀或无电式镀覆或类似操作。导电材料可包括金属，如铜、钛、钨、铝或类似物。晶种层的导电材料与底层部分的组合形成导通孔216。去除光刻胶和晶种层上未形成导电材料的部分。光刻胶可通过可接受的灰化或剥离工艺去除，如使用氧等离子或类似物。一旦将光刻胶去除，便将晶种层的暴露部分去除，如通过使用可接受蚀刻工艺，如通过湿式或干式蚀刻来进行。
在图13中，介电层218在各种组件上和各种组件周围形成。在形成之后，介电层218包围导通孔216和导线214。在一些实施例中，介电层218是包封体，如模制化合物、环氧树脂或类似物，且可通过压缩模塑、传递模塑或类似操作来涂覆。包封体可以液体或半液体形式进行涂覆且随后相继固化。在一些实施例中，介电层218在载体衬底202上方形成以使得将导通孔216掩埋或覆盖，且随后对介电层218执行平坦化工艺以暴露导通孔216。在平坦化工艺之后，介电层218与导通孔216的最顶部表面齐平(例如为平面的)。平坦化工艺可以是例如化学机械抛光(chemical-mechanical polish；CMP)。
在图14中，导线220在介电层218和导通孔216的暴露部分上形成。作为形成导线220的实例，晶种层在介电层218和导通孔216的暴露部分上方形成。在一些实施例中，晶种层是金属层，其可以是单个层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。晶种层可使用例如PVD或类似操作而形成。随后在晶种层上形成并图案化光刻胶。光刻胶可通过旋涂或类似操作而形成，且可暴露于光下以进行图案化。光刻胶的图案对应于导线220。所述图案化形成穿过光刻胶的开口以暴露晶种层。随后在光刻胶的开口中且在晶种层的暴露部分上形成导电材料。导电材料可通过镀覆形成，如电镀或无电式镀覆或类似操作。导电材料可包括金属，如铜、钛、钨、铝或类似物。晶种层的导电材料与底层部分的组合形成导线220。去除光刻胶和晶种层上未形成导电材料的部分。光刻胶可通过可接受的灰化或剥离工艺去除，如使用氧等离子或类似物。一旦将光刻胶去除，便将晶种层的暴露部分去除，如通过使用可接受蚀刻工艺，如通过湿式或干式蚀刻来进行。
当介电层218由包封体形成时，所述介电层可形成为较大厚度T3，如至少13微米的厚度T3。具体地说，包封体提供较大机械支撑，且因此相较于氮化物、氧化物、光敏聚合物或类似物可形成为较大厚度T3。较大厚度T3可允许较大导通孔216以及导线214和导线220的形成。具体地说，当介电层218是包封体时，导通孔216以及导线214和导线220可形成为较长长度和较大宽度。对于一些类型的连接(如电源和/或接地连接)，具有较长长度和较大宽度的构件可为合意的。
尽管已描述一种用于形成导通孔216、介电层218以及导线220的工艺，但应了解，可使用其它工艺来形成所述构件。举例来说，当介电层218的较大厚度T3不合意时，介电层218可由不同材料形成。在一些实施例中，介电层218由光敏材料形成，如PBO、聚酰亚胺、BCB或类似物，所述材料可使用光刻掩模来图案化。可随后形成包括对应于导通孔216的通孔部分和对应于导线220的线路部分的单个金属化图案。在此类实施例中，金属化图案的线路部分在介电层218的主表面上且沿主表面延伸，且金属化图案的通孔部分延伸穿过介电层218以物理且电性地耦合导线214。在此类实施例中，在导通孔216与导线220与之间不形成晶种层。
在图15中，重复上文所论述的步骤和工艺以形成介电层222、介电层226、介电层230、介电层234以及介电层238；且形成金属化图案224、金属化图案228、金属化图案232以及金属化图案236。介电层222、介电层226、介电层230、介电层234以及介电层238可由包封体形成，或可由氮化物、氧化物、光敏聚合物或类似物形成。金属化图案224、金属化图案228、金属化图案232以及金属化图案236可各自是具有线路和通孔部分的单个图案，或可具有单独形成的导线和导通孔。混合重布线结构104绘示为具有六个金属化图案层的实例。可分别通过重复或省略上文所论述的步骤和工艺在混合重布线结构104中形成更多或更少介电层和金属化图案。
在所示实施例中，介电层218和介电层226由包封体形成，且介电层222、介电层230、介电层234以及介电层238由氮化物、氧化物、光敏聚合物或类似物形成。举例来说，介电层218和介电层226可包含数据传输线，且介电层222、介电层230、介电层234以及介电层238可包含电源线和接地线。在其它实施例中，介电层218、介电层222、介电层226、介电层230、介电层234以及介电层238可由材料的其它组合形成，且可包含电源线、接地线以及数据传输线的其它配置。
此外，形成UBM 240以用于外部连接到混合重布线结构104。UBM 240具有在介电层238的主表面上且沿主表面延伸的凸块部分，且具有延伸穿过介电层238以物理且电性地耦合金属化图案236的通孔部分。UBM 240可以类似方式且由与金属化图案224、金属化图案228、金属化图案232以及金属化图案236类似的材料形成。在一些实施例中，相较于金属化图案224、金属化图案228、金属化图案232以及金属化图案236，UBM 240具有不同大小。因此，混合重布线结构104的金属化图案110(见图1)包括金属化图案224、金属化图案228、金属化图案232和金属化图案236以及UBM 240。
在图16中，导电连接件242在UBM 240上形成。导电连接件242可以是球栅阵列(ball grid array；BGA)连接件、焊球、金属柱、受控塌陷芯片连接(controlled collapsechip connection；C4)凸块、微凸块、无电镀镍钯浸金技术(electroless nickel-electroless palladium-immersion gold technique；ENEPIG)形成的凸块或类似物。导电连接件242可包含导电材料，如焊料、铜、铝、金、镍、银、钯、锡、类似物或其组合。在一些实施例中，导电连接件242通过蒸镀、电镀、印刷、焊料转移、植球或类似方法初始地形成焊料层而形成。一旦在所述结构上形成焊料层，便可执行回焊以便使材料成形为所要凸块形状。在另一实施例中，导电连接件242包括通过溅镀、印刷、电镀、无电式镀覆、CVD或类似操作形成的金属柱(如铜柱)。金属柱可为无焊料的且具有基本上竖直的侧壁。在一些实施例中，在金属柱的顶部上形成金属顶盖层。金属顶盖层可包含镍、锡、锡铅、金、银、钯、铟、镍钯、金、镍金、类似物或其组合，且可通过镀覆工艺形成。
在图17中，衬底244可附接到混合重布线结构104的第一侧。衬底244可以是例如有机衬底、陶瓷衬底、硅衬底或类似物。导电连接件242用以将衬底244附接到混合重布线结构104。附接衬底244可包含将衬底244放置在导电连接件242上，以及对导电连接件242进行回焊以将衬底244与混合重布线结构104物理且电性地耦合。
在附接到混合重布线结构104之前，可根据适用的制造工艺对衬底244进行处理以在衬底244中形成重布线结构。举例来说，衬底244包含衬底芯246。衬底芯246可由玻璃纤维、树脂、填充剂、其它材料和/或其组合形成。衬底芯246可由有机和/或无机材料形成。在一些实施例中，衬底芯246包含嵌入内部的一个或多个无源组件(未示出)。或者，衬底芯246可包括其它材料或组件。导通孔248形成为延伸穿过衬底芯246。导通孔248包括导电材料248A，如铜、铜合金或其它导体，且在一些实施例中可包含阻挡层、衬里、晶种层和/或填充材料248B。导通孔248提供从衬底芯246的一侧到衬底芯246的另一侧的竖直电性连接。举例来说，导通孔248中的一些耦合在衬底芯246的一侧处的导电构件与衬底芯246的相对侧处的导电构件之间。作为实例，导通孔248的电洞可使用钻孔工艺、光刻、激光工艺或其它方法来形成，且导通孔248的电洞随后由导电材料填充。在一些实施例中，导通孔248是中空导通孔，所述通孔具有由绝缘材料填充的中心。重布线结构250A和重布线结构250B在衬底芯246的相对侧上形成。重布线结构250A和重布线结构250B通过导通孔248和扇入/扇出电信号电性耦合。重布线结构250A和重布线结构250B各自包含介电层和金属化图案。各对应金属化图案具有在对应介电层的主表面上且沿主表面延伸的线路部分，且具有延伸穿过对应介电层的通孔部分。重布线结构250A和重布线结构250B各自分别包含用于外部连接的UBM 252A和UBM 252B，以及保护重布线结构250A和重布线结构250B的构件的焊料抗蚀剂253A和焊料抗蚀剂253B。重布线结构250A通过UBM 252A附接到混合重布线结构104。
在图18中，包封体254在各种组件上和各种组件周围形成。在形成之后，包封体254包围衬底244和导电连接件242。包封体254可由模塑化合物、环氧树脂或类似物形成，且可通过压缩模塑、传递模塑或类似方法来涂覆。包封体254可以液体或半液体形式进行涂覆且随后相继固化。包封体254可在载体衬底202上方形成以使得将衬底244掩埋或覆盖。
在图19中，随后对包封体254执行平坦化工艺以暴露衬底244的UBM 252B。在平坦化工艺之后，包封体254与UBM 252B的最顶部表面齐平(例如为平面的)。平坦化工艺可以是例如CMP。
虽然混合封装组件100示出为包含衬底244和包封体254，但应了解，这些构件是任选的。在其它实施例(下文论述)中，省略这些构件。
在平坦化工艺之后，执行载体衬底去接合以将载体衬底202从混合重布线结构104(例如从介电层204和波导114)拆离(或“去接合”)。根据一些实施例，去接合包含在释放层203上投射光(如激光或UV光)以使得释放层203在光的热量下分解，且可去除载体衬底202。随后将所述结构翻转且置于胶带上。
在图20中，开口256在介电层204中形成，从而暴露导线214。开口256暴露导线214的第一子组214A。开口256可通过钻孔工艺形成，如激光钻孔、机械钻孔或类似工艺。
在图21中，导电连接件258在开口256中形成，耦合到暴露的导线214。导电连接件258可以是球栅阵列(BGA)连接件、焊球、金属柱、受控塌陷芯片连接(C4)凸块、微凸块或类似物。导电连接件258可包含导电材料，如焊料、铜、铝、金、镍、银、钯、锡、类似物或其组合。在一些实施例中，导电连接件258通过蒸镀、电镀、印刷、焊料转移、植球或类似操作在开口256中初始地形成可回焊材料层而形成。一旦已在开口256中形成可回焊材料层，便可执行回焊以便使材料成形为所要凸块形状。
在图22中，通过沿划线区域(例如在第一封装区域100A周围)锯割来执行工艺。所述锯割将第一封装区域100A从邻近封装区域单体化。所得单体化组件来自第一封装区域100A。
在图23中，集成电路封装102附接到混合重布线结构104的第二侧，与衬底244相对。导电连接件258用以将集成电路封装102的连接件124附接到混合重布线结构104的导线214。附接集成电路封装102可包含将集成电路封装102放置在导电连接件258上，以及对导电连接件258进行回焊以将集成电路封装102与混合重布线结构104物理且电性地耦合。集成电路封装102包含用于与逻辑管芯118介接的第一电子管芯106。
此外，第二电子管芯106附接到混合重布线结构104的第二侧，与衬底244相对。导电连接件258还用以将第二电子管芯106的管芯连接件130附接到混合重布线结构104的导线214。附接第二电子管芯106可包含将第二电子管芯106放置在导电连接件258上，以及对导电连接件258进行回焊以将第二电子管芯106与混合重布线结构104物理且电性地耦合。
此外，一对光子管芯112附接到混合重布线结构104的第二侧，与衬底244相对。导电连接件258还用以将光子管芯112的管芯连接件134附接到混合重布线结构104的导线214。第一光子管芯112接近于集成电路封装102附接且电性耦合到所述集成电路封装102。导线214可将集成电路封装102电性耦合到第一光子管芯112。第二光子管芯112接近于第二电子管芯106附接且电性耦合到所述第二电子管芯106。导线214可将第二电子管芯106电性耦合到第二光子管芯112。
在一些实施例中，底填充料260形成为包围导电连接件258。底填充料260可减小应力且保护由对导电连接件258的回焊产生的接合部。底填充料260可在附接集成电路封装102和电子管芯106之后通过毛细流动工艺形成，或可在附接第二集成电路封装102和电子管芯106之前通过合适的沉积方法形成。底填充料260可由能够进行光传输的聚合物形成，如液体光学透明粘合剂(liquid optically clear adhesive；LOCA)，如丙烯基封端的氢化聚合物。在一些实施例中，单层底填充料260在多个邻近装置下方形成。举例来说，第一层底填充料260可在集成电路封装102和其相应光子管芯112下方形成，且第二层底填充料260可在电子管芯106和其相应光子管芯112下方形成。底填充料260可部分或完全地安置在波导114上方。
在图24中，外部连接件108在UBM 252B上形成。外部连接件108可以是球栅阵列(BGA)连接件、焊球、金属柱、受控塌陷芯片连接(C4)凸块、微凸块或类似物。外部连接件108可包含导电材料，如焊料、铜、铝、金、镍、银、钯、锡、类似物或其组合。在一些实施例中，外部连接件108通过蒸镀、电镀、印刷、焊料转移、植球或类似操作在UBM 252B上初始地形成可回焊材料层而形成。一旦已在UBM 252B上形成可回焊材料层，便可执行回焊以便使材料成形为所要凸块形状。
图25A示出来自图24的区域25的详细视图，其绘示根据一些实施例的混合封装组件100的额外构件。集成电路封装102接近第一光子管芯112附接。举例来说，集成电路封装102安置为与第一光子管芯112相隔距离D1，所述距离D1可在约0.5毫米到约5毫米的范围内。电子管芯106接近第二光子管芯112附接。举例来说，电子管芯106安置为与第二光子管芯112相隔距离D2，所述距离D2可在约0.5毫米到约5毫米的范围内。光子管芯112间隔距离D3，所述距离D3可在约1毫米到约150毫米的范围内。距离D3大于距离D1和距离D2。
光子管芯112在混合重布线结构104形成之后附接，且因此与混合重布线结构104分离(例如安置在混合重布线结构104外部)。因此，光子管芯112的光学I/O端口136可与波导114物理分离。举例来说，光学I/O端口136可以距离D4与波导114分离，所述距离D4可小于约10微米。底填充料260可(或可不)安置在光学I/O端口136与波导114之间的间隙中。
图25B示出来自图24的区域25的详细视图，其绘示根据一些其它实施例的混合封装组件100的额外构件。在此实施例中，光学I/O端口136与波导114直接物理接触。因此，在光学I/O端口136与波导114之间不安置底填充料260。
图26示出根据一些实施例的包含混合封装组件100的系统。在此实施例中，使用外部连接件108将混合封装组件100安装到封装衬底300。封装衬底300可由半导体材料制成，如硅、锗、钻石或类似物。或者，也可使用化合物材料，如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、这些化合物材料的组合以及类似物。另外，封装衬底300可以是SOI衬底。一般来说，SOI衬底包含如外延硅、锗、硅锗、SOI、SGOI或其组合的半导体材料层。在一个替代实施例中，封装衬底300基于绝缘芯，如玻璃纤维增强的树脂芯。一种实例芯材料是玻璃纤维树脂，如FR4。芯材料的替代方案包含双马来酰亚胺-三嗪BT树脂，或替代地其它PCB材料或膜。如ABF的积聚膜或其它层压物可用于封装衬底300。
封装衬底300可包含有源装置和无源装置(未示出)。如本领域的普通技术人员将认识到，可使用如晶体管、电容器、电阻器、这些装置的组合以及类似物的广泛多种装置来产生对装置堆叠的设计的结构性和功能性要求。所述装置可使用任何合适的方法来形成。
封装衬底300还可包含金属化层和通孔(未示出)以及在金属化层和路径上方的接合衬垫302。金属化层可在有源装置和无源装置上方形成，且设计成连接各种装置以形成功能电路。金属化层可由具有使导电材料层互连的通孔的介电(例如低k介电材料)与导电材料(例如铜)的交替层形成，且可通过任何合适的工艺(如沉积、镶嵌、双重镶嵌或类似物)形成。在一些实施例中，封装衬底300基本上不含有源装置和无源装置。
在一些实施例中，对外部连接件108进行回焊以将混合封装组件100附接到接合衬垫302。外部连接件108将封装衬底300(包含封装衬底300中的金属化层)电性且/或物理地耦合到混合封装组件100。在一些实施例中，无源装置(例如表面安装装置(surface mountdevice；SMD)，未示出)可在安装于封装衬底300上之前附接到混合封装组件100(例如接合到接合衬垫302)。在此类实施例中，无源装置可与外部连接件108接合到混合封装组件100的相同表面。
在用将混合封装组件100附接到封装衬底300之后所剩余的环氧树脂焊剂的环氧树脂部分中的至少一些对外部连接件108进行回焊之前，外部连接件108可具有形成于其上的环氧树脂焊剂(未示出)。此剩余环氧树脂部分可充当底填充料以减小应力且保护由对外部连接件108进行回焊所产生的接合部。在一些实施例中，底填充料(未示出)可在混合封装组件100与封装衬底300之间且包围外部连接件108形成。底填充料可在附接混合封装组件100之后通过毛细流动工艺形成，或可在附接混合封装组件100之前通过合适的沉积方法形成。
图27示出根据一些其它实施例的包含混合封装组件100的系统。在此实施例中，省略衬底244和包封体254。替代地，使用充当外部连接件108的导电连接件242将混合封装组件100安装到封装衬底300。
还可包含其它构件和工艺。举例来说，可包含测试结构以辅助对3D封装或三维晶片(3DIC)装置的校验测试。测试结构可包含例如形成于重布线层中或衬底上的测试衬垫，所述衬底允许对3D封装或3DIC的测试、探针和/或探针卡的使用以及类似操作。可对中间结构以及最终结构执行校验测试。另外，本文中所公开的结构和方法可与并有已知良好管芯的中间校验的测试方法结合使用以增加良率并降低成本。
实施例可实现优势。使用波导114来进行长信号连接可避免或减少插入损耗和/或那些连接上的串扰。因而可增大数据传输速率，且因而可减少延迟。此外，光子构件的使用减少了混合重布线结构104中所形成的导电构件的总量。可减少信号路由的量，进而增加混合封装组件100的制造产率。通过在混合重布线结构104形成之后附接光子管芯112，可改善混合封装组件100的制造灵活性。举例来说，可选择不同光子管芯112来进行附接而不对混合重布线结构104进行重新设计。
在一实施例中，一种混合封装组件包含：第一介电层；第一光子管芯，邻近第一介电层的第一侧安置；第二光子管芯，邻近第一介电层的第一侧安置；波导，将第一光子管芯光学耦合到第二光子管芯，所述波导安置在第一介电层与第一光子管芯之间以及第一介电层与第二光子管芯之间；第一集成电路管芯，邻近第一介电层的第一侧安置；第二集成电路管芯，邻近第一介电层的第一侧安置；导电构件，穿过第一介电层且沿第一介电层的第二侧延伸，所述导电构件将第一光子管芯电性耦合到第一集成电路管芯，所述导电构件将第二光子管芯电性耦合到第二集成电路管芯；以及第二介电层，邻近第一介电层的第二侧安置。
在所述混合封装组件的一些实施例中，波导包含：芯层，包含具有第一折射率的第一材料；以及芯层周围的包覆层，所述包覆层包含具有第二折射率的第二材料，第二折射率小于第一折射率。在所述混合封装组件的一些实施例中，波导以第一距离与第一光子管芯的光学端口且与第二光子管芯分离，第一距离在0微米到10微米的范围内。在一些实施例中，混合封装组件更包含：底填充料，安置在波导与光学端口之间，所述底填充料是液体光学透明粘合剂。在所述混合封装组件的一些实施例中，第一介电层包含光敏聚合物，且第二介电层包含模塑化合物。在一些实施例中，混合封装组件更包含：导通孔，延伸穿过第二介电层以将导电构件电性耦合；以及导线，沿第二介电层的主表面延伸，所述导线包含接触导通孔的晶种层。在所述混合封装组件的一些实施例中，第一介电层包含光敏聚合物，且第二介电层包含光敏聚合物。在一些实施例中，混合封装组件更包含：金属化图案，具有延伸穿过第二介电层的第一部分和沿第二介电层的主表面延伸的第二部分，在金属化图案的第一部分与第二部分之间不安置晶种层。在一些实施例中，混合封装组件更包含：集成电路封装，包含：电子重布线结构，所述电子重布线结构物理且电性地耦合到导电构件，第一集成电路管芯是第一电子管芯，第一电子管芯安置在电子重布线结构上，第二集成电路管芯是第二电子管芯。在所述混合封装组件的一些实施例中，波导具有平行于第一介电层的主表面延伸的平直部分和与第一介电层的主表面形成锐角的倾斜部分，所述锐角在20度到30度的范围内，所述倾斜部分将平直部分光学耦合到第一光子管芯和第二光子管芯。
在一实施例中，一种混合封装组件的制作方法包含：在载体衬底上方形成波导；在所述波导上方和周围沉积第一介电层；对来自所述第一介电层的第一侧的导线进行镀覆；去除所述载体衬底以暴露所述波导及所述第一介电层的第二侧；形成延伸穿过所述第一介电层导电构件以耦合所述导线的导电构件；将第一光子管芯及第二光子管芯附接到所述波导及所述第一介电层的第二侧；以及将第一集成电路管芯及第二集成电路管芯附接到所述导电构件及第所述一介电层的所述第二侧。
在所述制作方法的一些实施例中，形成所述波导包含：在所述载体衬底上方形成第一波导包覆层，所述第一波导包覆层包含具有第一折射率的第一波导材料；在所述第一波导包覆层上方形成波导芯层，所述波导芯层包含具有第二折射率的第二波导材料，所述第二折射率大于所述第一折射率；以及在所述波导芯层上方形成第二波导包覆层，所述第二波导包覆层包含所述第一波导材料。在所述制作方法的一些实施例中，形成所述第一波导包覆层包含印刷所述第一波导包覆层；形成所述波导芯层包含印刷所述波导芯层；且形成所述第二波导包覆层包含印刷所述第二波导包覆层。在所述制作方法的一些实施例中，形成所述第一波导包覆层包含使所述第一波导材料沉积及对所述第一波导材料进行蚀刻以形成所述第一波导包覆层；形成所述波导芯层包含使所述第二波导材料沉积和对所述第二波导材料进行蚀刻以形成所述波导芯层；且形成所述第二波导包覆层包含使所述第一波导材料沉积及对所述第一波导材料进行蚀刻以形成所述第二波导包覆层。在一些实施例中，所述制作方法更包含：对来自所述导线的导通孔进行镀覆；以及在所述导线上方和导通孔周围沉积第二介电层。在一些实施例中，所述制作方法更包含：在所述导线上方沉积第二介电层；以及形成金属化图案，所述金属化图案具有沿所述第二介电层的主表面延伸的线路部分和延伸穿过所述第二介电层以耦合所述导线的通孔部分。在一些实施例中，所述制作方法更包含：在所述第一介电层与所述第一光子管芯之间以及所述第一介电层与所述第二光子管芯之间形成底填充料，所述底填充料是液体光学透明粘合剂。
在一实施例中，一种混合封装组件的制作方法包含：形成混合重布线结构，包含：在载体衬底上形成波导；在所述波导上方和周围沉积第一介电层；形成穿过所述第一介电层且沿所述第一介电层的所述主表面延伸的导电构件；以及在所述导电构件和所述第一介电层的主表面上方沉积第二介电层；在形成混合重布线结构之后，将第一光子管芯及第二光子管芯附接到所述混合重布线结构，所述第一光子管芯通过所述波导光学耦合到所述第二光子管芯；以及将第一集成电路管芯及第二集成电路管芯附接到所述混合重布线结构，所述第一集成电路管芯通过所述导电构件电性耦合到所述第一光子管芯，所述第二集成电路管芯通过所述导电构件电性耦合到所述第二光子管芯。
在一些实施例中，所述制作方法更包含：将有机衬底附接到所述混合重布线结构，所述有机衬底包含电性耦合所述混合重布线结构的所述导电构件的电子重布线结构。在所述制作方法的一些实施例中，所述第一集成电路管芯安置为与所述第一光子管芯相隔第一距离，所述第二集成电路管芯安置为与所述第二光子管芯相隔第二距离，所述第一光子管芯安置为与所述第二光子管芯相隔第三距离，且第所述三距离大于所述第一距离和所述第二距离。
前文概述若干实施例的特征以使得本领域的技术人员可以更好地理解本公开的各方面。所属领域中的技术人员应了解，其可以易于使用本公开作为设计或修改用于实施本文中所介绍的实施例的相同目的和/或实现相同优势的其它工艺和结构的基础。所属领域中的技术人员还应认识到，此类等效构造并不脱离本公开的精神和范围，且其可在不脱离本公开的精神和范围的情况下在本文中进行各种改变、替代以及更改。

Claims (1)

1.一种混合封装组件，其特征在于，包括：
第一介电层；
第一光子管芯，邻近所述第一介电层的第一侧安置；
第二光子管芯，邻近所述第一介电层的所述第一侧安置；
波导，将所述第一光子管芯光学耦合到所述第二光子管芯，所述波导安置在所述第一介电层与所述第一光子管芯之间以及所述第一介电层与所述第二光子管芯之间；
第一集成电路管芯，邻近所述第一介电层的所述第一侧安置；
第二集成电路管芯，邻近所述第一介电层的所述第一侧安置；
导电构件，穿过所述第一介电层且沿所述第一介电层的第二侧延伸，所述导电构件将所述第一光子管芯电性耦合到所述第一集成电路管芯，所述导电构件将所述第二光子管芯电性耦合到所述第二集成电路管芯；以及
第二介电层，邻近所述第一介电层的所述第二侧安置。
CN201910836161.7A 2019-06-14 2019-09-05 混合封装组件 Pending CN112086445A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/441,343 US10867982B1 (en) 2019-06-14 2019-06-14 Hybrid integrated circuit package and method
US16/441,343 2019-06-14

Publications (1)

Publication Number Publication Date
CN112086445A true CN112086445A (zh) 2020-12-15

Family

ID=73734302

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910836161.7A Pending CN112086445A (zh) 2019-06-14 2019-09-05 混合封装组件

Country Status (3)

Country Link
US (3) US10867982B1 (zh)
CN (1) CN112086445A (zh)
TW (1) TW202046474A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024077908A1 (zh) * 2022-10-09 2024-04-18 深南电路股份有限公司 一种光电共封装结构及其制作方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10867982B1 (en) * 2019-06-14 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid integrated circuit package and method
US20230413586A1 (en) * 2020-01-20 2023-12-21 Monolithic 3D Inc. 3d semiconductor devices and structures with electronic circuit units
KR20220042705A (ko) * 2020-09-28 2022-04-05 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US11817380B2 (en) * 2021-02-26 2023-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of forming same

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10598875B2 (en) * 2018-12-14 2020-03-24 Intel Corporation Photonic package with a bridge between a photonic die and an optical coupling structure
US10867982B1 (en) * 2019-06-14 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid integrated circuit package and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024077908A1 (zh) * 2022-10-09 2024-04-18 深南电路股份有限公司 一种光电共封装结构及其制作方法

Also Published As

Publication number Publication date
US20230215854A1 (en) 2023-07-06
US20210134776A1 (en) 2021-05-06
US10867982B1 (en) 2020-12-15
TW202046474A (zh) 2020-12-16
US11605621B2 (en) 2023-03-14
US20200395347A1 (en) 2020-12-17

Similar Documents

Publication Publication Date Title
US10937736B2 (en) Hybrid integrated circuit package and method
KR102397032B1 (ko) 반도체 디바이스 및 제조 방법
US11605621B2 (en) Hybrid integrated circuit package and method
US11417698B2 (en) Semiconductor package and method of forming the same
KR20190005728A (ko) 이중 측면의 금속 라우팅을 갖는 반도체 패키지
US11935837B2 (en) Photonics integrated circuit package
US20220328552A1 (en) Semiconductor package and method of forming the same
KR20210053233A (ko) 반도체 패키지 및 제조 방법
CN112864119A (zh) 集成电路封装件及其形成方法
KR20210047225A (ko) 반도체 장치 및 제조 방법
US11747563B2 (en) Photonic semiconductor device and method of manufacture
CN112558240A (zh) 封装总成及其制造方法
JP2024516204A (ja) フォトニック集積回路を集積するファンアウトモジュール
US11961814B2 (en) Integrated circuit package and method
US20240077669A1 (en) Integrated circuit package and method of forming same
US20240113056A1 (en) Semiconductor device and methods of manufacture
CN117457625A (zh) 封装件、半导体封装件及其形成方法
CN117497516A (zh) 高密度光电集成的三维封装结构及其制作方法
KR20230117690A (ko) 집적 회로 패키지 및 이를 형성하는 방법
CN117203562A (zh) 集成光子集成电路的扇出模块
CN113053759A (zh) 制造半导体器件的方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20201215