WO2024077908A1 - 一种光电共封装结构及其制作方法 - Google Patents

一种光电共封装结构及其制作方法 Download PDF

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Publication number
WO2024077908A1
WO2024077908A1 PCT/CN2023/087987 CN2023087987W WO2024077908A1 WO 2024077908 A1 WO2024077908 A1 WO 2024077908A1 CN 2023087987 W CN2023087987 W CN 2023087987W WO 2024077908 A1 WO2024077908 A1 WO 2024077908A1
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layer
optical waveguide
chip
integrated chip
optoelectronic integrated
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PCT/CN2023/087987
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English (en)
French (fr)
Inventor
朱凯
黄立湘
邵广俊
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深南电路股份有限公司
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Publication of WO2024077908A1 publication Critical patent/WO2024077908A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/111—Manufacture and pre-treatment of the bump connector preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the field of chip packaging technology, and in particular to an optoelectronic co-packaging structure and a manufacturing method thereof.
  • the packaging structure of multiple chips mainly provides signal lines for signal transmission between chips through the redistributed layer (RDL).
  • RDL provides both high-density signal lines for interconnection between chips and signal lines for fanning out of chips to the external PCB. Since many signal lines in the RDL are densely interconnected, the lines inside the packaging structure are more complicated. In addition, the dielectric constant of the insulating medium in the RDL and the attenuation effect of the transmission signal between the high-density interconnected signal lines will also limit the signal transmission speed between chips, resulting in a slower signal transmission speed between chips.
  • the present application provides a method for manufacturing an optoelectronic co-packaging structure, comprising:
  • At least a first optoelectronic integrated chip and a second optoelectronic integrated chip are flipped and plastic-sealed on the optical waveguide layer side of the rewiring layer, the first optoelectronic integrated chip transmits optical signals with the second optoelectronic integrated chip through the optical waveguide layer, and the first optoelectronic integrated chip and the second optoelectronic integrated chip are connected to the flip-chip pads of the rewiring layer;
  • Ball planting is performed on the ball planting pad side of the redistribution layer.
  • the manufacturing method of the optoelectronic co-packaging structure of the present application integrates an optical waveguide layer in a rewiring layer, flips and plastic-seales a first optoelectronic integrated chip and a second optoelectronic integrated chip on the optical waveguide layer side of the rewiring layer, enables the first optoelectronic integrated chip and the second optoelectronic integrated chip to communicate through the optical waveguide layer, and effectively improves the transmission rate between chips by utilizing the high bandwidth of optical transmission; and effectively simplifies the complex circuits inside the packaging structure by replacing a part of the signal transmission lines between the chips with the optical waveguide layer.
  • providing a rewiring layer with an optical waveguide layer integrated on one side includes:
  • the rewiring layer is manufactured, and the rewiring layer includes: an electrical interconnection structure and a ball pad embedded in the insulating dielectric layer, one end of the electrical interconnection structure is connected to the ball pad, and the other end is connected to the flip-chip pad; the insulating dielectric layer has a groove structure to integrate the optical waveguide layer.
  • manufacturing an optical waveguide layer on the temporary bonding layer comprises:
  • the light reflecting layer is manufactured on the two inclined surfaces of the light waveguide layer, including: sputtering a metal layer, selectively etching the metal layer, and retaining the metal layer on the two inclined surfaces of the light waveguide layer to obtain the light reflecting layer.
  • providing a rewiring layer with an optical waveguide layer integrated on one side includes:
  • the rewiring layer is manufactured, and the rewiring layer includes: an electrical interconnection structure and a ball pad embedded in the insulating dielectric layer, one end of the electrical interconnection structure is connected to the ball pad, and the other end is connected to the flip-chip pad; the insulating dielectric layer has a groove structure to integrate the optical waveguide layer.
  • manufacturing the optical waveguide layer on the temporary bonding layer includes:
  • the method of manufacturing the flip-chip pad of the rewiring layer and the light reflecting layer on the two inclined surfaces of the optical waveguide layer comprises:
  • the metal layer is sputtered, and the metal layer is selectively etched to retain the metal layer on the two inclined surfaces of the optical waveguide layer and the metal layer at a preset position on the temporary bonding layer, so as to obtain the light reflecting layer and the flip-chip pad.
  • the first optoelectronic integrated chip and the second optoelectronic integrated chip are flipped and sealed on the optical waveguide layer side of the rewiring layer.
  • Chips including:
  • the first optoelectronic integrated chip includes a first electronic chip area and a first photonic chip area
  • the second optoelectronic integrated chip includes a second electronic chip area and a second photonic chip area
  • the first photonic chip area and the second photonic chip area transmit light through the optical waveguide layer
  • the first electronic chip area and the second electronic chip area are connected to the flip-chip pad of the rewiring layer through a bump.
  • an optoelectronic co-packaging structure comprising:
  • a rewiring layer being integrated with an optical waveguide layer
  • At least a first optoelectronic integrated chip and a second optoelectronic integrated chip are flip-chipped on the optical waveguide layer side of the rewiring layer, the first optoelectronic integrated chip performs optical transmission with the second optoelectronic integrated chip through the optical waveguide layer, and the first optoelectronic integrated chip and the second optoelectronic integrated chip are respectively connected to the flip-chip pads of the rewiring layer, and the flip-chip pads are located on the optical waveguide layer side of the rewiring layer;
  • a ball planting pad is arranged on the ball planting pad side of the rewiring layer, and a solder ball is arranged on the ball planting pad.
  • the optoelectronic co-packaging structure of the present application is provided with an optical waveguide layer in the rewiring layer, so that the first optoelectronic integrated chip and the second optoelectronic integrated chip located on the optical waveguide layer side of the rewiring layer communicate through the optical waveguide layer, and the high bandwidth of optical transmission is utilized to effectively improve the transmission rate between the chips; at the same time, the optical waveguide layer can adopt the same manufacturing technology as the rewiring layer, which simplifies the processing flow of the packaging structure and improves the integration of the packaging structure.
  • the optical waveguide layer comprises:
  • An optical waveguide lower cladding, an optical waveguide circuit and an optical waveguide upper cladding wherein the optical waveguide lower cladding is located at the bottom of the optical waveguide layer, and a window for forming an optical waveguide circuit channel is opened at a preset position of the optical waveguide lower cladding; the optical waveguide circuit is arranged above the optical waveguide lower cladding and in the optical waveguide circuit channel; the optical waveguide upper cladding is arranged above the optical waveguide circuit and wraps the optical waveguide circuit; the optical waveguide circuit is used for light transmission between the first optoelectronic integrated chip and the second optoelectronic integrated chip;
  • One end of the optical waveguide layer has a first inclined surface with a preset angle, and a first light reflecting layer is disposed on the surface of the first inclined surface;
  • the other end of the optical waveguide layer has a second inclined surface with a preset angle, and a second light reflecting layer is arranged on the surface of the second inclined surface.
  • the optoelectronic co-packaging structure further includes:
  • a plastic sealing layer wherein the plastic sealing layer is provided with two grooves, and the first optoelectronic integrated chip and the second optoelectronic integrated chip are respectively provided in one groove;
  • a first filling layer is provided between the first optoelectronic integrated chip and the lower surface of the rewiring layer, and a first bump is provided in the first filling layer, and the first bump is used for flip-mounting the first optoelectronic integrated chip;
  • a second filling layer is arranged between the second optoelectronic integrated chip and the lower surface of the rewiring layer, and a second bump is arranged in the second filling layer.
  • the second bump is used for flip-mounting the second optoelectronic integrated chip.
  • the rewiring layer includes:
  • An electrical interconnection structure and a ball pad are embedded in the insulating dielectric layer, one end of the electrical interconnection structure is connected to the ball pad, and the other end is connected to the flip-chip pad; the insulating dielectric layer has a groove structure with an inclined surface to integrate the optical waveguide layer.
  • FIG1 is a flow chart of a method for manufacturing an optoelectronic co-packaging structure provided in one embodiment of the present application
  • FIG2-1 is a schematic diagram of a redistribution layer structure provided in an embodiment of the present application.
  • FIG2-2 is a schematic diagram of a flip-chip optoelectronic integrated chip on one side of a redistribution layer provided in one embodiment of the present application;
  • FIG2-3 is a schematic diagram of a ball implantation on the other side of a redistribution layer provided in an embodiment of the present application;
  • FIG. 3 is a flow chart of a first method for manufacturing a rewiring layer having an optical waveguide layer integrated on one side provided in an embodiment of the present application;
  • FIG4-1 is a schematic diagram of coating a temporary bonding layer on a carrier provided in an embodiment of the present application
  • FIG4-2 is a schematic diagram of a flip-chip pad pattern provided in an embodiment of the present application.
  • FIG4-3 is a schematic diagram of manufacturing a lower cladding layer of an optical waveguide provided in an embodiment of the present application.
  • FIG4-4 is a schematic diagram of a circuit for manufacturing an optical waveguide provided in an embodiment of the present application.
  • FIG. 4-5 is a schematic diagram of manufacturing an upper cladding layer of an optical waveguide provided in an embodiment of the present application
  • 4-6 are schematic diagrams of processing the inclined surface of the optical waveguide layer provided in one embodiment of the present application.
  • 4-7 are schematic diagrams of manufacturing a light reflection layer provided in an embodiment of the present application.
  • 4-8 are schematic diagrams of manufacturing a rewiring layer provided in an embodiment of the present application.
  • 4-9 is a schematic diagram of attaching a temporary carrier to the ball implanting side of the redistribution layer provided in one embodiment of the present application;
  • FIGS. 4-10 are schematic diagrams of flip-chip optoelectronic integrated chips and plastic packaging provided in one embodiment of the present application.
  • 4-11 is a schematic diagram of ball planting provided in an embodiment of the present application.
  • FIG. 5 is a flow chart of a second method for manufacturing a rewiring layer having an optical waveguide layer integrated on one side provided in an embodiment of the present application;
  • FIG6-1 is a schematic diagram of a processed optical waveguide layer slope provided in an embodiment of the present application.
  • FIG6-2 is a schematic diagram of manufacturing a light reflection layer and a flip-chip pad provided in an embodiment of the present application.
  • FIG7 is a schematic diagram of a first optoelectronic co-packaging structure provided in an embodiment of the present application.
  • FIG8 is a schematic diagram of a second optoelectronic co-packaging structure provided in an embodiment of the present application.
  • a method for manufacturing an optoelectronic co-packaging structure as shown in FIG. 1 comprising:
  • Step S100 providing a rewiring layer with an optical waveguide layer integrated on one side.
  • a structure of a redistribution layer 7 is provided, and an optical waveguide layer 6 is integrated on one side of the redistribution layer 7 .
  • Step S200 Flip-chip and plastic-encapsulate the first optoelectronic integrated chip and the second optoelectronic integrated chip on the optical waveguide layer side of the re-wiring layer, the first optoelectronic integrated chip is used to connect the second optoelectronic integrated chip through the optical waveguide layer, and the first optoelectronic integrated chip and the second optoelectronic integrated chip are used to connect the flip-chip pads of the re-wiring layer.
  • the first optoelectronic integrated chip 2 is flipped on the side of the rewiring layer 7 where the optical waveguide layer 6 is integrated through the first flip-chip pad 711
  • the second optoelectronic integrated chip 3 is flipped on the side of the rewiring layer 7 where the optical waveguide layer 6 is integrated through the second flip-chip pad 712
  • the first optoelectronic integrated chip 2 is connected to one end of the optical waveguide layer 6, and the second optoelectronic integrated chip 3 is connected to the other end of the optical waveguide layer 6, so that
  • the first optoelectronic integrated chip 2 and the second optoelectronic integrated chip 3 are able to perform optical communication through the optical waveguide layer 6; then the first optoelectronic integrated chip 2 and the second optoelectronic integrated chip 3 are plastic-sealed by the plastic sealing material 9; the optoelectronic integrated chip can be completely plastic-sealed or a part of the surface of the optoelect
  • the number of flip-chip pads and optoelectronic integrated chips is not limited to two, and the number of flip-chip pads can be set according to actual needs.
  • Step S300 performing ball planting on the ball planting pad side of the redistribution layer.
  • balls are planted on the ball planting pads 715 on the other side of the re-wiring layer 7.
  • the balls are solder balls 8, and the number of balls can be set according to actual needs.
  • the manufacturing method of the optoelectronic co-packaging structure of the present embodiment integrates an optical waveguide layer in the rewiring layer, flips and plastic-seales the first optoelectronic integrated chip and the second optoelectronic integrated chip on the optical waveguide layer side of the rewiring layer, enables the first optoelectronic integrated chip and the second optoelectronic integrated chip to communicate through the optical waveguide layer, and effectively improves the transmission rate between chips by utilizing the high bandwidth of optical transmission; and effectively simplifies the complex circuits inside the packaging structure by transmitting signals between the first optoelectronic integrated chip and the second optoelectronic integrated chip through the optical waveguide layer.
  • a method for manufacturing an optoelectronic co-packaging structure is provided. Based on the method in FIG. 1 , a method for manufacturing a redistribution layer having an optical waveguide layer integrated on one side provided in this embodiment is shown in FIG. 3 , and the method comprises:
  • Step S101 providing a temporary carrier with a temporary bonding layer coated on its surface.
  • a temporary bonding layer 200 is fabricated on a hard carrier 100, wherein the hard carrier 100 may be round or square; if the hard carrier 100 is round, the material is one of silicon, glass, and stainless steel; if the hard carrier 100 is square, the material is one of glass, stainless steel, ceramic, and glass fiber reinforced organic resin; the temporary bonding layer 200 may be in liquid or film form, and when in liquid form, it needs to be fabricated by coating, and when in film form, it may be fabricated by rolling, hot pressing, vacuum lamination, and the like; the temporary bonding layer 200 may be thermosensitive, photosensitive, chemically dissolving, mechanically separating, and the like; as a preferred embodiment, a photosensitive temporary bonding layer is selected, and the photosensitive temporary bonding layer can only be used with a glass carrier; fabricating the optical waveguide layer directly on a temporary carrier with high flatness can significantly improve the exposure capability, improve the fineness of the optical waveguide circuit, and help improve the relative position accuracy between the optical waveguide circuit and the bump
  • Step S102 making a flip-chip pad of the rewiring layer on the temporary bonding layer.
  • the semi-additive method is used to form the patterns of the first flip-chip pad 711 and the second flip-chip pad 712.
  • the specific method is as follows: first, a seed layer is sputtered to form a seed layer, and then a first preset photoresist pattern is formed according to the positions of the first flip-chip pad 711 and the second flip-chip pad 712, and copper is electroplated on the first photoresist pattern, and then the first preset photoresist pattern is removed, and the seed layer is etched to obtain the first flip-chip pad 711 and the second flip-chip pad 712; in this embodiment, the seed layer is formed by sputtering, and then the seed layer is formed by sputtering.
  • the layer is preferably titanium/copper, and the photoresist is preferably photoresist, or it can be a dry film; the flip-chip pad is made by using the photoresist pattern, and the position of the flip-chip pad can be adjusted at will according to design requirements, and the production is more flexible.
  • Step S103 fabricating an optical waveguide layer on the temporary bonding layer, and fabricating inclined surfaces at both ends of the optical waveguide layer.
  • a specific method of manufacturing an optical waveguide layer on a temporary bonding layer and manufacturing inclined surfaces at both ends of the optical waveguide layer is as follows:
  • Step S1031 making an alignment target for the optical waveguide layer on the temporary bonding layer.
  • an alignment target of the optical waveguide layer is made at a preset position on the temporary bonding layer 200 , and the position of the entrance and exit of the optical waveguide line of the optical waveguide layer is determined according to the position of the alignment target, thereby making the entrance and exit of the optical waveguide line.
  • the first flip-chip pad 711 and the second flip-chip pad 712 may be used as alignment targets for the optical waveguide layer, and the positions of the entrances and exits of the optical waveguide path of the optical waveguide layer may be determined, thereby manufacturing the entrances and exits of the optical waveguide path.
  • Step S1032 using the alignment target as a reference, manufacturing an optical waveguide lower cladding, and opening a window at a preset position of the optical waveguide lower cladding to form an optical waveguide line channel.
  • an optical waveguide lower cladding 61 is manufactured, and a window is opened at a preset position of the lower cladding to form a channel for the optical waveguide line 62.
  • the specific manufacturing process is as follows: the optical waveguide lower cladding 61 is coated, and the excess lower cladding is selectively removed based on a second preset photoresist pattern; and the optical waveguide lower cladding 61 selectively opens a window at a preset position to provide a channel for light to enter and exit the optical waveguide line 62; in this embodiment, if the hard carrier is circular, spin coating is preferred; if the hard carrier is square, slit coating or spraying is preferred; as another embodiment, the optical waveguide lower cladding 61 can also be manufactured by 3D printing; the optical waveguide lower cladding 61 can shield the lower surface of the optical waveguide line 62.
  • Step S1033 fabricating an optical waveguide circuit on the optical waveguide circuit channel and above the optical waveguide lower cladding.
  • An optical waveguide circuit 62 is manufactured at the window position of the lower cladding 61 and above the optical waveguide lower cladding.
  • the specific manufacturing process is: coating the optical waveguide, and selectively removing excess optical waveguides based on a third preset photoresist pattern, and only retaining the optical waveguides at the preset position; if the hard carrier is circular, spin coating is preferred, and if the hard carrier is square, slit coating or spraying is preferred; as another embodiment, the optical waveguide circuit 62 can also be manufactured by 3D printing; the optical waveguide circuit 62 can provide an optical channel for signal transmission between optoelectronic integrated chips.
  • Step S1034 fabricating an optical waveguide upper cladding layer above the optical waveguide circuit to form an optical waveguide layer.
  • an optical waveguide upper cladding layer 63 is formed above the optical waveguide circuit 62 to form an optical waveguide layer.
  • the specific process is as follows: coating the optical waveguide upper cladding layer 63, and selectively removing the excess optical waveguide upper cladding layer 63 based on the fourth preset photoresist pattern, leaving only the upper cladding layer at the position of the optical waveguide circuit 62, and the optical waveguide upper cladding layer 63 completely wraps the optical waveguide circuit 62; if the hard carrier is circular, spin coating is preferred, and if the carrier is square, slit coating is preferred. Or spraying; as another embodiment, the optical waveguide upper cladding layer 63 can also be made by 3D printing; the optical waveguide upper cladding layer 63 can shield the upper surface of the optical waveguide line 62.
  • a first slope X1 and a second slope X2 are made at both ends of the optical waveguide layer.
  • the angles of the first slope X1 and the second slope X2 can be designed according to the light reflection requirements. As a preferred solution, the slope angle can be designed to be 45 degrees.
  • the nanoimprinting method is preferably used to make the slope, and mechanical grinding and laser cutting methods can also be used. If the material of the optical waveguide circuit, the material of the optical waveguide lower cladding and the optical waveguide upper cladding are photosensitive materials, gradient exposure can also be used to obtain edge slopes.
  • the slopes at both ends of the optical waveguide layer provide support surfaces for the subsequent production of the light reflection layer.
  • Step S104 making a light reflection layer on two inclined surfaces of the optical waveguide layer
  • a first light reflecting layer 64 and a second light reflecting layer 64_1 need to be made on the inclined surfaces at both ends so that light can be reflected and transmitted in the optical waveguide circuit.
  • the specific manufacturing process of the light reflecting layer is as follows: a metal layer is sputtered on the entire plate, and then a fifth preset photoresist pattern is made. According to the fifth preset photoresist pattern, the metal layer is selectively etched to retain only the metal layer near the inclined surfaces at both ends of the optical waveguide layer to obtain the first light reflecting layer 64 and the second light reflecting layer 64_1.
  • the metal layer is made of one of gold, silver and copper.
  • the light reflecting layer can provide a light reflecting surface for the optical waveguide circuit so that light can change the transmission direction in the optical waveguide circuit.
  • Step S105 making a rewiring layer, the rewiring layer comprising: an electrical interconnection structure and a ball pad embedded in the insulating dielectric layer, one end of the electrical interconnection structure is connected to the ball pad, and the other end is connected to the flip-chip pad; the insulating dielectric layer has a groove structure to integrate the optical waveguide layer.
  • a rewiring layer 7 is manufactured on the surface of the structure in FIG. 4-7 by a build-up method.
  • electrical interconnection pillars 714, copper lines 713 and ball pads 715 are manufactured.
  • the electrical interconnection pillars 714 and the copper lines constitute an electrical interconnection structure.
  • One end of the electrical interconnection structure is connected to the ball pad 715, and the other end is connected to the flip-chip pad 711.
  • a groove structure is provided in the insulating dielectric layer to integrate the optical waveguide layer.
  • the insulating dielectric layer in the rewiring layer can be silicon dioxide, photosensitive polyimide, Ajinomoto build-up film, etc., preferably photosensitive polyimide.
  • the copper lines in the rewiring layer are manufactured by a semi-additive method.
  • the rewiring layer can be designed with circuits for external electrical communication according to design requirements.
  • the groove structure of the insulating dielectric layer includes: a bottom surface and two inclined surfaces, wherein the bottom surface is located at the top of the groove, the two inclined surfaces are located at both ends of the groove, and the two inclined surfaces of the groove have the same width as the inclined surfaces at both ends of the optical waveguide layer.
  • the groove structure can be embedded in the optical waveguide layer, so that the upper cladding layer of the optical waveguide is bonded to the bottom surface, the lower cladding layer of the optical waveguide is bonded to the plastic packaging layer, and the inclined surfaces at both ends of the optical waveguide layer are bonded to the two inclined surfaces of the groove to fix the optical waveguide layer.
  • a method for manufacturing an optoelectronic co-packaging structure is provided. Based on the method in FIG. 1 , at least a first optoelectronic integrated chip and a second optoelectronic integrated chip are flipped and plastic-sealed on the optical waveguide layer side of the redistribution layer, including:
  • Step S201 flip-chipping at least a first optoelectronic integrated chip and a second optoelectronic integrated chip on the optical waveguide layer side of the rewiring layer.
  • a temporary carrier 8 is attached to the ball pad side of the redistribution layer, and the hard carrier on the optical waveguide layer side is removed; wherein, the method of removing the hard carrier depends on the type of temporary bonding layer glue, and if necessary, the residual temporary bonding glue needs to be cleaned.
  • thermocompression bonding is preferably used to flip the optoelectronic integrated chip. Flipping the optoelectronic integrated chip can reduce the package volume and increase the signal transmission rate.
  • Step S202 using a filling glue to fill the bottom of the first optoelectronic integrated chip and the second optoelectronic integrated chip.
  • An optical bottom filling glue is used to underfill the bottom of the first optoelectronic integrated chip 2 and the second optoelectronic integrated chip 3, and then the chips are encapsulated with a plastic encapsulation material; according to the size of the bumps of the optoelectronic integrated chip, an optical non-conductive film (NCF) can also be selected to achieve bottom filling; compression molding is preferably used for encapsulating the chip, and when a film-like plastic encapsulation material is used, vacuum lamination can also be used; filling the optoelectronic integrated chip with a filling glue can make the optoelectronic integrated chip packaging structure more stable.
  • NCF optical non-conductive film
  • the first optoelectronic integrated chip 2 includes a first electronic chip area 21 and a first photonic chip area 22
  • the second optoelectronic integrated chip 3 includes a second electronic chip area 31 and a second photonic chip area 32
  • the first photonic chip area 22 and the second photonic chip area 32 transmit light through the optical waveguide layer 6
  • the first electronic chip area 21 and the first photonic chip area 22 are connected to the flip-chip pad 711 of the rewiring layer 7 through the bump 41
  • the second electronic chip area 31 and the second photonic chip area 32 are connected to the flip-chip pad 712 of the rewiring layer 7 through the bump 51
  • the photonic chip area can transmit optical signals through the optical waveguide circuit, and the transmission rate is relatively high.
  • a method for manufacturing an optoelectronic co-packaging structure is provided. Based on the method in FIG. 1 , the embodiment provides a method for performing ball planting on the ball planting pad side of the redistribution layer, including:
  • the temporary carrier on the ball planting pad side is removed, and a ball is planted on the ball planting pad 715 of the redistribution layer 7.
  • the planted ball is a solder ball 8.
  • the number of plants can be set according to actual needs, and then the optoelectronic co-packaging structure is obtained by cutting according to the design parameters.
  • the solder ball can be welded to the external circuit to transmit electrical signals.
  • a method for manufacturing an optoelectronic co-packaging structure is provided. Based on the method in FIG. 1 , a method for manufacturing a redistribution layer having an optical waveguide layer integrated on one side provided in this embodiment is shown in FIG. 5 , and the method comprises:
  • Step S1001 providing a temporary carrier with a temporary bonding layer coated on its surface.
  • step S1001 is the same as step S101 in the second embodiment and will not be described again.
  • Step S1002 fabricating an optical waveguide layer on the temporary bonding layer, and fabricating inclined surfaces at both ends of the optical waveguide layer.
  • step S1002 is the same as step S103 in the second embodiment, and will not be described again.
  • Step S1003 making flip-chip pads of the rewiring layer and light reflecting layers on the inclined surfaces at both ends of the optical waveguide layer.
  • step S1001 and step S1002 an optical waveguide layer structure as shown in FIG6-1 is obtained, a metal layer is sputtered on the structure, the metal layer is selectively etched, the metal layer on the two inclined surfaces of the optical waveguide layer is retained, and the metal layer at a preset position on the temporary bonding layer is retained to obtain the light reflection layer and the flip-chip pad.
  • the specific process is as follows:
  • a metal seed layer 300 is sputtered on the entire plate, and the material of the metal seed layer is one of gold, silver, and copper; then a sixth preset photoresist pattern 400 is made, and the sixth preset photoresist pattern 400 reveals the positions of the first inclined surface 64, the second inclined surface 64_1, and the flip-chip pad at both ends of the optical waveguide layer; and copper electroplating is performed, and then the sixth preset photoresist pattern 400 is removed, and the metal seed layer is etched to obtain a metal layer on the first inclined surface 64 and the second inclined surface 64_1, which is a light reflecting layer, and the flip-chip pad.
  • the method for manufacturing a rewiring layer with an optical waveguide layer integrated on one side in this embodiment is different from the method for manufacturing a rewiring layer with an optical waveguide layer integrated on one side in FIG. 3 in that: in FIG. 3 , bumps are first manufactured on a temporary bonding layer, and the light reflection layers at both ends of the optical waveguide layer are manufactured by sputtering; whereas in this embodiment, an optical waveguide layer is first manufactured on a temporary bonding layer, and the light reflection layers at both ends of the optical waveguide layer and flip-chip pads are manufactured together by copper electroplating of a photoresist pattern.
  • the method of this embodiment uses fewer photoresist patterns and has a simpler manufacturing process.
  • Step S1004 making a rewiring layer, the rewiring layer comprising: an electrical interconnection structure and a ball pad embedded in the insulating dielectric layer, one end of the electrical interconnection structure is connected to the ball pad, and the other end is connected to the flip-chip pad; the insulating dielectric layer has a groove structure to integrate the optical waveguide layer.
  • step S1004 is the same as step S105 in the second embodiment, and will not be described again.
  • the steps after the optical waveguide layer is manufactured are the same as the steps after the optical waveguide layer is manufactured in the second embodiment, and will not be described in detail herein.
  • the method for manufacturing the optical waveguide structure of this embodiment can achieve the same effect as the method for manufacturing the optical waveguide structure in the second embodiment.
  • an optoelectronic co-packaging structure as shown in FIG. 7 the optoelectronic co-packaging structure comprising:
  • the rewiring layer 7 includes an optical waveguide layer 6, a first flip-chip pad 711, a second flip-chip pad 712, and a ball pad 715, wherein the first flip-chip pad 711 and the second flip-chip pad 712 are located on the optical waveguide layer side of the rewiring layer 7, and the ball pad 715 is located on the other side of the rewiring layer.
  • the optical waveguide layer can be rectangular or circular, or can be any other shape. Shape.
  • At least the first optoelectronic integrated chip 2 and the second optoelectronic integrated chip 3 are flip-chipped on the optical waveguide layer 6 side of the rewiring layer 7, the first optoelectronic integrated chip 2 is connected to the second optoelectronic integrated chip 3 through the optical waveguide layer 6, and the first optoelectronic integrated chip is connected to the first flip-chip pad 711, and the second optoelectronic integrated chip 3 is connected to the second flip-chip pad 712; a ball planting pad 715 is provided on the ball planting pad 715 side of the rewiring layer 7, and solder balls 8 are provided on the ball planting pad 715, and the number of solder balls 8 can be set according to design requirements.
  • the number of the optoelectronic integrated chip and the flip-chip pad is at least 2, which can be set according to actual needs.
  • the optoelectronic co-packaging structure of this embodiment has an optical waveguide layer arranged in the rewiring layer.
  • the optoelectronic integrated chip communicates electrically with the outside via flip-chip pads, ball implant pads and solder balls.
  • the first optoelectronic integrated chip and the second optoelectronic integrated chip located on the optical waveguide layer side of the rewiring layer communicate via the optical waveguide layer, utilizing the high bandwidth of optical transmission to effectively improve the transmission rate between chips.
  • an optoelectronic co-packaging structure as shown in Figure 8 which includes: a plastic packaging layer 1, a rewiring layer 7 and solder balls 8, wherein the rewiring layer 7 is arranged on the upper surface of the plastic packaging layer 1, and the solder balls 8 are arranged on the upper surface of the rewiring layer.
  • the rewiring layer 7 is provided with an optical waveguide layer 6, a first flip-chip pad 711, a second flip-chip pad 712, a ball pad 715 and an electrical interconnection structure 71, wherein the first flip-chip pad 711 and the second flip-chip pad 712 are located on the optical waveguide layer side of the rewiring layer 7, and the ball pad 715 is located on the other side of the rewiring layer, and the cross-section of the optical waveguide layer in the length direction is a trapezoid; the electrical interconnection structure and the ball pad are embedded in the insulating dielectric layer of the rewiring layer, one end of the electrical interconnection structure 71 is connected to the ball pad 715, and the other end is connected to the first flip-chip pad 711; the insulating dielectric layer has a groove structure with an inclined surface to integrate the optical waveguide layer 6.
  • the electrical interconnection structure 71 includes: an electrical interconnection column 714 and an electrical interconnection line 713 , wherein the electrical interconnection line 713 is connected to the flip-chip pad 711 and the ball-planting pad 715 respectively through the electrical interconnection column 714 .
  • the optical waveguide layer 6 includes: an optical waveguide lower cladding 61, an optical waveguide line 62 and an optical waveguide upper cladding 63, wherein the optical waveguide lower cladding 61 is located at the bottom of the optical waveguide layer 6, the optical waveguide upper cladding 63 is located at the top of the optical waveguide layer 6, the optical waveguide line 62 is located between the optical waveguide lower cladding 61 and the optical waveguide upper cladding 63, and the two ends of the optical waveguide line 62 form two optical entrances and exits of the optical waveguide line 62 on the lower surface of the optical waveguide lower cladding 61, forming an optical channel of the optical waveguide line 62, and the optical waveguide line 62 is used for light transmission between the first optoelectronic integrated chip 2 and the second optoelectronic integrated chip 3.
  • the optical waveguide line 62 includes: a first optical waveguide line branch 621, a second optical waveguide line branch 622 and a third optical waveguide line branch 623, wherein one end of the first optical waveguide line branch 621 serves as an optical inlet and outlet of the optical waveguide line 62, and the other end is connected to one end of the second optical waveguide line branch 622, and the other end of the second optical waveguide line branch 622 is connected to the One end of the third optical waveguide branch 623 and the other end of the third optical waveguide branch 623 serve as another light entrance and exit of the optical waveguide.
  • connection between the first optical waveguide wire branch 621 and the second optical waveguide wire branch 622 forms a first inclined surface 64 at a preset angle, and a first metal layer is arranged on the surface of the first inclined surface 64 to form a first light reflecting layer;
  • connection between the third optical waveguide wire branch 623 and the second optical waveguide wire branch 622 forms a second inclined surface 65 at a preset angle, and a second metal layer is arranged on the surface of the second inclined surface 65 to form a second light reflecting layer.
  • the first light reflecting layer and the second light reflecting layer can provide reflection surfaces for light, so that the light can change direction when propagating in the optical waveguide wire, thereby realizing optical communication between the first optoelectronic integrated chip 2 and the second optoelectronic integrated chip 3.
  • the preset angle ranges from 30 degrees to 60 degrees.
  • the preset angle of the first slope 64 and the preset angle of the second slope 64_1 can be set to the same angle or to different angles, depending on the specific setting of the optical transmission line.
  • the preset angle can be set to 45 degrees.
  • the plastic packaging layer 1 is provided with two grooves, and the first optoelectronic integrated chip 2 and the second optoelectronic integrated chip 3 are respectively arranged in one groove; the two grooves are grooves naturally formed after the first optoelectronic integrated chip 2 and the second optoelectronic integrated chip 3 are packaged.
  • a first filling layer 4 is arranged between the first optoelectronic integrated chip 2 and the lower surface of the rewiring layer 7, and a first bump 41 is arranged in the first filling layer 4.
  • the first bump 41 is used for flip-chipping the first optoelectronic integrated chip 2, and the first bump 41 is connected to the first flip-chip pad 711;
  • a second filling layer 5 is arranged between the second optoelectronic integrated chip 3 and the lower surface of the rewiring layer 7, and a second bump 51 is arranged in the second filling layer 5.
  • the second bump 51 is used for flip-chipping the second optoelectronic integrated chip 3, and the second bump 51 is connected to the second flip-chip pad 712; the filling layer is formed because the bump occupies a certain space, and the filling layer is filled with filling glue, which can fix the optoelectronic integrated chip and improve the packaging reliability.
  • the first optoelectronic integrated chip 2 includes a first electronic chip area 21 and a first photonic chip area 22
  • the second optoelectronic integrated chip 3 includes a second electronic chip area 31 and a second photonic chip area 32
  • the first electronic chip area 21 is connected to the first bump 41
  • the second electronic chip area 31 is connected to the second bump 51
  • the first photonic chip area 22 and the second photonic chip area 32 transmit light through the optical waveguide circuit 62, so that the first optoelectronic integrated chip 2 and the second optoelectronic integrated chip 3 can communicate optically through the optical waveguide circuit 62
  • the photonic chip area as the optical communication functional area of the optoelectronic integrated chip, can convert optical signals and electrical signals.
  • the optoelectronic co-packaging structure of this embodiment is provided with an optical waveguide layer, a flip-chip pad and an electrical interconnection structure in the rewiring layer.
  • the optoelectronic integrated chip can communicate electrically with the outside through the flip-chip pad and the electrical interconnection structure.
  • the first photon chip area of the first optoelectronic integrated chip and the second photon chip area of the second optoelectronic integrated chip can communicate optically through the optical waveguide circuit, and the high bandwidth of optical transmission is utilized to effectively improve the transmission rate between chips.
  • the optical waveguide layer effectively simplifies the packaging. Complex wiring inside the structure.

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Abstract

本申请公开了一种光电共封装结构及其制作方法，涉及芯片封装技术领域，该方法包括：提供一侧集成有光波导层的再布线层；在所述再布线层的光波导层侧倒装并塑封第一光电集成芯片和第二光电集成芯片，所述第一光电集成芯片通过所述光波导层与所述第二光电集成芯片进行光信号传输，且所述第一光电集成芯片和所述第二光电集成芯片连接所述再布线层的倒装焊盘；在所述再布线层的植球焊盘侧进行植球；使第一光电集成芯片和第二光电集成芯片通过光波导层进行通讯，利用光传输的高带宽，有效的提高了芯片之间的传输速率，简化了封装结构内部复杂的线路。

Description

一种光电共封装结构及其制作方法
本申请以2022年10月09日提交的申请号为202211227739.7，名称为“一种光电共封装结构及其制作方法”的中国发明申请为基础，并要求其优先权。
技术领域
本申请涉及芯片封装技术领域，特别涉及一种光电共封装结构及其制作方法。
背景技术
目前，多个芯片的封装结构主要通过再布线层(Redistributed layer，RDL)为芯片间的信号传输提供信号线，RDL既提供芯片间互连的高密度信号线，也提供芯片扇出到外部PCB的信号线；由于RDL内众多信号线高密互连，导致封装结构内部的线路较为复杂，且RDL中的绝缘介质的介电常数与高密互连信号线之间对传输信号的衰减作用，也会限制芯片间的信号传输速度，导致芯片间的信号传输速度较慢。
申请内容
基于此，有必要针对上述技术问题，提供一种光电共封装结构及其制作方法，以解决封装结构内部线路较为复杂以及芯片间的信号传输速度较慢的问题。
第一方面，本申请提供一种光电共封装结构的制作方法，包括：
提供一侧集成有光波导层的再布线层；
在所述再布线层的光波导层侧至少倒装并塑封第一光电集成芯片和第二光电集成芯片，所述第一光电集成芯片通过所述光波导层与所述第二光电集成芯片进行光信号传输，且所述第一光电集成芯片和所述第二光电集成芯片连接所述再布线层的倒装焊盘；
在所述再布线层的植球焊盘侧进行植球。
上述方案具有以下有益效果：
本申请的光电共封装结构的制作方法，在再布线层中集成光波导层，在再布线层的光波导层侧倒装并塑封第一光电集成芯片和第二光电集成芯片，使第一光电集成芯片和第二光电集成芯片通过光波导层进行通讯，利用光传输的高带宽，有效的提高了芯片之间的传输速率；通过光波导层替代芯片间一部分的信号传输线路，有效的简化了封装结构内部复杂的线路。
可选的，所述提供一侧集成有光波导层的再布线层，包括：
提供一表面涂布有临时键合层的临时载体；
在所述临时键合层上制作所述再布线层的倒装焊盘；
在所述临时键合层上制作所述光波导层，在所述光波导层的两端制作斜面；
在所述光波导层的两个斜面上制作光反射层；
制作所述再布线层，所述再布线层包括：嵌于绝缘介质层内的电互连结构和植球焊盘，所述电互连结构一端连接所述植球焊盘，另一端连接所述倒装焊盘；所述绝缘介质层具有凹槽结构以集成所述光波导层。
可选的，在所述临时键合层上制作光波导层，包括：
在所述临时键合层上制作光波导层的对位靶标；
以所述对位靶标为基准，制作光波导下包层，在所述光波导下包层的预设位置开窗，以形成光波导线路通道；
在光波导线路通道上以及在所述光波导下包层的上方制作光波导线路；
在所述光波导线路的上方制作光波导上包层，以形成光波导层；
在所述光波导层的两个斜面上制作光反射层，包括：溅射金属层，选择性蚀刻所述金属层，保留所述光波导层的两个斜面上的金属层，得到所述光反射层。
可选的，所述提供一侧集成有光波导层的再布线层，包括：
提供一表面涂布有临时键合层的临时载体；
在所述临时键合层上制作所述光波导层，在所述光波导层的两端制作斜面；
制作所述再布线层的倒装焊盘和所述光波导层两端的斜面上的光反射层；
制作所述再布线层，所述再布线层包括：嵌于绝缘介质层内的电互连结构和植球焊盘，所述电互连结构一端连接所述植球焊盘，另一端连接所述倒装焊盘；所述绝缘介质层具有凹槽结构以集成所述光波导层。
可选的，在所述临时键合层上制作所述光波导层，包括：
在所述临时键合层上制作光波导层的对位靶标；
以所述对位靶标为基准，制作光波导下包层，在所述光波导下包层的预设位置开窗，以形成光波导线路通道；
在光波导线路通道上以及在所述光波导下包层的上方制作光波导线路；
在所述光波导线路的上方制作光波导上包层，以形成所述光波导层；
所述制作再布线层的倒装焊盘和所述光波导层的两个斜面上的光反射层，包括：
溅射金属层，选择性蚀刻所述金属层，保留所述光波导层的两个斜面上的金属层，以及保留所述临时键合层上预设位置处的金属层，得到所述光反射层和所述倒装焊盘。
可选的，在所述再布线层的光波导层侧倒装并塑封第一光电集成芯片和第二光电集成 芯片，包括：
在所述再布线层的光波导层侧倒装所述第一光电集成芯片和所述第二光电集成芯片；
采用填充胶在所述第一光电集成芯片和所述第二光电集成芯片的底部进行填充；
通过塑封料将所述第一光电集成芯片和所述第二光电集成芯片进行塑封；
所述第一光电集成芯片包括第一电子芯片区和第一光子芯片区，所述第二光电集成芯片包括第二电子芯片区和第二光子芯片区，所述第一光子芯片区和所述第二光子芯片区通过所述光波导层进行光传输，所述第一电子芯片区和第二电子芯片区通过凸块连接所述再布线层的倒装焊盘。
第二方面，本申请提供一种光电共封装结构，包括：
再布线层，所述再布线层集成有光波导层；
所述再布线层的光波导层侧至少倒装有第一光电集成芯片和第二光电集成芯片，所述第一光电集成芯片通过所述光波导层与所述第二光电集成芯片进行光传输，且所述第一光电集成芯片和所述第二光电集成芯片分别连接所述再布线层的倒装焊盘，所述倒装焊盘位于所述再布线层的光波导层侧；
所述再布线层的植球焊盘侧设置有植球焊盘，所述植球焊盘上设置有锡球。
上述方案具有以下有益效果：
本申请的光电共封装结构，在再布线层中设置光波导层，使位于再布线层的光波导层侧的第一光电集成芯片和第二光电集成芯片，通过光波导层进行通讯，利用光传输的高带宽，有效的提高了芯片之间的传输速率；同时，光波导层可以采用与再布线层相同的制作技术，简化了封装结构的加工流程，提高了封装结构的集成度。
可选的，所述光波导层包括：
光波导下包层、光波导线路和光波导上包层，所述光波导下包层位于所述光波导层的底部，所述光波导下包层的预设位置开有用于形成光波导线路通道的窗口；所述光波导线路设置于所述光波导下包层上方和所述光波导线路通道内；所述光波导上包层设置于所述光波导线路的上方且包裹所述光波导线路；所述光波导线路用于进行所述第一光电集成芯片和所述第二光电集成芯片之间的光传输；
所述光波导层的一端有呈预设角度的第一斜面，所述第一斜面的表面设置有第一光反射层；
所述光波导层的另一端有呈预设角度的第二斜面，所述第二斜面的表面设置有第二光反射层。
可选的，所述光电共封装结构还包括：
塑封层，所述塑封层设置有两个凹槽，所述第一光电集成芯片和所述第二光电集成芯片分别设置于一个凹槽内；
所述第一光电集成芯片与所述再布线层的下表面之间设置有第一填充层，在所述第一填充层内设置有第一凸块，所述第一凸块用于倒装所述第一光电集成芯片；
所述第二光电集成芯片与所述再布线层的下表面之间设置有第二填充层，在所述第二填充层内设置有第二凸块，所述第二凸块用于倒装所述第二光电集成芯片。
可选的，所述再布线层包括：
嵌于绝缘介质层内的电互连结构和植球焊盘，所述电互连结构一端连接所述植球焊盘，另一端连接所述倒装焊盘；所述绝缘介质层具有带倾斜面的凹槽结构，以集成所述光波导层。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一实施例中提供的一种光电共封装结构的制作方法流程图；
图2-1是本申请一实施例中提供的一种再布线层结构示意图；
图2-2是本申请一实施例中提供的一种在再布线层一侧倒装光电集成芯片示意图；
图2-3是本申请一实施例中提供的一种在再布线层另一侧植球示意图；
图3是本申请一实施例中提供的第一种制作一侧集成有光波导层的再布线层的方法流程图；
图4-1是本申请一实施例中提供的载体上涂布临时键合层示意图；
图4-2是本申请一实施例中提供的制作倒装焊盘图形示意图；
图4-3是本申请一实施例中提供的制作光波导下包层示意图；
图4-4是本申请一实施例中提供的制作光波导线路示意图；
图4-5是本申请一实施例中提供的制作光波导上包层示意图；
图4-6是本申请一实施例中提供的加工光波导层斜面示意图；
图4-7是本申请一实施例中提供的制作光反射层示意图；
图4-8是本申请一实施例中提供的制作再布线层示意图；
图4-9是本申请一实施例中提供的在再布线层植球侧贴附临时载体示意图；
图4-10是本申请一实施例中提供的倒装光电集成芯片并塑封示意图；
图4-11是本申请一实施例中提供的植球示意图；
图5是本申请一实施例中提供的第二种制作一侧集成有光波导层的再布线层的方法流程图；
图6-1是本申请一实施例中提供的加工光波导层斜面示意图；
图6-2是本申请一实施例中提供的制作光反射层和倒装焊盘示意图；
图7是本申请一实施例中提供的第一种光电共封装结构示意图；
图8是本申请一实施例中提供的第二种光电共封装结构示意图；
符号说明如下：
100、硬质载体；200、临时键合层；300、金属种子层；400、光阻图形；X1、第一
斜面；X2、第二斜面；1、塑封层；2、第一光电集成芯片；21、第一电子芯片区；22、第一光子芯片区；3、第二光电集成芯片；31、第二电子芯片区；32、第二光子芯片区；4、第一填充层；41、第一倒装焊盘；5、第二填充层；51、第二倒装焊盘；6、光波导层；61、光波导下包层；62、光波导线路；63、光波导上包层；621、第一光波导线支路；622、第二光波导线支路；623、第三光波导线支路；7、再布线层；71、电互连结构；711、第一凸块；712、第二凸块；713、铜线路；714、电互连柱；715、植球焊盘；8、锡球；9、塑封料。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。
在一实施例中，提供一种如图1所示的一种光电共封装结构的制作方法，该方法包括：
步骤S100：提供一侧集成有光波导层的再布线层。
参见图2-1，为提供的再布线层7的结构，在再布线层7的一侧集成有光波导层6。
步骤S200：在再布线层的光波导层侧倒装并塑封第一光电集成芯片和第二光电集成芯片，第一光电集成芯片用于通过光波导层连接所述第二光电集成芯片，且第一光电集成芯片和第二光电集成芯片用于连接再布线层的倒装焊盘。
参见图2-2，在再布线层7中集成有光波导层6的一侧通过第一倒装焊盘711倒装第一光电集成芯片2，通过第二倒装焊盘712倒装第二光电集成芯片3，并将第一光电集成芯片2与光波导层6的一端连接，将第二光电集成芯片3与光波导层6的另一端连接，使 得第一光电集成芯片2和第二光电集成芯片3能够通过光波导层6进行光通讯；然后通过塑封料9将第一光电集成芯片2和第二光电集成芯片3进行塑封；对光电集成芯片塑封，可以将光电集成芯片完全塑封，也可以暴露光电集成芯片的部分表面。
本实施例中，倒装焊盘以及光电集成芯片的数量不局限于两个，可根据实际需要设置倒装焊盘的数量。
步骤S300：在再布线层的植球焊盘侧进行植球。
参见图2-3，在再布线层7的光波导层6侧倒装塑封第一光电集成芯片2和第二光电集成芯片3之后，在再布线层7的另一侧的植球焊盘715上进行植球，植球为锡球8，植球数量可根据实际需要进行设置。
本实施例的光电共封装结构的制作方法，在再布线层中集成光波导层，在再布线层的光波导层侧倒装并塑封第一光电集成芯片和第二光电集成芯片，使第一光电集成芯片和第二光电集成芯片通过光波导层进行通讯，利用光传输的高带宽，有效的提高了芯片之间的传输速率；通过光波导层进行第一光电集成芯片和第二光电集成芯片之间的信号传输，有效的简化了封装结构内部复杂的线路。
在一实施例中，提供一种光电共封装结构的制作方法，在图1中的方法基础上，本实施例中提供的制作一侧集成有光波导层的再布线层的方法如图3所示，该方法包括：
步骤S101：提供一表面涂布有临时键合层的临时载体。
参见图4-1，在一个硬质载体100上制作临时键合层200，其中硬质载体100可以是圆形，也可以是方形；若硬质载体100为圆形，材质为硅、玻璃、不锈钢中的一种；若硬质载体100为方形，材质为玻璃、不锈钢、陶瓷、玻纤增强有机树脂中的一种；临时键合层200可以液态或膜状，当为液态时，需采用涂布方式制作，当为膜状时，可以采用辊压、热压、真空贴膜等方法；临时键合层200可以为热敏性、光敏型、化学溶解型、机械分离型等；作为优选方案，选用光敏型临时键合层，光敏型临时键合层只能搭配玻璃载体使用；直接在高平整度的临时载体上制作光波导层，可以显著提高曝光能力，提高光波导线路的精细程度，有利于提高光波导线路和再布线层上凸块间的相对位置精度。
步骤S102：在临时键合层上制作再布线层的倒装焊盘。
参见图4-2，在临时键合层200上，采用半加成法制作第一倒装焊盘711和第二倒装焊盘712的图形，具体方法为：先溅射制作种子层，然后根据第一倒装焊盘711和第二倒装焊盘712的位置制作第一预设光阻图形，并在第一光阻图形电镀铜，然后褪去第一预设光阻图形，蚀刻种子层，得到第一倒装焊盘711和第二倒装焊盘712；本实施例中，种子 层优选钛/铜，光阻优选光刻胶，也可以是干膜；通过光阻图形制作倒装焊盘，能够根据设计需要随意调整倒装焊盘的位置，制作较为灵活。
步骤S103：在临时键合层上制作光波导层，在光波导层的两端制作斜面。
在一示例中，在临时键合层上制作光波导层，在光波导层的两端制作斜面的具体方法如下：
步骤S1031：在临时键合层上制作光波导层的对位靶标。
参见图4-3，在临时键合层200上预设的位置制作光波导层的对位靶标，根据对位靶标的位置确定光波导层的光波导线路的出入口的位置，从而制作光波导线路的出入口。
作为一个示例，也可以将第一倒装焊盘711和第二倒装焊盘712作为光波导层的对位靶标，也能够确定光波导层的光波导线路的出入口的位置，从而制作光波导线路的出入口。
步骤S1032：以对位靶标为基准，制作光波导下包层，在光波导下包层的预设位置开窗，以形成光波导线路通道。
参见图4-4，以对位靶标为基准，制作光波导下包层61，在下包层的预设位置开窗，以形成光波导线路62的通道，具体制作过程为：涂布光波导下包层61，并基于第二预设光阻图形选择性去除多余的下包层；且光波导下包层61在预设位置选择性开窗，以提供光线进出光波导线路62的通道；本实施例中，若硬质载体为圆形，优选旋涂(spin coating)的方式，若硬质载体为方形，优选狭缝涂布(slit coating)或喷涂的方式；作为其他实施方式，也可以采用3D打印的方法制作光波导下包层61；光波导下包层61能够遮蔽光波导线路62的下表面。
步骤S1033：在光波导线路通道上以及在光波导下包层的上方制作光波导线路。
在下包层61的开窗位置，以及在光波导下包层的上方制作光波导线路62，具体制作过程为：涂布光波导，并基于第三预设光阻图形选择性去除多余光波导，只保留预设位置的光波导；若硬质载体为圆形，优选旋涂(spin coating)的方式，若硬质载体为方形，优选狭缝涂布(slit coating)或喷涂的方式；作为其他实施方式，也可以采用3D打印的方法制作光波导线路62；光波导线路62能够为光电集成芯片之间的信号传输提供光通道。
步骤S1034：在光波导线路的上方制作光波导上包层，以形成光波导层。
参见图4-5，在光波导线路62的上方制作光波导上包层63，以形成光波导层，具体过程为：涂布光波导上包层63，并基于第四预设光阻图形选择性去除多余光波导上包层63，只保留光波导线路62位置的上包层，光波导上包层63将光波导线路62完全包裹；若硬质载体为圆形，优选旋涂(spin coating)的方式，若载体为方形，优选狭缝涂布(slit coating) 或喷涂的方式；作为其他实施方式，也可以采用3D打印的方法制作光波导上包层63；光波导上包层63能够遮蔽光波导线路62的上表面。
参见图4-6，在光波导层的两端制作第一斜面X1和第二斜面X2，第一斜面X1和第二斜面X2的角度可以根据光线反射需求进行设计，作为优选方案，斜面角度可设计为45度；制作斜面优选纳米压印法，也可以采用机械磨切、激光切割方法；若光波导线路的材料、光波导下包层和光波导上包层的材料是感光型材料，还可以分别采用梯度曝光获得边缘斜坡；光波导层两端的斜面为后续制作光反射层提供支撑面。
步骤S104：在所述光波导层的两个斜面上制作光反射层；
参见图4-7，上述步骤得到两端具有斜面的光波导层之后，需要在两端的斜面上制作第一光反射层64和第二光反射层64_1，以使光能够在光波导线路中进行反射传输，光反射层的具体制作过程为：整板溅射金属层，然后制作第五预设光阻图形，根据第五预设光阻图形，选择性蚀刻金属层，只保留光波导层两端斜面附近的金属层，得到第一光反射层64和第二光反射层64_1；本实施例中，金属层材质为金、银、铜中的一种；光反射层能够为光波导线路提供光反射面，使光能够在光波导线路中改变传输方向。
步骤S105：制作再布线层，再布线层包括：嵌于绝缘介质层内的电互连结构和植球焊盘，电互连结构一端连接植球焊盘，另一端连接倒装焊盘；绝缘介质层具有凹槽结构以集成光波导层。
参见图4-8，在图4-7中的结构表面采用积层法制作再布线层7，在制作再布线层7的过程中制作电互连柱714、铜线路713和植球焊盘715，电互连柱714和铜线路构成电互连结构，电互连结构一端连接植球焊盘715，另一端连接倒装焊盘711，绝缘介质层设置凹槽结构以集成光波导层；再布线层中绝缘介质层可以是二氧化硅、感光型聚酰亚胺、味之素积层薄膜等，优选感光型聚酰亚胺；再布线层中的铜线路采用半加成法制作；再布线层能够根据设计需要，设计与外部电通讯的电路。
可选的，绝缘介质层的凹槽结构包括：底面和两个斜面，其中，底面位于凹槽的顶部，两个斜面位于凹槽的两端，凹槽的两个斜面与光波导层两端的斜面宽度相同，该凹槽结构能够嵌入光波导层，使光波导上包层与底面贴合，光波导下包层与塑封层贴合，光波导层两端的斜面与凹槽的两个斜面贴合，以固定光波导层。
在一实施例中，提供一种光电共封装结构的制作方法，在图1中的方法基础上，本实施例中提供的在再布线层的光波导层侧至少倒装并塑封第一光电集成芯片和第二光电集成芯片，包括：
步骤S201：再布线层的光波导层侧至少倒装第一光电集成芯片和第二光电集成芯片。
参见图4-9，在再布线层植球焊盘侧贴附临时载体8，解除光波导层侧的硬质载体；其中，解除硬质载体的方式根据临时键合层胶的类型而定，如果有必要，还需要进行残留临时键合胶的清洗。
参见图4-10，在再布线层7上光波导层侧至少倒装第一光电集成芯片2和第二光电集成芯片3，根据芯片凸点类型和倒装精度需要，可以采用批量回流焊(mass reflow)、热压键合(TCB)或混合键合(hybrid bonding)的方式倒装芯片；本实施例中，优选热压键合的方式倒装光电集成芯片；光电集成芯片倒装能够减小封装体积，同时能够提高信号传输速率。
步骤S202：采用填充胶在第一光电集成芯片和第二光电集成芯片的底部进行填充。
采用光学底部填充胶对第一光电集成芯片2和第二光电集成芯片3的底部填充(underfill)，然后通过塑封料塑封芯片；根据光电集成芯片凸点的尺寸，还可以选择光学非导电胶膜(NCF)实现底部填充；塑封芯片的方式优选压缩成型，当使用膜状塑封料时，还可以使用真空贴膜；采用填充胶填充光电集成芯片，能够使光电集成芯片封装结构更加稳定。
步骤S203：第一光电集成芯片2包括第一电子芯片区21和第一光子芯片区22，第二光电集成芯片3包括第二电子芯片区31和第二光子芯片区32，第一光子芯片区22和第二光子芯片区32通过光波导层6进行光传输，第一电子芯片区21和第一光子芯片区22通过凸块41连接再布线层7的倒装焊盘711，第二电子芯片区31和第二光子芯片区32通过凸块51连接再布线层7的倒装焊盘712；光子芯片区能够通过光波导线路进行光信号传输，传输速率较高。
在一实施例中，提供一种光电共封装结构的制作方法，在图1中的方法基础上，本实施例中提供的在再布线层的植球焊盘侧进行植球，包括：
参见图4-11，解除植球焊盘侧的临时载体，并在再布线层7的植球焊盘715上植球，植球为锡球8，植球数量可根据实际需要进行设置，然后根据设计参数切割得到光电共封装结构；锡球能够与外部线路进行焊接，以传输电信号。
在一实施例中，提供一种光电共封装结构的制作方法，在图1中的方法基础上，本实施例中提供的制作一侧集成有光波导层的再布线层的方法如图5所示，该方法包括：
步骤S1001：提供一表面涂布有临时键合层的临时载体。
本实施例中，步骤S1001与实施例二中的步骤S101相同，在此不再赘述。
步骤S1002：在临时键合层上制作光波导层，在光波导层的两端制作斜面。
本实施例中，步骤S1002与实施例二中的步骤S103相同，在此不再赘述。
步骤S1003：制作再布线层的倒装焊盘和光波导层两端的斜面上的光反射层。
本实施例中，经过步骤S1001和步骤S1002得到如图6-1所示的光波导层结构，在此结构上溅射金属层，选择性蚀刻金属层，保留所述光波导层的两个斜面上的金属层，以及保留所述临时键合层上预设位置处的金属层，得到所述光反射层和所述倒装焊盘，具体过程为：
参见图6-2，整板溅射金属种子层300，金属种子层材质为金、银、铜中的一种；然后制作第六预设光阻图形400，第六预设光阻图400形显露光波导层两端的第一斜面64、第二斜面64_1和倒装焊盘的位置；并进行电镀铜，然后褪去第六预设光阻图形400，并刻蚀金属种子层，得到第一斜面64和第二斜面64_1上的金属层，即为光反射层，以及倒装焊盘。
本实施例中制作一侧集成有光波导层的再布线层的方法，与图3中的制作一侧集成有光波导层的再布线层的方法不同之处在于：图3是先在临时键合层上制作凸块，光波导层两端的光反射层采用溅射制作；而本实施例中，先在临时键合层上制作光波导层，光波导层两端的光反射层和倒装焊盘一起通过光阻图形电镀铜制作而成。
相较于图3中的制作一侧集成有光波导层的再布线层的制作方法，本实施例的方法所述使用的光阻图形数量较少，制作流程较为简单。
步骤S1004：制作再布线层，再布线层包括：嵌于绝缘介质层内的电互连结构和植球焊盘，电互连结构一端连接植球焊盘，另一端连接倒装焊盘；绝缘介质层具有凹槽结构以集成光波导层。
本实时中，步骤S1004与实施例二中的步骤S105相同，在此不再赘述。
本实施例中，制作完光波导层之后的步骤与实施例二中制作完光波导层之后的步骤相同，在此不再赘述。
本实施例的光波导结构的制作方法能够达到与实施例二中光波导结构的制作方法相同的效果。
在一实施例中，提供一种如图7所示的光电共封装结构，该光电共封装结构包括：
再布线层7，再布线层7内设置有光波导层6、第一倒装焊盘711、第二倒装焊盘712和植球焊盘715，其中，第一倒装焊盘711和第二倒装焊盘712位于再布线层7的光波导层侧，植球焊盘715位于再布线层另一侧，光波导层可以为矩形或圆形，也可以为其他任 意形状。
再布线层7的光波导层6侧至少倒装有第一光电集成芯片2和第二光电集成芯片3，第一光电集成芯片2通过光波导层6连接第二光电集成芯片3，且第一光电集成芯片连接第一倒装焊盘711，第二光电集成芯片3连接第二倒装焊盘712；再布线层7的植球焊盘715侧设置有植球焊盘715，植球焊盘715上设置有锡球8，锡球8的数量可根据设计需要进行设置。
本实施例中，光电集成芯片和倒装焊盘的数量至少为2个，可根据实际需要进行设置。
本实施例的光电共封装结构，在再布线层中设置光波导层，光电集成芯片通过倒装焊盘、植球焊盘和锡球与外部进行电通讯，位于再布线层的光波导层侧的第一光电集成芯片和第二光电集成芯片，通过光波导层进行通讯，利用光传输的高带宽，有效的提高了芯片之间的传输速率。
在一实施例中，提供一种如图8所示的光电共封装结构，该光电共封装结构包括：塑封层1、再布线层7和锡球8，其中，再布线层7设置于塑封层1的上表面，锡球8设置于再布线层的上表面。
本实施例中，再布线层7内设置有光波导层6、第一倒装焊盘711、第二倒装焊盘712、植球焊盘715和电互连结构71，其中，第一倒装焊盘711和第二倒装焊盘712位于再布线层7的光波导层侧，植球焊盘715位于再布线层另一侧，光波导层长度方向截面为梯形；电互连结构和植球焊盘嵌于再布线层的绝缘介质层内，电互连结构71一端连接植球焊盘715，另一端连接第一倒装焊盘711；绝缘介质层具有带倾斜面的凹槽结构，以集成光波导层6。
本实施例中，电互连结构71包括：电互连柱714和电互连线路713，其中，电互连线路713通过电互连柱714分别与倒装焊盘711和植球焊盘715进行连接。
光波导层6包括：光波导下包层61、光波导线路62和光波导上包层63，其中，光波导下包层61位于光波导层6的底部，光波导上包层63位于光波导层6的顶部，光波导线路62位于光波导下包层61和光波导上包层63之间，光波导线路62的两端在光波导下包层61的下表面形成光波导线路62的两个光出入口，形成光波导线路62的光通道，光波导线路62用于第一光电集成芯片2和第二光电集成芯片3之间的光传输。
本实施例中，光波导线路62包括：第一光波导线支路621、第二光波导线支路622和第三光波导线支路623，其中，第一光波导线支路621的一端作为光波导线路62的一个光出入口，另一端连接第二光波导线支路622的一端，第二光波导线支路622的另一端连接 第三光波导线支路623的一端，第三光波导线支路623的另一端作为光波导线路的另一个光出入口。
本实施例中，第一光波导线支路621与第二光波导线支路622的连接处呈预设角度的第一斜面64，在第一斜面64的表面设置有第一金属层，从而形成第一光反射层；第三光波导线支路623与第二光波导线支路622的连接处呈预设角度的第二斜面65，在第二斜面65的表面设置有第二金属层，从而形成第二光反射层，第一光反射层和第二光反射层能够为光提供反射面，使光在光波导线路中传播时能够改变方向，从而实现第一光电集成芯片2和第二光电集成芯片3的光通讯。
在一示例中，预设角度的范围为30度—60度，第一斜面64的预设角度与第二斜面64_1的预设角度可以设置为相同角度，也可以设置为不同角度，根据光传输线路具体设置；作为优选方案，预设角度可以设置为45度。
本实施例中，塑封层1设置有两个凹槽，第一光电集成芯片2和第二光电集成芯片3分别设置于一个凹槽内；该两个凹槽是封装第一光电集成芯片2和第二光电集成芯片3之后所自然形成的凹槽。
第一光电集成芯片2与再布线层7的下表面之间设置有第一填充层4，在第一填充层4内设置有第一凸块41，第一凸块41用于倒装第一光电集成芯片2，第一凸块41与第一倒装焊盘711连接；第二光电集成芯片3与再布线层7的下表面之间设置有第二填充层5，在第二填充层5内设置有第二凸块51，第二凸块51用于倒装第二光电集成芯片3，第二凸块51与第二倒装焊盘712连接；填充层是由于凸块占用一定空间所形成，填充层内填充填充胶，能固定光电集成芯片，提高封装可靠性。
本实施例中，第一光电集成芯片2包括第一电子芯片区21和第一光子芯片区22，第二光电集成芯片3包括第二电子芯片区31和第二光子芯片区32，第一电子芯片区21与第一凸块41连接，第二电子芯片区31与第二凸块51连接，第一光子芯片区22与第二光子芯片区32通过光波导线路62进行光传输，使得第一光电集成芯片2和第二光电集成芯片3之间能够通过光波导线路62进行光通讯；光子芯片区作为光电集成芯片的光通讯功能区，能够对光信号和电信号进行转换。
本实施例的光电共封装结构，在再布线层设置光波导层、倒装焊盘和电互连结构，光电集成芯片能够通过倒装焊盘和电互连结构与外部进行电通讯，第一光电集成芯片的第一光子芯片区和第二光电集成芯片的第二光子芯片区能够通过光波导线路进行光通讯，利用光传输的高带宽，有效的提高了芯片之间的传输速率；同时，光波导层有效的简化了封装 结构内部复杂的线路。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种光电共封装结构的制作方法，其中，包括：
    提供一侧集成有光波导层的再布线层；
    在所述再布线层的光波导层侧至少倒装并塑封第一光电集成芯片和第二光电集成芯片，所述第一光电集成芯片通过所述光波导层与所述第二光电集成芯片进行光信号传输，且所述第一光电集成芯片和所述第二光电集成芯片连接所述再布线层的倒装焊盘；
    在所述再布线层的植球焊盘侧进行植球。
  2. 根据权利要求1所述的光电共封装结构的制作方法，其中，所述提供一侧集成有光波导层的再布线层，包括：
    提供一表面涂布有临时键合层的临时载体；
    在所述临时键合层上制作所述再布线层的倒装焊盘；
    在所述临时键合层上制作所述光波导层，在所述光波导层的两端制作斜面；
    在所述光波导层的两个斜面上制作光反射层；
    制作所述再布线层，所述再布线层包括：嵌于绝缘介质层内的电互连结构和植球焊盘，所述电互连结构一端连接所述植球焊盘，另一端连接所述倒装焊盘；所述绝缘介质层具有凹槽结构以集成所述光波导层。
  3. 根据权利要求2所述的光电共封装结构的制作方法，其中，在所述临时键合层上制作光波导层，包括：
    在所述临时键合层上制作光波导层的对位靶标；
    以所述对位靶标为基准，制作光波导下包层，在所述光波导下包层的预设位置开窗，以形成光波导线路通道；
    在光波导线路通道上以及在所述光波导下包层的上方制作光波导线路；
    在所述光波导线路的上方制作光波导上包层，以形成所述光波导层；
    在所述光波导层的两个斜面上制作光反射层，包括：
    溅射金属层，选择性蚀刻所述金属层，保留所述光波导层的两个斜面上的金属层，得到所述光反射层。
  4. 根据权利要求1所述的光电共封装结构的制作方法，其中，所述提供一侧集成有光波导层的再布线层，包括：
    提供一表面涂布有临时键合层的临时载体；
    在所述临时键合层上制作所述光波导层，在所述光波导层的两端制作斜面；
    制作所述再布线层的倒装焊盘和所述光波导层两端的斜面上的光反射层；
    制作所述再布线层，所述再布线层包括：嵌于绝缘介质层内的电互连结构和植球焊盘，所述电互连结构一端连接所述植球焊盘，另一端连接所述倒装焊盘；所述绝缘介质层具有凹槽结构以集成所述光波导层。
  5. 根据权利要求4所述的光电共封装结构的制作方法，其中，在所述临时键合层上制作所述光波导层，包括：
    在所述临时键合层上制作光波导层的对位靶标；
    以所述对位靶标为基准，制作光波导下包层，在所述光波导下包层的预设位置开窗，以形成光波导线路通道；
    在光波导线路通道上以及在所述光波导下包层的上方制作光波导线路；
    在所述光波导线路的上方制作光波导上包层，以形成所述光波导层；
    所述制作再布线层的倒装焊盘和所述光波导层的两个斜面上的光反射层，包括：
    溅射金属层，选择性蚀刻所述金属层，保留所述光波导层的两个斜面上的金属层，以及保留所述临时键合层上预设位置处的金属层，得到所述光反射层和所述倒装焊盘。
  6. 根据权利要求1所述的光电共封装结构的制作方法，其中，在所述再布线层的光波导层侧倒装并塑封第一光电集成芯片和第二光电集成芯片，包括：
    在所述再布线层的光波导层侧倒装所述第一光电集成芯片和所述第二光电集成芯片；
    采用填充胶在所述第一光电集成芯片和所述第二光电集成芯片的底部进行填充；
    通过塑封料将所述第一光电集成芯片和所述第二光电集成芯片进行塑封；
    所述第一光电集成芯片包括第一电子芯片区和第一光子芯片区，所述第二光电集成芯片包括第二电子芯片区和第二光子芯片区，所述第一光子芯片区和所述第二光子芯片区通过所述光波导层进行光传输，所述第一电子芯片区和所述第二电子芯片区通过凸块连接所述再布线层的倒装焊盘。
  7. 一种光电共封装结构，其中，包括：
    再布线层，所述再布线层集成有光波导层；
    所述再布线层的光波导层侧至少倒装有第一光电集成芯片和第二光电集成芯片，所述第一光电集成芯片通过所述光波导层与所述第二光电集成芯片进行光传输，且所述第一光电集成芯片和所述第二光电集成芯片分别连接所述再布线层的倒装焊盘，所述倒装焊盘位于所述再布线层的光波导层侧；
    所述再布线层的植球焊盘侧设置有植球焊盘，所述植球焊盘上设置有锡球。
  8. 根据权利要求7所述的光电共封装结构，其中，所述光波导层包括：
    光波导下包层、光波导线路和光波导上包层，所述光波导下包层位于所述光波导层的底部，所述光波导下包层的预设位置开有用于形成光波导线路通道的窗口；所述光波导线路设置于所述光波导下包层上方和所述光波导线路通道内；所述光波导上包层设置于所述光波导线路的上方且包裹所述光波导线路；所述光波导线路用于进行所述第一光电集成芯片和所述第二光电集成芯片之间的光传输；
    所述光波导层的一端有呈预设角度的第一斜面，所述第一斜面的表面设置有第一光反射层；所述光波导层的另一端有呈预设角度的第二斜面，所述第二斜面的表面设置有第二光反射层。
  9. 根据权利要求7所述的光电共封装结构，其中，所述光电共封装结构还包括：
    塑封层，所述塑封层设置有两个凹槽，所述第一光电集成芯片和所述第二光电集成芯片分别设置于一个凹槽内；
    所述第一光电集成芯片与所述再布线层的下表面之间设置有第一填充层，在所述第一填充层内设置有第一凸块，所述第一凸块用于倒装所述第一光电集成芯片；
    所述第二光电集成芯片与所述再布线层的下表面之间设置有第二填充层，在所述第二填充层内设置有第二凸块，所述第二凸块用于倒装所述第二光电集成芯片。
  10. 根据权利要求8所述的光电共封装结构，其中，所述再布线层包括：
    嵌于绝缘介质层内的电互连结构和植球焊盘，所述电互连结构一端连接所述植球焊盘，另一端连接所述倒装焊盘；所述绝缘介质层具有带倾斜面的凹槽结构，以集成所述光波导层。
PCT/CN2023/087987 2022-10-09 2023-04-13 一种光电共封装结构及其制作方法 WO2024077908A1 (zh)

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