CN206546453U - 利用混合多芯片集成的光收发器 - Google Patents

利用混合多芯片集成的光收发器 Download PDF

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Publication number
CN206546453U
CN206546453U CN201720200162.9U CN201720200162U CN206546453U CN 206546453 U CN206546453 U CN 206546453U CN 201720200162 U CN201720200162 U CN 201720200162U CN 206546453 U CN206546453 U CN 206546453U
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chip
optical transceiver
dielectric
tmv
optical
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丁亮
拉达克里希南·L·纳贾拉詹
罗伯托·科乔利
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Marvell Asia Pte Ltd
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Inphi Corp
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    • G—PHYSICS
    • G02—OPTICS
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    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
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    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4274—Electrical aspects
    • G02B6/428—Electrical aspects containing printed circuit boards [PCB]
    • G—PHYSICS
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    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
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    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
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    • G02B6/26—Optical coupling means
    • G02B6/30—Optical coupling means for use between fibre and thin-film device
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Abstract

一种利用混合多芯片集成的光收发器。所述光收发器包括具有多个预制表面接合位点的PCB。第一芯片包括嵌入在覆盖电介质再分布层的电介质模制层内的多个电子装置的FOWLP封装，通过在电介质再分布层与多个预制表面接合位点之间分别接合多个导体球，同时暴露在电介质模制层中的多个模制通孔(TMV)内填充的焊接材料，将所述第一芯片设置在所述PCB上。光收发器还包括被配置为Sipho管芯的第二芯片，其包括嵌入基本上无需任何电子装置工艺的SOI晶片中的光子装置。第二芯片堆叠在所述第一芯片上方，其中，多个导体凸块分别接合到在多个TMV中的焊接材料。本公开的光收发器具有较低的寄生电容，同时保持简单封装工艺和低成本。

Description

利用混合多芯片集成的光收发器
技术领域
本公开涉及光电集成，更具体地，涉及基于使用低成本扇出晶片级封装(FOWLP)架构和模制通孔(through-mold via)(TMV)技术的管芯上封装多芯片堆叠集成的紧凑型光收发器。
背景技术
随着科学技术的快速更新，计算机的处理速度和容量相应地增加。为了缩短在电子装置之间(例如，从LD驱动器/TIA到数字信号处理器DSP)或者在电子(驱动器/TIA)和光子(例如，CDR和PAM4ASIC)之间的常规引线接合的互连长度，人们已经开始在Si光子管芯中使用硅通孔(TSV)工艺来替代引线接合并且进行互连。然而，由于执行工艺和处理薄晶片的高成本，所以TSV工艺仍然准备用于大规模生产。此外，当前的基础设施和投资仅允许在12英寸晶片中进行精细的TSV工艺。这限制了在使用小于12英寸的衬底尺寸的各种技术中采用的基于TSV的互连的灵活性，例如，8英寸SiGe工艺、8英寸BiCMOS工艺、GaAs衬底工艺、InP衬底工艺、以及8英寸MEMS工艺。制造工艺的复杂性、低产量、低效的晶片面积使用以及扩展到高级电子设备非常昂贵，使TSV工艺不切实际地用于制造Si光子场产品。因此，需要替代解决方案，用于集成电子功能和光子电路，以满足在电子和光子之间不断增加的带宽的要求。期望具有改进的封装方案，其享有3D多芯片堆叠集成的高性能益处，具有更短的互连和更低的寄生，同时保持简单封装工艺和低成本。
实用新型内容
根据本实用新型的一个方面，一种利用混合多芯片集成的光收发器，包括：PCB，具有多个预制表面接合位点；第一芯片，包括嵌入在覆盖电介质再分布层的电介质模制层内的多个电子装置，通过分别在所述多个预制表面接合位点经由多个导体球接合所述电介质再分布层同时暴露填充在多个模制通孔TMV中的焊接材料，将所述第一芯片设置在所述PCB上，所述多个TMV形成在所述电介质模制层中；以及第二芯片，包括嵌入在SOI晶片中的光子装置，所述第二芯片具有添加有多个导体凸块的前表面，所述第二芯片堆叠在所述第一芯片上方，其中，在所述前表面上的所述多个导体凸块分别接合到所述多个TMV中的所述焊接材料。
进一步地，所述第一芯片包括在覆盖用于所述电介质再分布层的HD-8940 PBO膜的扇出晶片级封装(FOWLP)架构下使用用于所述电介质模制层的嵌入绝缘片(EBIS)型材料封装在一起的多个电子管芯。
进一步地，所述多个电子装置包括PAM4 ASIC模块、驱动器模块、跨阻抗放大器模块以及多个AC耦合电容器。
进一步地，所述多个导体球中的每个接合到嵌入在所述电介质再分布层中的第一导电焊盘。
进一步地，填充在所述多个TMV中的每个中的所述焊接材料接合到嵌入在所述电介质再分布层中的第二导电焊盘。
进一步地，所述第二芯片是基本上没有硅通孔结构的Si光子芯片。
进一步地，所述光子装置包括基于Si的光波导、调制器以及多个光电二极管。
进一步地，所述第二芯片还包括一个或多个激光二极管，所述一个或多个激光二极管安装在所述前表面的凹陷区域上并且经由安装焊盘与所述多个导体凸块中的一个或多个电耦接，以通过在所述电介质再分布层中的一个或多个导电焊盘以及所述多个导体球中的一个或多个连接到所述PCB，而无需任何外部引线接合。
进一步地，所述第二芯片还包括形成在所述前表面的边缘附近的一个或多个光纤耦合结构。
进一步地，所述电介质再分布层还包括嵌入导线，所述嵌入导线用于分别通过填充在所述多个TMV中的所述焊接材料和在所述第二芯片的所述前表面上的所述多个导体凸块，来将所述多个电子装置选择性地连接到至少所述调制器和所述多个光电二极管。
进一步地，还包括安装在一个或多个光纤耦合结构中的一个或多个光纤，所述一个或多个光纤在所述第二芯片的前表面和所述第一芯片的所述电介质模制层之间，以与对应的基于Si的光波导耦合。
附图说明
图1是根据本实用新型实施例的通过DoP工艺在PCB上组装的光收发器的俯视图；
图2是示出根据本实用新型的实施例的图1的光收发器组件的横截面AA'剖视图的示图；
图3是示出根据本实用新型的实施例的图1的光收发器组件的横截面BB'剖视图的示图；
图4是示出根据本实用新型的实施例的图1的光收发器组件的横截面CC'剖视图的示图；以及
图5A-图5D是示出根据本实用新型的实施例的用于组装紧凑型光收发器的一系列过程的示图。
具体实施方式
本公开涉及光电集成。更具体地，通过在具有用于电耦接的模制通孔(TMV)的FOWLP封装电子芯片上堆叠的高产出硅光子芯片的管芯上封装(DoP)多芯片集成，来形成高速紧凑型光收发器。在某些实施例中，本实用新型应用于高速光通信，但是其他应用也是可行的。
在现代电气互连系统中，高速串行链路代替并联数据总线，并且串行链路速度因CMOS技术的演进而快速增大。根据摩尔定律，互联网带宽每两年就几乎翻倍。但是摩尔定律在今后十年结束。标准CMOS硅晶体管在大约5nm时停止增大。并且，因生产规模而增大的互联网带宽进入稳定时期。但是互联网和移动应用继续需要大量带宽来传输照片、视频、音乐以及其他多媒体文件。本公开描述了超越摩尔定律提高通信带宽的技术和方法。
串行链路性能受到信道电气带宽和电子部件的限制。为了解决由带宽限制引起的符号间干扰(ISI)问题，我们需要使所有电气部件尽可能接近，以减小在其间的距离或通道长度。光子学和电子学的单片集成(例如，参见美国专利No.8,895,413)承诺一次性提高其能力。Luxtera的专利公开了集成Si光子和高速电子器件的两种单片方式，即，使用嵌入电子部件内的Si通孔(TSV)的并排集成和3D集成。实际上，这两种方法在电子学和光子学之间带来了比引线接合方法提供的低得多的寄生现象。然而，由于制造过程极端复杂，所以该方法非常昂贵并且产量低。从系统的角度来看，存在另一个缺点，即，在电子电路和PCB或封装衬底之间仍然需要引线接合。因此，从PCB或封装衬底到电子电路的电信号传输没有改善，反之亦然。实现具有高产出的高级集成的替代方法是使用多芯片集成技术。在本申请中，我们将公开通过单独制造的TSV/TGV插入器使用电/光管芯堆叠集成的高速紧凑型光收发器以及具有优化的节距尺寸的交错凸块设置。
在特定的实施例中，本实用新型提供一种借助混合多芯片集成的光收发器。所述光收发器包括具有多个预制表面接合位点的PCB。此外，所述光收发器包括第一芯片，第一芯片包括嵌入在覆盖电介质再分布层的电介质模制层内的多个电子装置。通过分别在多个预制表面接合位点经由多个导体球接合电介质再分布层，同时暴露在形成在电介质模制层中的多个模制通孔(TMV)内填充的焊接材料，将所述第一芯片设置在所述PCB上。而且，所述光收发器包括第二芯片，其包括嵌入在SOI晶片中的光子装置，所述SOI晶片具有添加有多个导体凸块的前表面。通过将前表面上的多个导体凸块分别接合到多个TMV中的焊接材料，将所述第二芯片堆叠在所述第一芯片上方。
借助根据本实用新型的改进，提供了许多益处。在某些实施例中，本实用新型提供一种用于封装光收发器的3D管芯上封装(DoP)多芯片堆叠集成，其使用较低成本的FOWLP和TMV技术实现具有实质上低寄生电容的优异紧凑尺寸。堆叠结构节省更多的电路板面积，其将用于更小的形状因子光学模块或用于车载光学应用。通过在单独芯片上的光子和电子装置的完全解耦过程，可以整体上为每个部件实现更高的产量，并且为光收发器实现更高的可靠性。此外，通过利用TMV技术和通过再分布层和PCB的直接导体球接合，消除了包括LD电源线的所有不可靠的高寄生引线接合以及在Si光子芯片中的高成本低产出TSV接合，以提供超低寄生组装过程。使用TMV技术在顶部和底部管芯或封装之间进行垂直互连，对于各种电子技术节点是灵活的。如果光收发器设计者想要改变驱动器/TIA(SiGe、GaAs或CMOS)和CDR或PAM4ASIC(45nm、28nm、20nm CMOS)的技术，则这是有益的。接合FOWLP和TMV过程，人们不需要重新设计单个芯片并重新开发每个芯片的其相应过程。本实用新型在宽带通信技术的背景下实现这些益处和其他益处。然而，通过参考说明书的后部分和附图，可以实现本实用新型的性质和优点的进一步理解。
图1是根据本实用新型的实施例的通过在PCB上包括FOWLP和DoP工艺的多芯片集成组装的光收发器的俯视图。该图仅是示例，其不应不适当地限制权利要求的范围。本领域的技术人员将认识到许多变化、替换以及修改。如图所示，光收发器100通过多芯片集成来组装。在扇出晶片级封装(FOWLP)架构下形成第一芯片，以集成光收发器所需的所有关键电子管芯。第二芯片形成为单个Si光子(Sipho)管芯，以集成包括表面安装的激光二极管的主要光子部件。第二芯片或Si光子管芯在管芯上封装工艺中堆叠在第一芯片上，以通过采用模制通孔(TMV)技术来耦合在第一芯片中的对应电子装置。
参考图1，在组装的光收发器100的俯视图中，模制材料110覆盖设置在PCB 101上的封装中的多个电子装置。多个电子装置是单独的电子管芯，包括PAM4ASIC模块122、驱动器模块124、跨阻抗放大器模块126或多个单独的AC耦合电容器128和其他无源部件127。在模制材料110的暴露的前端表面上，通过倒转其前表面，以面对模制材料110的暴露的前端，来设置Sipho管芯130。如图所示，一个或多个激光二极管132安装在Sipho管芯的在该俯视图中面朝下的前表面上。至少包括微控制器单元(MCU)141和电源管理单元(PMU)142的光收发器100的其他部件直接组装在PCB 101上。下面可以在沿着线A-A'、B-B'和C-C'的几个横截面剖视图中找出紧凑型光收发器100的组装结构的额外特征。
图2是示出根据本实用新型的实施例的图1的光收发器组件的横截面AA'剖视图的示图。该图仅是示例，其不应不适当地限制权利要求的范围。本领域的技术人员将认识到许多变化、替换以及修改。如该AA'剖视图所示，第一芯片通过多个球119接合到PCB 101的表面。如前面在图1所示，第一芯片是多个电子管芯的FOWLP封装。特别在该剖视图中，PAM4ASIC模块122、驱动器模块124和几个AC耦合电容器(CAP)128嵌入模制材料110中。模制材料110是通常用于FOWLP封装工艺的嵌入绝缘片(EBIS)型电介质材料(dielectricmaterial)。
如图所示，模制材料110形成为覆盖用作再分布层(RDL)113的另一电介质材料。该RDL 113包括多个图案化或单独嵌入的导电焊盘或布线115。在RDL 113的后端表面上，在将FOWLP封装设置在PCB 101的相应的多个预制表面接合位点之前，通过后端工艺增加多个导体球119。多个导体球119中的每个形成到RDL 113内部的导电焊盘的电接触，并且引导至RDL 113的2D平面的其他位置，以连接到在FOWLP封装中的指定电子装置。当然，多个导体球119还连接PCB的内部布线，该内部布线引导至PCB上的其他电子装置(例如，MCU或PMU)，或用于操作光收发器的其他外部源。
另外，如图2所示，第二芯片130堆叠在第一芯片上。在一个实施例中，通过仅仅基本上集成所有光子装置，而不包括任何电子装置工艺和通过脆弱光子装置的任何昂贵的跨硅通孔(TSV)结构，将第二芯片130形成为Sipho管芯。在一个示例中，在Sipho管芯130中的光子装置包括光调制器135、多个光电二极管(在图4中的137)和用于光束耦合器/分离器或多路复用器/解复用器装置(未明确示出)的基于Si或SiN的光波导。在另一示例中，在第二芯片的前表面上形成几个光纤耦合结构134或136，用于耦合激光输出或用于光收发器的输入/输出光信号的光纤。
再次参考图2，通过经由管芯上封装工艺利用TMV技术来实现这种多芯片堆叠集成。在堆叠第二芯片之前，在模制材料110的暴露的前端表面上，在多个图案化位置中形成穿过模制材料110的整个厚度的具有笔直轮廓的多个模制通孔(TMV)结构，以到达在RDL113内对应的导电焊盘。滴入焊接材料129，以基本上填充整个通孔，其顶端靠近或略高于模制材料110的前端表面。因此，在用于形成Sipho管芯的单独封装工艺之后，通过在其前表面上在指定为匹配多个TMV的图案化位置的位置处增加多个导体凸块139，制备第二芯片130。现在，将第二芯片130翻转，以使前表面朝向模制材料的露出的前端表面，使得多个导体凸块139分别接合(通过焊接)到多个TMV中的焊接材料。
经由导体凸块139通过TMV结构的在第二芯片和第一芯片之间的接合为在第一芯片中的电子装置和在第二芯片中的光子装置之间的指定的光电控制和信号通信提供低寄生电连接。例如，嵌入Sipho管芯130中的调制器135经由多个导体凸块139中的一个通过焊接材料129以及在RDL113中的一个或多个导电焊盘和布线连接到驱动器模块124，以基于指定的数字信号模式，调制输出激光。在另一示例中，光电二极管137(参见下面的图4)也经由多个导体凸块139中的一个通过焊接材料129和在RDL113中的一个或多个导电焊盘和布线电耦合，以将转换的电流信号(来自接收的光信号)发送给跨阻放大器模块126。在PCB组件上的整个光收发器封装中不存在引线接合。无引线接合的组装方案使得光收发器能够传送>56G波特符号率，因此，能够以PAM4信号调制格式传送112Gbps。
在另一实施例中，一个或多个激光二极管132安装在前表面的预制凹陷区域131上，其中，导电焊盘133可以设置为用于容纳激光二极管132。导电焊盘133包括在前表面的正常(非凹陷)区域的延伸部分。当在前表面增加多个导体凸块139时，至少一个导体凸块连接到导电焊盘133的延伸部分，用于为激光二极管132提供DC功率。凹陷区域131形成为允许在FOWLP封装上的倒转接合的Sipho管芯之间具有足够的间隙，即使在此处安装表面安装激光二极管。此外，在该DoP工艺中不存在引线接合，即使通常用于为激光二极管供电的引线接合也被凸块接合和内部布线代替，以减小总体寄生电容。
图3是示出根据本实用新型的实施例的图1的光收发器组件的横截面BB'剖视图的示图。该图仅是示例，其不应不适当地限制权利要求的范围。本领域的技术人员将认识到许多变化、替换以及修改。如沿着BB'线的特定剖视图所示，光纤138耦合到形成在第二芯片130的前表面中的对应的光纤耦合结构136。在这种多芯片堆叠配置中，至少光纤138的截面被覆盖在第二芯片的前表面和第一芯片的模制材料110的前端表面之间。在特定的实施例中，形成光纤耦合结构136，以使光纤138的光芯(optical core)与在Sipho管芯130中的光波导对准。在形成Sipho管芯130时，通过将光纤耦合结构136(例如，V形槽)定位在前表面的凹陷区域，可以实现适当对准。
图4是示出根据本实用新型的实施例的图1的光收发器组件的横截面CC'剖视图的示图。该图仅是示例，其不应不适当地限制权利要求的范围。本领域的技术人员将认识到许多变化、替换以及修改。如沿着CC'线的特定剖面图所示，第一芯片经由多个球119接合到PCB 101。如前面在图1和图2所述，第一芯片是多个电子管芯的FOWLP封装。特别地，在该剖视图中，PAM4ASIC模块122、跨阻抗放大器(TIA)模块126和几个AC耦合电容器(CAP)128嵌入在模制材料110中。如前面在图1、图2以及图3所述，第二芯片是Sipho管芯130，其基本上集成了所有光子装置，包括嵌入式光电二极管137和表面安装的激光二极管132和光纤138。在第二芯片和第一芯片之间经由导体凸块139通过TMV结构的接合提供了低-寄生电连接，用于在第一芯片中的电子装置(例如，TIA 126)与在第二芯片中的光子装置(例如，光电二极管137)之间的指定的光电控制和信号通信。
在可替换的实施例中，本实用新型还提供了一种用于组装紧凑型光收发器的方法，示出了基于利用低成本FOWLP架构和TMV技术的多芯片堆叠集成的一些关键过程，用于促进DoP过程。图5A-图5D是示出根据本实用新型的实施例的方法的一系列过程的示图。这些图仅是示例，其不应不适当地限制权利要求的范围。本领域的技术人员将认识到许多变化、替换以及修改。可以通过示出整个组装过程的仅四个快照，来跳过一个或多个过程。可以以多个连续顺序插入一个现有或额外过程。在不影响组装过程的主要顺序的同时，可以在部件的微小变化时包括其他过程。
参考图5A的横截面图，形成FOWLP封装，其具有嵌入在覆盖电介质再分布层113的电介质模制层110中的多个电子装置。电介质模制层110离开前端表面111，电介质再分布层113具有后端表面112。FOWLP封装基本上集成了基本上用于组装光收发器的所有的电子管芯，包括PAM4或CDR、驱动器和TIA。作为FOWLP工艺的一部分包含TMV工艺以，执行TMV工艺，以在多个图案化位置中产生多个笔直轮廓的模制通孔(TMV)。另外，FOWLP工艺还包括在电介质再分布层113中形成图案化的导电焊盘115或布线。在前端表面中的某些位置(未露出)以及在后端表面112中的替代位置中，使用Cu材料通过后端工艺，选择性地形成这些导电焊盘115。还在其内形成导电布线的二维网络，以基于指定的应用选择性地连接那些导电焊盘。
在一个实施例中，通过激光工艺创建每个TMV，以从具有高纵横比的前端表面111向下蚀刻或钻取穿过模制层110的整个厚度，以到达在电介质再分布层113的前端(通常不露出)的一个导电焊盘115。在形成多个TMV之后，在通过无电镀Ni/Au电镀在Cu焊盘上形成UBM结构之后，将焊接材料129滴入每个TMV内。在某些实施例中，焊接材料充分地填充到每个TMV，使得焊接材料129的顶端部分接近或稍微高于前端表面112。
在另一实施例中，FOWLP工艺还包括后端表面凸块形成工艺。特别地，在后端表面112上，在与PCB 101上的多个预制表面接合部位匹配的预定位置处形成多个导体球119(通常由选择的焊接材料或合金制成)。
参考图5B的横截面图，单独形成Si光子(Sipho)管芯130，以仅集成光子装置。使用该管芯，不进行关键的电子装置工艺。特别地，Sipho管芯130由一片SOI晶片制成，其中，形成各种光波导和光学部件。在一个示例中，光波导可以是基于Si的或基于Si3N4的，以提供光束耦合/分离或波长复用/解复用功能。包括诸如激光调制器135和光电二极管等光电子装置的其他部件也可以嵌入Sipho管芯130的前表面130F下方。但是，在Sipho管芯形成工艺中不包括任何硅通孔结构，以避免容易损坏在薄SOI晶片中的嵌入光子装置或近表面光学部件以及任何相关的低产量生产问题。
在特定的实施例中，Sipho管芯形成工艺还包括在前表面130F中形成凹陷区域131，并且导电焊盘133可以布置并放置在凹陷区域131上，包括具有规则水平的前表面130F的至少一个延伸部分。该凹陷区域131加上相应的导电焊盘133提供用于安装一个或多个激光二极管132的基底。激光二极管132通过导电焊盘133建立所有其对应的电连接，特别是用于接收用于驱动激光激发的DC电流的所有电连接。
在另一个特定的实施例中，制备Sipho管芯130的后续工艺包括在包括导电焊盘133的至少一个延伸部分的前表面130F上的多个选定位置上添加多个导体凸块139。然而，多个导体凸块均可以由选择的焊接材料制成，被配置为形成用于嵌入的激光调制器135或光电二极管以及用于表面安装的激光二极管132的电连接。
参考图5C，光收发器组装过程通过多芯片3D堆叠集成执行。FOWLP封装设置在PCB101上，后端表面112面向PCB，使得多个导体球119分别接合到PCB 101的多个预制表面接合位点。这些凸块接合在其自身之间或者在其与外部装置之间在FOWLP封装中基本上建立多个电子装置的必要的电连接，而不使用任何引线接合。因此，为了组装高(>56)Gbaud符号率收发器，可以实现用于将FOWLP封装连接在PCB上的期望的非常低的寄生电容。
此外，翻转Sipho管芯130，以使前表面130F面向FOWLP封装的模制材料110的前表面112。通过将多个导体凸块139直接接合到形成在模制材料110中的多个TMV中的焊接材料129的相应顶端部分上，来执行管芯上封装工艺。再次，Sipho管芯130在FOWLP封装上的连接不需要引线接合，甚至对于一个或多个激光二极管132的电源线。相反，TMV技术用于在FOWLP封装中在顶部Sipho管芯和底部电子管芯之间进行垂直互连。通过选择SiGe、GaAs或CMOS技术并在45nm、28nm、20nm CMOS技术扩大下增强CDR或PAM4ASIC的性能，这为各种电子技术节点提供了巨大的灵活性，并且有利于光收发器设计者改变用于优化调制器驱动器/TIA模块的性能的特定技术。
参考图5D，在PCB上组装的光收发器的可替换的横截面图中，在FOLLP封装芯片上的Sipho管芯130的DoP工艺多芯片堆叠之后，一个或多个光纤138连接到在Sipho管芯130的前表面130F的边缘上一个或多个预制的光纤耦合结构136。现在，光纤耦合结构136的位置在模制材料110的前表面130F和前端表面111之间的某处。在一个实施例中，Sipho管芯130的前表面130F从端部区域适当地凹陷，以允许用于安装光纤138的空间，使得光纤纤芯可以适当地对准(并固定)到Sipho管芯130中的光波导。当然，本领域的技术人员应认识到关于在紧凑型光收发器上的光纤安装的许多变化、替换以及修改。

Claims (11)

1.一种利用混合多芯片集成的光收发器，其特征在于，包括：
PCB，具有多个预制表面接合位点；
第一芯片，包括嵌入在覆盖电介质再分布层的电介质模制层内的多个电子装置，通过分别在所述多个预制表面接合位点经由多个导体球接合所述电介质再分布层同时暴露填充在多个模制通孔TMV中的焊接材料，将所述第一芯片设置在所述PCB上，所述多个TMV形成在所述电介质模制层中；以及
第二芯片，包括嵌入在SOI晶片中的光子装置，所述第二芯片具有添加有多个导体凸块的前表面，所述第二芯片堆叠在所述第一芯片上方，其中，在所述前表面上的所述多个导体凸块分别接合到所述多个TMV中的所述焊接材料。
2.根据权利要求1所述的光收发器，其特征在于，所述第一芯片包括在覆盖用于所述电介质再分布层的HD-8940PBO膜的扇出晶片级封装(FOWLP)架构下使用用于所述电介质模制层的嵌入绝缘片(EBIS)型材料封装在一起的多个电子管芯。
3.根据权利要求1所述的光收发器，其特征在于，所述多个电子装置包括PAM4ASIC模块、驱动器模块、跨阻抗放大器模块以及多个AC耦合电容器。
4.根据权利要求1所述的光收发器，其特征在于，所述多个导体球中的每个接合到嵌入在所述电介质再分布层中的第一导电焊盘。
5.根据权利要求1所述的光收发器，其特征在于，填充在所述多个TMV中的每个中的所述焊接材料接合到嵌入在所述电介质再分布层中的第二导电焊盘。
6.根据权利要求1所述的光收发器，其特征在于，所述第二芯片是基本上没有硅通孔结构的Si光子芯片。
7.根据权利要求6所述的光收发器，其特征在于，所述光子装置包括基于Si的光波导、调制器以及多个光电二极管。
8.根据权利要求6所述的光收发器，其特征在于，所述第二芯片还包括一个或多个激光二极管，所述一个或多个激光二极管安装在所述前表面的凹陷区域上并且经由安装焊盘与所述多个导体凸块中的一个或多个电耦接，以通过在所述电介质再分布层中的一个或多个导电焊盘以及所述多个导体球中的一个或多个连接到所述PCB，而无需任何外部引线接合。
9.根据权利要求6所述的光收发器，其特征在于，所述第二芯片还包括形成在所述前表面的边缘附近的一个或多个光纤耦合结构。
10.根据权利要求7所述的光收发器，其特征在于，所述电介质再分布层还包括嵌入导线，所述嵌入导线用于分别通过填充在所述多个TMV中的所述焊接材料和在所述第二芯片的所述前表面上的所述多个导体凸块，来将所述多个电子装置选择性地连接到至少所述调制器和所述多个光电二极管。
11.根据权利要求10所述的光收发器，其特征在于，还包括安装在一个或多个光纤耦合结构中的一个或多个光纤，所述一个或多个光纤在所述第二芯片的前表面和所述第一芯片的所述电介质模制层之间，以与对应的基于Si的光波导耦合。
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