WO2024022113A1 - 片上光互连结构及其制作方法 - Google Patents

片上光互连结构及其制作方法 Download PDF

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Publication number
WO2024022113A1
WO2024022113A1 PCT/CN2023/107090 CN2023107090W WO2024022113A1 WO 2024022113 A1 WO2024022113 A1 WO 2024022113A1 CN 2023107090 W CN2023107090 W CN 2023107090W WO 2024022113 A1 WO2024022113 A1 WO 2024022113A1
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Prior art keywords
integrated circuit
photonic integrated
chip
circuit chips
optical
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Application number
PCT/CN2023/107090
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English (en)
French (fr)
Inventor
沈亦晨
孟怀宇
江卢山
Original Assignee
上海曦智科技有限公司
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Publication of WO2024022113A1 publication Critical patent/WO2024022113A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/26—Optical coupling means
    • G02B6/262—Optical details of coupling light into, or out of, or between fibre ends, e.g. special fibre end shapes or associated optical elements
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/26—Optical coupling means
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00

Definitions

  • the present application relates to the field of optical interconnection technology, and more specifically, to an on-chip optical interconnection structure and a manufacturing method thereof.
  • Silicon photonics may be the most promising technology, enabling high-bandwidth links, for example, by parallelizing multiple channels through wavelength division multiplexing (WDM).
  • WDM wavelength division multiplexing
  • optical interconnection technology usually refers to on-chip interconnection, that is, based on optical interconnection within a single chip.
  • chip size including silicon photonic chips.
  • the optical interconnect Lian's technology applications are limited and unable to realize the technology's full potential.
  • Embodiments of the present application provide an on-chip optical interconnection structure and a manufacturing method thereof to solve the problem that existing on-chip optical interconnection technology is limited by the size of a single photonic integrated circuit chip.
  • an on-chip optical interconnect structure including:
  • a semiconductor wafer including a plurality of first photonic integrated circuit chips, each of the first photonic integrated circuit chips having opposing first and second surfaces, wherein each of the first photonic integrated circuit chips including a plurality of first optical waveguides;
  • Each second photonic integrated circuit chip includes a plurality of second optical waveguides.
  • Each second photonic integrated circuit chip is fixed to two adjacent first photonic integrated circuit chips. Part of the circuit chip is on the first surface and covers two adjacent first photonic integrated circuits The corresponding area boundary of the chip on the semiconductor wafer;
  • the two adjacent first photonic integrated circuit chips are connected by the second photonic integrated circuit chip fixed on part of the first surface of the two adjacent first photonic integrated circuit chips.
  • Optical interconnect Optical interconnect.
  • the second plurality of photonic integrated circuit chips are passive photonic integrated circuit chips.
  • the plurality of first optical waveguides of the two adjacent first photonic integrated circuit chips are connected to The plurality of second optical waveguides of the second photonic integrated circuit chip fixed on part of the first surface of the two adjacent first photonic integrated circuit chips are in one-to-one correspondence, so as to connect the phases Two adjacent first photonic integrated circuit chips are optically interconnected.
  • the projections of the ends of the plurality of first optical waveguides of the two adjacent first photonic integrated circuit chips are fixed to the adjacent ones.
  • the projections of the ends of the plurality of second optical waveguides of each of the second photonic integrated circuit chips on the first surface of portions of the two first photonic integrated circuit chips are in a one-to-one correspondence. overlap.
  • the first surface of the adjacent two first photonic integrated circuit chips is close to the Two adjacent first photonic integrated circuit chips are each provided with at least one beam redirection element at corresponding area boundaries on the semiconductor wafer, wherein each of the beam redirection elements is used to change the direction of the light beam to into each of the first optical waveguides and/or each of the second optical waveguides; for the components fixed on the first surfaces of the two adjacent first photonic integrated circuit chips
  • the second photonic integrated circuit chip has a set of grating couplers disposed on both sides of the plurality of second optical waveguides of the second photonic integrated circuit chip in a direction parallel to the plane of the second photonic integrated circuit chip, Each group of grating couplers corresponds one-to-one to the plurality of first optical waveguides of the two adjacent first photonic integrated circuit chips and is used for optical coupling, wherein each group of grating couplers It includes at least one grating coupler element;
  • each of the first photonic integrated circuit chips includes a plurality of metal connection posts, and one side surface of the metal connection posts is separated from the surface of each of the first photonic integrated circuit chips. The first surface is exposed.
  • the on-chip optical interconnect structure further includes at least one electronic integrated circuit chip secured to the first surface of at least one first photonic integrated circuit chip.
  • a plurality of optical coupling regions are provided on the first surface of the semiconductor wafer, and an optical coupling interface is provided in each of the optical coupling regions.
  • the on-chip optical interconnect structure further includes a plurality of dummy chips, and the plurality of dummy chips are fixed to the plurality of optical coupling areas on the first surface of the semiconductor wafer in one-to-one correspondence. on the top, wherein each of the dummy chips has a cavity with upper and lower openings, and the opening of the cavity faces the optical coupling interface and covers the optical coupling interface.
  • the on-chip optical interconnect structure further includes a plastic encapsulation layer covering the first surface of the semiconductor wafer and covering sides, at least one of the plurality of dummy chips. sides of the electronic integrated circuit chip and the plurality of second photonic integrated circuit chips.
  • the on-chip optical interconnect structure further includes a plurality of light guide structures, the plurality of light guide structures correspond to the plurality of dummy chips, wherein each of the light guide structures passes through The cavity of each dummy chip is used to couple optical signals to the corresponding optical coupling interface.
  • a method for manufacturing an on-chip optical interconnect structure including:
  • a semiconductor wafer including a plurality of first photonic integrated circuit chips, each of the first photonic integrated circuit chips having opposing first and second surfaces, wherein each of the first photonic integrated circuit chips
  • the chip includes a plurality of first optical waveguides
  • a plurality of second photonic integrated circuit chips are provided, each of the second photonic integrated circuit chips includes a plurality of second optical waveguides, and each of the second photonic integrated circuit chips is fixed to two adjacent first photonic integrated circuit chips. Part of the first surface of the photonic integrated circuit chip and covering the corresponding area boundaries of the two adjacent first photonic integrated circuit chips on the semiconductor wafer;
  • the plurality of second optical waveguides of each second photonic integrated circuit chip are connected to the two adjacent first photonic integrated circuit chips.
  • the plurality of first optical waveguides of the first photonic integrated circuit chip are aligned one by one to optically interconnect the two adjacent photonic integrated circuit chips.
  • the method further includes: connecting each of the second photonic integrated circuit chips being fixed on part of the first surface of two adjacent first photonic integrated circuit chips in a back-mounted manner and covering the two adjacent first photonic integrated circuit chips on the semiconductor wafer the corresponding area boundary; or
  • the method further includes: connecting the ends of the plurality of first optical waveguides of the two adjacent first photonic integrated circuit chips in the thickness direction of the semiconductor wafer. Projecting and fixing the end portions of the plurality of second optical waveguides of each second photonic integrated circuit chip on the portion of the first surface of the two adjacent first photonic integrated circuit chips. The projections overlap in a one-to-one correspondence manner to optically interconnect the two adjacent first photonic integrated circuit chips through adiabatic coupling.
  • the method further includes: placing a position on the first surface of the adjacent two first photonic integrated circuit chips close to the two adjacent first photonic integrated circuit chips. At least one beam redirecting element is placed at each corresponding area boundary on the semiconductor wafer; wherein each beam redirecting element is used to change the direction of the beam to enter each of the first optical waveguides and/or each in the second optical waveguide; and for the second photonic integrated circuit chip fixed on the first surface of part of the two adjacent first photonic integrated circuit chips, in parallel with the second In the direction of the plane where the photonic integrated circuit chip is located, a group of grating couplers is formed on both sides of the plurality of second optical waveguides of the second photonic integrated circuit chip, and each group of the grating couplers is respectively connected to the adjacent
  • the plurality of first optical waveguides of the two photonic integrated circuit chips correspond one to one and are used for optical coupling, wherein each group of the grating couplers includes at least one grating coupler element; wherein two adjacent grating couple
  • the method further includes: fabricating a plurality of metal connection posts in each of the first photonic integrated circuit chips, and removing one side surface of the metal connection posts from each of the first photonic integrated circuit chips. The first surface of the integrated circuit chip is exposed.
  • the method further includes: placing each of the second photonic integrated circuit cores The sheet is fixed on part of the first surface of the two adjacent first photonic integrated circuit chips and covers the two adjacent first photonic integrated circuit chips behind the corresponding area boundary on the semiconductor wafer. , for at least one first photonic integrated circuit chip, provide at least one electronic integrated circuit chip corresponding to the first photonic integrated circuit chip, and fix the at least one electronic integrated circuit chip on the first photonic integrated circuit chip corresponding area of the first surface.
  • the method further includes: arranging a plurality of optical coupling areas on the first surface of the semiconductor wafer, and arranging an optical coupling interface in each of the optical coupling areas; and providing a plurality of dummy chips.
  • each of the dummy chips has a cavity with a single side opening, and the plurality of dummy chips are fixed on the plurality of optical coupling areas one by one, so that the cavity of each dummy chip is The opening faces the optical coupling interface and covers the optical coupling interface.
  • the method further includes: after fixing the plurality of dummy chips on the plurality of optical coupling areas one by one, forming a plastic encapsulation layer on the first surface of the semiconductor wafer.
  • the plastic encapsulation layer covers the side surfaces of the plurality of dummy chips, the side surfaces of the at least one electronic integrated circuit chip and the plurality of second photonic integrated circuit chips.
  • the method further includes: after the plastic encapsulation layer is produced, thinning the body of the semiconductor wafer on a side of the semiconductor wafer away from the plurality of second photonic integrated circuit chips. Processing to expose the surface of the metal connecting post on the side away from the plurality of second photonic integrated circuit chips.
  • forming a connection with each of the metal connection posts on the second surface of the semiconductor wafer after exposing the surface of the metal connection post on a side away from the plurality of second photonic integrated circuit chips, forming a connection with each of the metal connection posts on the second surface of the semiconductor wafer.
  • the method further includes: thinning the plastic encapsulation layer and the plurality of dummy chips so that the cavities of the plurality of dummy chips are connected up and down and the plurality of electronic integrated circuit chips are away from the One side surface of the semiconductor wafer is exposed.
  • the method further includes: installing a light guide structure or a laser chip onto the corresponding optical coupling interface through the opening of each dummy chip.
  • the on-chip optical interconnection structure and the manufacturing method thereof provided by the present invention are provided on the semiconductor wafer having a plurality of first photonic integrated circuit chips with a portion of the first photonic integrated circuit chip covering two adjacent first photonic integrated circuit chips.
  • a surface of a second photonic integrated circuit chip utilizing the second photonic integrated circuit chip A plurality of second optical waveguides are used to optically interconnect two adjacent first photonic integrated circuit chips, thereby achieving uninterrupted on-chip optical interconnection at the wafer level to improve the performance and performance of the on-chip optical network.
  • Value It has broken through the upper limit of the size of a single First Photonic integrated circuit chip, and can select the number of First Photonic integrated circuit chips in the same optical communication according to needs, and the design is flexible.
  • FIG. 1A is a schematic top view of an on-chip optical interconnection structure provided according to an embodiment of the present invention.
  • FIG. 1B is a schematic side structural diagram of an on-chip optical interconnect structure provided according to an embodiment of the present invention.
  • FIG. 2 shows the optical interaction between the plurality of first optical waveguides of two adjacent first photonic integrated circuit chips through the plurality of second optical waveguides of the second photonic integrated circuit chip in the embodiment of FIG. 1A .
  • FIG. 3 is a diagram showing the optical interaction between the plurality of first optical waveguides of two adjacent first photonic integrated circuit chips through the plurality of second optical waveguides of the second photonic integrated circuit chip in the embodiment of FIG. 1A .
  • FIG. 4A is a schematic top view of another on-chip optical interconnect structure provided according to an embodiment of the present invention.
  • FIG. 4B is a schematic side view of another on-chip optical interconnect structure provided according to an embodiment of the present invention.
  • FIG. 5 is a schematic side view of another on-chip optical interconnect structure provided according to an embodiment of the present invention.
  • FIG. 6 is a flow chart of a method for manufacturing an on-chip optical interconnect structure according to an embodiment of the present invention.
  • FIGS. 7A-7I are schematic diagrams of the manufacturing process of a method for manufacturing an on-chip optical interconnect structure according to an embodiment of the present invention.
  • connection should be understood in a broad sense.
  • connection or integral connection; it can be mechanical connection, electrical connection or mutual communication; it can be direct connection, or indirect connection through an intermediary, it can be internal connection of two elements or interaction of two elements relation.
  • the meaning of chip in this article may include bare chips.
  • embodiments of the present invention propose an on-chip optical interconnection structure and a manufacturing method thereof, aiming to achieve uninterrupted on-chip optical interconnection within the wafer level.
  • FIG. 1A is a schematic top structural view of an on-chip optical interconnection structure provided according to an embodiment of the present invention.
  • FIG. 1B is a schematic side structural view of an on-chip optical interconnection structure provided according to an embodiment of the present invention.
  • the on-chip optical interconnection structure includes: a semiconductor wafer 100 , the semiconductor wafer 100 includes a plurality of first photonic integrated circuit chips 102 , each of the first photonic integrated circuit chips 102 has The opposite first surface 102a and the second surface 102b, wherein each of the first photonic integrated circuit chips 102 includes a plurality of first optical waveguides 110; a plurality of second photonic integrated circuit chips 200, each of the second The photonic integrated circuit chip 200 includes a plurality of second optical waveguides 210, and each second photonic integrated circuit chip 200 is fixed on part of the first surface 102a of two adjacent first photonic integrated circuit chips 102.
  • the second photonic integrated circuit chip 200 is optically interconnected on portions of the first surface 102a of the two first photonic integrated circuit chips 102.
  • the semiconductor wafer 100 is, for example, a motherboard photonic wafer, and a plurality of first photonic integrated circuit chips 102 are prepared on the motherboard photonic wafer.
  • the first photonic integrated circuit chip 102 uses photons as information carriers to process and transmit information, and may be a silicon-based photonic integrated circuit chip.
  • a dicing lane may be provided between two adjacent first photonic integrated circuit chips 102 , and the dicing lane represents the space reserved for cutting on the motherboard photonic wafer.
  • the corresponding area boundaries of two adjacent first photonic integrated circuit chips 102 on the semiconductor wafer 100 may be between the two adjacent first photonic integrated circuit chips 102
  • the dicing lane is provided, and the dicing lane between the two adjacent first photonic integrated circuit chips 102 with the second photonic integrated circuit chip 200 fixed above does not carry out the step of chip cutting and separation into separate chips.
  • Two adjacent first photonic integrated circuit chips 102 are chips connected together to enhance the optical path alignment of the first photonic integrated circuit chip 102 and the second photonic integrated circuit chip 200 and improve optical coupling. efficiency, while saving process costs Book.
  • the technical solution provided by the embodiment of the present invention is to provide a semiconductor wafer having a plurality of first photonic integrated circuit chips by covering a portion of the first surface of two adjacent first photonic integrated circuit chips.
  • the second photonic integrated circuit chip uses a plurality of second optical waveguides of the second photonic integrated circuit chip to optically interconnect the two adjacent first photonic integrated circuit chips, thereby achieving seamless wafer level On-chip optical interconnection to improve the performance and application value of Optical Network-on-Chip (ONOC). It has broken through the upper limit of the size of a single First Photonic integrated circuit chip, and can select the number of First Photonic integrated circuit chips in the same optical communication according to needs, and the design is flexible.
  • the plurality of first optical waveguides 110 and the plurality of second optical waveguides 210 perform multi-channel transmission in a parallel manner, which can significantly increase the number of Transmitted optical communication capacity.
  • the second plurality of photonic integrated circuit chips 200 are passive photonic integrated circuit chips. That is, each second photonic integrated circuit chip 200 does not need to be provided with additional power during normal operation.
  • a plurality of second optical waveguides 210 provided in each second photonic integrated circuit chip 200 are used for optical signal transmission, and each second photonic integrated circuit chip 200 does not generate any harmonics during normal operation. Wave.
  • the plurality of second optical waveguides 210 of each second photonic integrated circuit chip 200 are patterned and formed based on the first area on the semiconductor layer.
  • the semiconductor layer is, for example, SOI ( A plurality of second optical waveguides 210 are formed on the top silicon of a Silicon on Insulator (Silicon on Insulator) structure by wet etching or laser ablation.
  • SOI Silicon on Insulator
  • other methods may be used to form multiple second optical waveguides 210 on the second photonic integrated circuit chip 200 .
  • the embodiments of the present invention are not limited here.
  • FIG. 2 shows the optical interaction between the plurality of first optical waveguides of two adjacent first photonic integrated circuit chips through the plurality of second optical waveguides of the second photonic integrated circuit chip in the embodiment of FIG. 1A .
  • all of the two adjacent first photonic integrated circuit chips 102 that are optically interconnected, all of the two adjacent first photonic integrated circuit chips 102
  • the plurality of second optical waveguides 210 of the second photonic integrated circuit chip 200 on the first surface 102a are arranged in one-to-one correspondence, so that the two adjacent first photonic integrated circuit chips 102 are Optical interconnect.
  • the projections of the ends of the plurality of first optical waveguides 110 of the two adjacent first photonic integrated circuit chips 102 are different from those fixed on The ends of the plurality of first optical waveguides 110 of each second photonic integrated circuit chip 200 on the part of the first surface 102a of the two adjacent first photonic integrated circuit chips 102 and The projections of the ends of the second optical waveguide 210 overlap in a one-to-one correspondence.
  • the ends of the plurality of first optical waveguides 110 of the two adjacent first photonic integrated circuit chips 102 realize the connection between the two adjacent first photonic integrated circuit chips 102 through adiabatic coupling. optical interconnection.
  • FIG. 3 is a diagram showing the optical interaction between the plurality of first optical waveguides of two adjacent first photonic integrated circuit chips through the plurality of second optical waveguides of the second photonic integrated circuit chip in the embodiment of FIG. 1A .
  • the two adjacent first photonic integrated circuit chips 102 are On the first surface 102a, at least one beam redirecting element 810 is respectively provided at the corresponding area boundary of the two adjacent first photonic integrated circuit chips 102 on the semiconductor wafer 100, wherein each of the beam redirecting elements 810
  • the redirecting element 810 is used to change the direction of the light beam to enter each of the first optical waveguides 110 and/or each of the second optical waveguides 210; for the two adjacent first photon integration fixed
  • the second photonic integrated circuit chip 200 on part of the first surface 102a of the circuit chip 102 is located on all parts of the second photonic integrated circuit chip 200 in a direction parallel to the plane where the second photonic integrated circuit chip 200 is located.
  • a group of grating couplers 213 are disposed on both sides of the plurality of second optical waveguides 210. Each group of the grating couplers 213 is respectively connected to the plurality of adjacent first photonic integrated circuit chips 102.
  • the first optical waveguides 110 correspond one to one and are used for optical coupling, wherein each group of grating couplers 213 includes at least one grating coupler element; wherein two adjacent first photonic integrated circuit chips 102 pass through
  • the beam redirecting element 810, the two sets of grating couplers 213 and the plurality of second optical waveguides 210 are optically interconnected.
  • the beam redirecting element 810 may be a prism assembly, which is used to change the transmission direction of the beam to enter each of the first optical waveguides 110 and/or each In the second optical waveguide 210, specifically, the prism component is a triangular prism having two right-angled sides and a hypotenuse.
  • the plurality of adjacent first photonic integrated circuit chips 102 are The ends of each first optical waveguide 110 are facing the hypotenuse of the prism assembly, so as to change the propagation direction of the light beam transmitted by the plurality of first optical waveguides 110 of a first photonic integrated circuit chip 102 by 90 degrees and then pass through a One group of the grating couplers 213 is transmitted to the plurality of second optical waveguides 210 of the second photonic integrated circuit chip 200, and another group of the grating couplers 213 is transmitted to another first photonic integrated circuit chip. 102, thereby realizing optical interconnection between two adjacent first photonic integrated circuit chips 102.
  • a groove can be opened on the first surface 102 a of each first photonic integrated circuit chip 102 , and the beam redirecting element 810 can be accommodated in the groove.
  • the groove on the one hand, it plays a role of fixing and limiting, and on the other hand, it can also adjust the light beams of the plurality of first optical waveguides 110 of the two adjacent first photonic integrated circuit chips 102 to be incident/ It is emitted to the middle of the beam redirecting element 810 to avoid unnecessary light loss.
  • each of the first photonic integrated circuit chips 102 includes a plurality of metal connection posts 1022 , and one side surface of the metal connection posts 1022 is separated from each of the first photonic integrated circuit chips 102 .
  • the first surface 102a of a photonic integrated circuit chip 102 is exposed.
  • FIG. 4A is a schematic top view of another on-chip optical interconnect structure provided according to an embodiment of the present invention.
  • FIG. 4B is a schematic side view of another on-chip optical interconnect structure provided according to an embodiment of the present invention.
  • the on-chip optical interconnect structure further includes at least one electronic integrated circuit chip 300 fixed on the first surface 102 a of at least one first photonic integrated circuit chip 102 .
  • Each of the electronic integrated circuit chips 300 uses electrons as information carriers to process information and transmit data, such as silicon-based electronic integrated circuit chips, germanium-based electronic integrated circuit chips or compound semiconductor electronic integrated circuit chips. Integration of the photonic integrated circuit chip and the electronic integrated circuit chip can be achieved by stacking at least one of the first photonic integrated circuit chip 102 and the at least one electronic integrated circuit chip 300 .
  • At least one electronic integrated circuit chip 300 may be fixed to the non-light coupling area and non-photonic coupling area on the first surface 102a of at least one first photonic integrated circuit chip 102 by welding or other means. The area covered by the two-photon integrated circuit chip 200.
  • the at least one electronic integrated circuit chip 300 is soldered to the on the first surface 102a of the at least one first photonic integrated circuit chip 102.
  • an under fill is filled in the gap between each electronic integrated circuit chip 300 and the first surface 102a to further strengthen each electronic integrated circuit chip 300.
  • one electronic integrated circuit chip 300 is formed above the first surface 102a of the first photonic integrated circuit chip 102. In actual use, there may be more than one electronic integrated circuit chip.
  • the chips 300 such as 2, 3, 4 or more, can be flexibly selected according to actual needs.
  • a plurality of optical coupling regions 1024 are provided on the first surface 102a of the semiconductor wafer 100, and an optical coupling interface 104 is provided in each of the optical coupling regions 1024.
  • a part of the optical coupling interface 104 allows the light provided by an external light source to be input into the optical coupling interface 104 through a light guide structure 600 such as a fiber array (Fiber Array, FA), thereby allowing the optical signal to be transmitted in each of the first photonic integrated circuit chips. Transmission is performed in the plurality of first optical waveguides 110 of 102. For example, it is coupled into the first photonic integrated circuit chip 102 through a grating coupler in the optical coupling interface 104 .
  • optical coupling interface 104 allows the optical signals transmitted/processed by the plurality of first photonic integrated circuit chips 102 to be transmitted to the integrated circuit chip structure on its substrate through a light guide structure 600 such as an optical fiber array for subsequent processing.
  • a light guide structure 600 such as an optical fiber array for subsequent processing.
  • the position of the optical coupling interface 104 can be set according to actual needs, making the layout more flexible. It should be noted that in other embodiments, other optical interconnection interfaces or devices for transmitting optical signals may also be provided in the optical coupling interface 104 accordingly.
  • FIG. 5 is a schematic side view of another on-chip optical interconnect structure provided according to an embodiment of the present invention.
  • the on-chip optical interconnection structure further includes a plurality of dummy chips 400 .
  • the plurality of dummy chips 400 correspond to the plurality of dummy chips fixed on the first surface 102 a of the semiconductor wafer 100 in one-to-one correspondence.
  • Each of the dummy chips 400 has a cavity with upper and lower openings, and the opening of the cavity faces the optical coupling interface 104 and covers the optical coupling interface 104 .
  • the on-chip optical interconnect structure further includes a plastic encapsulation layer 106 covering the first surface 102 a of the semiconductor wafer 100 and covering the plurality of dummy chips. 400 , the at least one electronic integrated circuit chip 300 and the plurality of second photonic integrated circuit chips 200 .
  • the on-chip optical interconnect structure further includes a plurality of light guide structures 600, and the plurality of light guide structures 600 Each light guide structure 600 corresponds to the plurality of dummy chips 400 one-to-one, wherein each light guide structure 600 passes through the cavity of each dummy chip 400 to couple the optical signal to the corresponding The optical coupling interface 104.
  • a method for manufacturing an on-chip optical interconnection structure is also provided.
  • FIG. 6 is a flow chart of a method for manufacturing an on-chip optical interconnect structure according to an embodiment of the present invention.
  • the manufacturing method of the on-chip optical interconnect structure includes:
  • the semiconductor wafer includes a plurality of first photonic integrated circuit chips, each of the first photonic integrated circuit chips has an opposite first surface and a second surface, wherein each of the first photonic integrated circuit chips
  • the integrated circuit chip includes a plurality of first optical waveguides
  • each of the second photonic integrated circuit chips includes a plurality of second optical waveguides, and fix each of the second photonic integrated circuit chips to two adjacent ones. part of the first surface of the first photonic integrated circuit chip and covering the corresponding area boundaries of the two adjacent first photonic integrated circuit chips on the semiconductor wafer;
  • the plurality of second optical waveguides of each second photonic integrated circuit chip are connected to the two adjacent first photonic integrated circuit chips.
  • the plurality of first optical waveguides of the first photonic integrated circuit chip are aligned one by one to optically interconnect the two adjacent photonic integrated circuit chips.
  • FIGS. 7A-7I are schematic diagrams of the manufacturing process of a method for manufacturing an on-chip optical interconnect structure according to an embodiment of the present invention.
  • a semiconductor wafer 100 is first provided.
  • the semiconductor wafer 100 includes a plurality of first photonic integrated circuit chips 102 , each of the first photonic integrated circuit chips 102 having an opposite first surface. 102a and the second surface 102b, wherein each of the first photonic integrated circuit chips 102 includes a plurality of first optical waveguides 110.
  • the semiconductor wafer 100 is, for example, a motherboard photonic wafer.
  • the motherboard photonic wafer has a plurality of first photonic integrated circuit chips 102. Between two adjacent second photonic integrated circuit chips 102, There may be dicing lanes between a photonic integrated circuit chip 102.
  • the dicing lanes represent the space reserved for cutting on the motherboard photonic wafer, so that subsequent light transmission can be carried according to the requirements of the same optical communication.
  • the signal capacity size is separated between chips to select an appropriate number of first photonic integrated circuit chips 102 for optical interconnection.
  • Each of the second photonic integrated circuit chips 200 includes a plurality of second optical waveguides 210 .
  • Each of the second photonic integrated circuit chips 200 is fixed on part of the first surface 102a of the two adjacent first photonic integrated circuit chips 102 and covering the corresponding portions of the two adjacent first photonic integrated circuit chips 102 on the semiconductor wafer 100 Area boundary; wherein, the area boundary corresponding to two adjacent first photonic integrated circuit chips 102 on the semiconductor wafer 100 may be a dicing lane between two adjacent first photonic integrated circuit chips 102; wherein , for the two adjacent first photonic integrated circuit chips 102 that are optically interconnected, connect the plurality of second optical waveguides 210 of each second photonic integrated circuit chip 200 with the two adjacent ones.
  • the plurality of first optical waveguides 110 of each first photonic integrated circuit chip 102 are aligned one by one to optically interconnect the two adjacent photonic integrated circuit chips 102 .
  • the plurality of second photonic integrated circuit chips 200 are passive photonic integrated circuit chips. Each of the second photonic integrated circuit chips 200 does not need to be provided with additional power during normal operation. A plurality of second optical waveguides 210 provided in each second photonic integrated circuit chip 200 are used for optical signal transmission, and each second photonic integrated circuit chip 200 does not generate any harmonics during normal operation. Wave.
  • the plurality of second optical waveguides 210 of each second photonic integrated circuit chip 200 are patterned and formed based on the first area on the semiconductor layer.
  • the semiconductor layer is, for example, SOI ( A plurality of second optical waveguides 210 are formed on the top silicon of a Silicon on Insulator (Silicon on Insulator) structure by wet etching or laser ablation.
  • SOI Silicon on Insulator
  • other methods may be used to form multiple second optical waveguides 210 on the second photonic integrated circuit chip 200 .
  • the embodiments of the present invention are not limited here.
  • each second photonic integrated circuit chip 200 is fixed to two adjacent first photonic integrated circuit chips 102 in a back-mounted manner. part of the first surface 102a and covers two adjacent first photons The integrated circuit chip 102 corresponds to the area boundary on the semiconductor wafer 100 .
  • each second photonic integrated circuit chip 200 can also be removed, and each second photonic integrated circuit with the bottom semiconductor layer removed can also be removed.
  • the chip 200 is fixed on part of the first surface 102a of the two adjacent first photonic integrated circuit chips 102 in a front-mounted manner and covers the adjacent two first photonic integrated circuit chips 102. Corresponding area boundaries on the semiconductor wafer 100 .
  • the ends of the plurality of first optical waveguides 110 of the two adjacent first photonic integrated circuit chips 102 are The plurality of second optical waveguides 210 of each second photonic integrated circuit chip 200 are projected and fixed on the portion of the first surface 102a of the two adjacent first photonic integrated circuit chips 102 The projections of the ends overlap in a one-to-one correspondence to achieve optical interconnection between the two adjacent first photonic integrated circuit chips 102 through adiabatic coupling.
  • the adjacent two first photonic integrated circuit chips 102 are close to each other.
  • At least one beam redirecting element 810 is placed at each corresponding area boundary on the semiconductor wafer 100; wherein each beam redirecting element 810 is used to change the direction of the beam to enter each of the first optical waveguides 110 and /or in each second optical waveguide 210; and for the second photonic integrated circuit chip fixed on the part of the first surface 102a of the two adjacent first photonic integrated circuit chips 102 200.
  • a set of grating couplers 213 is formed on both sides of the plurality of second optical waveguides 210 of the second photonic integrated circuit chip 200,
  • Each group of grating couplers 213 corresponds one-to-one to the plurality of first optical waveguides 110 of the two adjacent photonic integrated circuit chips 102 and is used for optical coupling, wherein each group of grating couplers
  • the device 213 includes at least one grating coupler element; wherein the two adjacent first photonic integrated circuit chips 102 pass through the beam redirection element 810, two sets of grating couplers 213 and the plurality of second optical waveguides. 210 for optical interconnection.
  • the grating coupler 213 may be a loop-back grating coupler having multiple channels.
  • a plurality of metal connection posts 1022 are made in each of the first photonic integrated circuit chips 102, and one side surface of the metal connection posts 1022 is removed from each of the first photonic integrated circuit cores. The first surface 102a of the sheet 102 is exposed.
  • the conductive vias can be manufactured using "Through Silicon Via" (TSV) technology.
  • TSV is a high-density packaging technology that is gradually replacing the current wire bonding technology that is relatively mature.
  • TSV technology realizes the vertical electrical interconnection of through silicon holes by filling them with conductive materials such as copper, tungsten, and polysilicon.
  • the TSV process may include deep silicon etching to form microvias or blind vias, deposition of insulating layers/barrier layers/seed layers, deep hole filling, chemical mechanical polishing, thinning, and redistribution lead preparation and other process technologies.
  • the process methods for forming conductive vias in a photonic integrated circuit chip 102 include but are not limited to laser etching, deep reactive ion etching, etc. After forming the conductive vias, processes such as deep hole filling are used to remove conductive materials (such as metals). of filling. The present invention will not be described in detail here.
  • each second photonic integrated circuit chip 200 is fixed on part of the first surface 102 a of the two adjacent first photonic integrated circuit chips 102 . And after covering the corresponding area boundaries of the two adjacent first photonic integrated circuit chips 102 on the semiconductor wafer 100, for at least one of the first photonic integrated circuit chips 102, the first photonic integrated circuit chip is provided.
  • the chip 102 corresponds to at least one electronic integrated circuit chip 300, and the at least one electronic integrated circuit chip 300 is fixed on the corresponding area of the first surface 102a of the first photonic integrated circuit chip 102.
  • a plurality of optical coupling regions 1024 are formed on the first surface 102 a of the semiconductor wafer 100 , and an optical coupling interface 104 is provided in each of the optical coupling regions 1024 .
  • multiple dummy chips 400 are provided. Each of the dummy chips 400 has a cavity with a single side opening. The multiple dummy chips 400 are They are fixed on the plurality of optical coupling areas 1024 in one-to-one correspondence, so that the opening of the cavity of each dummy chip 400 faces the optical coupling interface 104 and covers the optical coupling interface 104 .
  • the dummy chip 400 and its cavity can form a closed protective space for the optical coupling interface 104 to prevent the organic material in the plastic layer from being exposed to light during the subsequent plastic packaging process of the on-chip optical interconnect structure.
  • Organic matter remains behind the coupling area, which seriously affects the coupling efficiency of the optical coupling interface 104 , resulting in serious light loss, thereby affecting the normal operation of the first photonic integrated circuit chip 102 .
  • the dummy chip 400 refers to a wafer that does not have any photonic devices or electronic devices integrated thereon, such as a bare silicon wafer.
  • the plastic encapsulation layer 106 covers the side surfaces of the plurality of dummy chips 400 , the side surfaces of the at least one electronic integrated circuit chip 300 and the plurality of second photonic integrated circuit chips 200 .
  • the injection molding material of the plastic sealing layer 106 may be, for example, epoxy resin, which covers the first surface 102a of the semiconductor wafer 100 in a molten state, and forms the plastic sealing layer 106 after solidification, so that the polyethylene wafer 106 is molded.
  • Each dummy chip 400, the at least one electronic integrated circuit chip 300 and the plurality of second photonic integrated circuit chips 200 are firmly fixed at corresponding positions on the semiconductor wafer 100, thereby forming a stable packaging structure.
  • the body of the semiconductor wafer 100 is thinned on the side of the semiconductor wafer 100 away from the plurality of second photonic integrated circuit chips 200 .
  • the body of the semiconductor wafer 100 is thinned on the side of the semiconductor wafer 100 away from the plurality of second photonic integrated circuit chips 200 .
  • the plastic encapsulation layer 106 and the plurality of dummy chips 400 are thinned so that the cavities of the plurality of dummy chips 400 are connected up and down and the cavities of the plurality of electronic integrated circuit chips 300 are away from the semiconductor.
  • One surface of the wafer 100 is exposed.
  • the semiconductor wafer 100 is The second surface 102b is fixed to the package substrate 500.
  • the light guide structure 600 or the laser chip is installed on the corresponding optical coupling interface 104 through the opening of each dummy chip 400 .
  • the light guide structure shown 600 represents an optical fiber array.
  • the optical fiber array passes through the cavity of each dummy chip 400 and is coupled to the optical coupling interface 104.
  • optical coupling glue can be used to obliquely couple the optical fiber array to the optical coupling interface 104.
  • an optical fiber array may be coupled to an optical coupling interface of an optical coupler at an angle of 45° relative to the first surface 102a of the semiconductor wafer 100, and the other end of the optical fiber array is connected to an external light source to provide light for the first Optical signal input of the photonic integrated circuit chip 102.
  • the on-chip optical interconnection structure and the manufacturing method thereof provided by embodiments of the present invention are intended to cover two adjacent first photonic integrated circuit chips by providing a semiconductor wafer having a plurality of first photonic integrated circuit chips.
  • the second photonic integrated circuit chip on part of the first surface of the photonic integrated circuit chip uses a plurality of second optical waveguides of the second photonic integrated circuit chip to connect two adjacent first photonic integrated circuit chips.
  • the optical input and output ports can be flexibly set in the wafer-level on-chip optical interconnection structure. Any location, and the number of first photonic integrated circuit chips in the same optical communication can be selected as needed, with flexible design.
  • the plurality of first optical waveguides and the plurality of second optical waveguides perform multi-channel transmission in parallel, which can significantly increase the optical communication capacity transmitted in each of the first photonic integrated circuit chips.

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Abstract

一种片上光互连结构及其制作方法，旨在通过在具有多个第一光子集成电路芯片（102）的半导体晶片（100）上设置有覆盖在相邻两个第一光子集成电路芯片（102）的部分第一表面（102a）的第二光子集成电路芯片（200），利用第二光子集成电路芯片（200）的多个第二光波导（210），将相邻的两个第一光子集成电路芯片（102）之间进行光互连，从而实现晶圆级无间断的片上光互连，以提高片上光网络的性能和应用价值。突破了单颗第一光子集成电路芯片（102）尺寸的上限，并且可以根据需要选择在同一光通信中的第一光子集成电路芯片（102）的数量，设计灵活。

Description

片上光互连结构及其制作方法
本申请要求于2022年07月25日提交中国专利局、申请号为202210878889.8、发明名称为“片上光互连结构及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及光互连技术领域，更为具体而言，涉及片上光互连结构及其制作方法。
背景技术
随着带宽的数据处理和通信，数据中心和高性能计算机的不断增长的需求必须不断提高自己的能力和表现。该增强数据处理性能应该伴随着功耗的减少以及较低的制造成本。硅光子可能是最有前途的技术，例如，可以在通过波分复用(WDM)使得多个信道并行，从而实现高带宽链路。
目前现有的光互连技术，通常指的是芯片上的互连，即基于单颗芯片内的光互连；对于光互连技术而言，芯片的尺寸越大，其优势越明显。但是，由于受晶圆代工工厂的限制，芯片尺寸(包括硅光子芯片)设有上限，暂无成熟工艺或者成熟代工厂提供单颗芯片尺寸不受限制的硅光子芯片，故导致该光互连的技术应用受到限制，无法充分发挥该技术的潜能。
技术解决方案
本申请实施例提供了片上光互连结构及其制作方法，以解决现有片上光互连技术受限于单颗光子集成电路芯片的尺寸限制的问题。
在一个示例性的实施方式中，提供一种片上光互连结构，包括：
半导体晶片，所述半导体晶片包括多个第一光子集成电路芯片，每个所述第一光子集成电路芯片具有相对的第一表面和第二表面，其中，每个所述第一光子集成电路芯片包括多个第一光波导；
多个第二光子集成电路芯片，每个所述第二光子集成电路芯片包括多个第二光波导，每个所述第二光子集成电路芯片固定于相邻的两个所述第一光子集成电路芯片的部分所述第一表面上并覆盖相邻的两个所述第一光子集成电路 芯片在所述半导体晶片上对应的区域边界；
其中，相邻的两个所述第一光子集成电路芯片通过固定于该相邻的两个所述第一光子集成电路芯片的部分所述第一表面上的所述第二光子集成电路芯片进行光互连。
在一些实施方式中，所述多个第二光子集成电路芯片是无源光子集成电路芯片。
在一些实施方式中，针对进行光互连的相邻的两个所述第一光子集成电路芯片，该相邻的两个所述第一光子集成电路芯片的所述多个第一光波导与固定于该相邻的两个所述第一光子集成电路芯片的部分所述第一表面上的所述第二光子集成电路芯片的所述多个第二光波导一一对应，以将该相邻的两个所述第一光子集成电路芯片进行光互连。
在一些实施方式中，在所述半导体晶片的厚度方向上，该相邻的两个所述第一光子集成电路芯片的所述多个第一光波导的端部的投影与固定于该相邻的两个所述第一光子集成电路芯片的部分所述第一表面上的每个所述第二光子集成电路芯片的所述多个第二光波导的端部的投影以一一对应的方式交叠。在一些实施方式中，针对进行光互连的相邻的两个所述第一光子集成电路芯片，在该相邻的两个所述第一光子集成电路芯片的所述第一表面上靠近该相邻的两个所述第一光子集成电路芯片在所述半导体晶片上对应的区域边界各设置有至少一个光束重定向元件，其中，每个所述光束重定向元件用于改变光束的方向以进入每个所述第一光波导和/或每个所述第二光波导中；针对固定于该相邻的两个所述第一光子集成电路芯片的部分所述第一表面上的所述第二光子集成电路芯片，在平行该第二光子集成电路芯片所在平面的方向上，在该第二光子集成电路芯片的所述多个第二光波导的两侧均设置有一组光栅耦合器，每组所述光栅耦合器分别与该相邻的两个所述第一光子集成电路芯片的所述多个第一光波导一一对应并且用于光耦合，其中，每组所述光栅耦合器包括至少一个光栅耦合器元件；其中，相邻的两个所述第一光子集成电路芯片通过所述光束重定向元件、两组光栅耦合器以及所述多个第二光波导进行光互连。
在一些实施方式中，每个所述第一光子集成电路芯片包括多个金属连接柱，并且所述金属连接柱的一侧表面从每个所述第一光子集成电路芯片的所述 第一表面露出。
在一些实施方式中，所述片上光互连结构还包括固定于至少一个所述第一光子集成电路芯片的所述第一表面上的至少一个电子集成电路芯片。
在一些实施方式中，在所述半导体晶片的所述第一表面上设置有多个光耦合区，每个所述光耦合区内设置有光耦合接口。
在一些实施方式中，所述片上光互连结构还包括多个伪芯片，所述多个伪芯片一一对应固定于所述半导体晶片的所述第一表面上的所述多个光耦合区上，其中，每个所述伪芯片具有上下开口的空腔，所述空腔的开口面对所述光耦合接口并覆盖所述光耦合接口。
在一些实施方式中，所述片上光互连结构还包括塑封层，所述塑封层覆盖在所述半导体晶片的所述第一表面上，并且包覆所述多个伪芯片的侧面、至少一个电子集成电路芯片的侧面以及所述多个第二光子集成电路芯片。
在一些实施方式中，所述片上光互连结构还包括多个导光结构，所述多个导光结构与所述多个伪芯片一一对应，其中，每个所述导光结构穿过每个所述伪芯片的所述空腔，以将光信号耦合至对应的所述光耦合接口。
在一个示例性的实施方式中，提供了一种片上光互连结构的制作方法，所述方法包括：
提供半导体晶片，所述半导体晶片包括多个第一光子集成电路芯片，每个所述第一光子集成电路芯片具有相对的第一表面和第二表面，其中，每个所述第一光子集成电路芯片包括多个第一光波导；
提供多个第二光子集成电路芯片，每个所述第二光子集成电路芯片包括多个第二光波导，将每个所述第二光子集成电路芯片固定在相邻的两个所述第一光子集成电路芯片的部分所述第一表面上并覆盖相邻的两个所述第一光子集成电路芯片在所述半导体晶片上对应的区域边界；
其中，针对进行光互连的相邻的两个所述第一光子集成电路芯片，将每个所述第二光子集成电路芯片的所述多个第二光波导与该相邻的两个所述第一光子集成电路芯片的所述多个第一光波导进行一一对准，以将该相邻的两个所述光子集成电路芯片进行光互连。
在一些实施方式中，所述方法还包括：将每个所述第二光子集成电路芯片 以背面贴装的方式固定在相邻的两个所述第一光子集成电路芯片的部分所述第一表面上并覆盖相邻的两个所述第一光子集成电路芯片在所述半导体晶片上对应的区域边界；或者
去除每个所述第二光子集成电路芯片的底部半导体层，将已去除底部半导体层的每个所述第二光子集成电路芯片以正面贴装的方式固定在相邻的两个所述第一光子集成电路芯片的部分所述第一表面上并覆盖相邻的两个所述第一光子集成电路芯片在所述半导体晶片上对应的区域边界。
在一些实施方式中，所述方法还包括：在所述半导体晶片的厚度方向上，将该相邻的两个所述第一光子集成电路芯片的所述多个第一光波导的端部的投影与固定于该相邻的两个所述第一光子集成电路芯片的部分所述第一表面上的每个所述第二光子集成电路芯片的所述多个第二光波导的端部的投影以一一对应的方式交叠，以通过绝热耦合的方式将相邻的两个所述第一光子集成电路芯片进行光互连。
在一些实施方式中，所述方法还包括：在该相邻的两个所述第一光子集成电路芯片的所述第一表面上靠近该相邻的两个所述第一光子集成电路芯片在所述半导体晶片上对应的区域边界各放置有至少一个光束重定向元件；其中，每个所述光束重定向元件用于改变光束的方向以进入每个所述第一光波导和/或每个所述第二光波导中；以及针对固定于该相邻的两个所述第一光子集成电路芯片的部分所述第一表面上的所述第二光子集成电路芯片，在平行于该第二光子集成电路芯片所在平面的方向上，在该第二光子集成电路芯片的所述多个第二光波导的两侧均形成有一组光栅耦合器，每组所述光栅耦合器分别与该相邻的两个所述光子集成电路芯片的所述多个第一光波导一一对应并且用于光耦合，其中，每组所述光栅耦合器包括至少一个光栅耦合器元件；其中，相邻的两个所述第一光子集成电路芯片通过所述光束重定向元件、两组光栅耦合器以及所述多个第二光波导进行光互连。
在一些实施方式中，所述方法还包括：在每个所述第一光子集成电路芯片内制作多个金属连接柱，并将所述金属连接柱的一侧表面从每个所述第一光子集成电路芯片的所述第一表面露出。
在一些实施方式中，所述方法还包括：在将每个所述第二光子集成电路芯 片固定在相邻的两个所述第一光子集成电路芯片的部分所述第一表面上并覆盖相邻的两个所述第一光子集成电路芯片在所述半导体晶片上对应的区域边界之后，针对至少一个所述第一光子集成电路芯片，提供与该第一光子集成电路芯片对应的至少一个电子集成电路芯片，并将所述至少一个电子集成电路芯片固定在该第一光子集成电路芯片的所述第一表面的对应区域。
在一些实施方式中，所述方法还包括：在所述半导体晶片的所述第一表面上设置多个光耦合区，在每个所述光耦合区内设置光耦合接口；提供多个伪芯片，每个所述伪芯片具有单面开口的空腔，将所述多个伪芯片一一对应固定在所述多个光耦合区上，以使每个所述伪芯片的所述空腔的开口面对所述光耦合接口并覆盖所述光耦合接口。
在一些实施方式中，所述方法还包括：在将所述多个伪芯片一一对应固定在所述多个光耦合区上之后，在所述半导体晶片的所述第一表面上制作塑封层，所述塑封层包覆所述多个伪芯片的侧面、所述至少一个电子集成电路芯片的侧面以及所述多个第二光子集成电路芯片。
在一些实施方式中，所述方法还包括：在所述塑封层制作完成之后，在所述半导体晶片远离所述多个第二光子集成电路芯片的一侧对所述半导体晶片的本体进行减薄处理，以露出所述金属连接柱远离所述多个第二光子集成电路芯片一侧的表面。
在一些实施方式中，在露出所述金属连接柱远离所述多个第二光子集成电路芯片一侧的表面之后，在所述半导体晶片的所述第二表面形成与每个所述金属连接柱一一对应电连接的布线层以及导电凸块。
在一些实施方式中，所述方法还包括：减薄所述塑封层、所述多个伪芯片，使得所述多个伪芯片的空腔上下贯通以及所述多个电子集成电路芯片的远离所述半导体晶片的一侧表面露出。
在一些实施方式中，所述方法还包括：将导光结构或者激光器芯片通过每个所述伪芯片的开口安装至对应的所述光耦合接口上。
本发明提供的片上光互连结构及其制作方法，通过在具有多个第一光子集成电路芯片的所述半导体晶片上设置有覆盖在相邻两个第一光子集成电路芯片的部分所述第一表面的第二光子集成电路芯片，利用第二光子集成电路芯片 的多个第二光波导，将相邻的两个所述第一光子集成电路芯片之间进行光互连，从而实现晶圆级无间断的片上光互连，以提高片上光网络的性能和应用价值。突破了单颗第一光子集成电路芯片尺寸的上限，并且可以根据需要选择在同一光通信中的第一光子集成电路芯片的数量，设计灵活。
本发明实施方式的各个方面、特征、优点等将在下文结合附图进行具体描述。根据以下结合附图的具体描述，本发明的上述方面、特征、优点等将会变得更加清楚。
本发明实施方式的各个方面、特征、优点等将在下文结合附图进行具体描述。根据以下结合附图的具体描述，本发明的上述方面、特征、优点等将会变得更加清楚。
参照后文的说明和附图，详细公开了本发明的特定实施例，指明了本发明的原理可以被采用的方式。应该理解，本发明的实施例在范围上并不因而受到限制。在所附权利要求的精神和条款的范围内，本发明的实施例包括许多改变、修改和等同。
针对一种实施例描述和/或示出的特征可以以相同或类似的方式在一个或更多个其它实施例中使用，与其它实施例中的特征相组合，或替代其它实施例中的特征。
应该强调，术语“包括/包含”在本文使用时指特征、整件、步骤或组件的存在，但并不排除一个或更多个其它特征、整件、步骤或组件的存在或附加。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A是根据本发明实施例提供的一种片上光互连结构的俯视结构示意图。
图1B是根据本发明实施例提供的一种片上光互连结构的侧视结构示意图。
图2是根据图1A实施例中相邻的两个所述第一光子集成电路芯片的多个第一光波导通过所述第二光子集成电路芯片的所述多个第二光波导进行光互连的第一种实施方式的侧视结构示意图。
图3是根据图1A实施例中相邻的两个所述第一光子集成电路芯片的多个第一光波导通过所述第二光子集成电路芯片的所述多个第二光波导进行光互连的第二种实施方式的侧视结构示意图。
图4A是根据本发明实施例提供的又一种片上光互连结构的俯视结构示意图。
图4B是根据本发明实施例提供的又一种片上光互连结构的侧视结构示意图。
图5是根据本发明实施例提供的另一种片上光互连结构的侧视结构示意图。
图6是根据本发明实施例提供的片上光互连结构的制作方法的流程图。
图7A-图7I是根据本发明实施例提供的片上光互连结构的制作方法的制作工序示意图。
本发明的实施方式
为了便于理解本发明技术方案的各个方面、特征以及优点，下面结合附图对本发明进行具体描述。应当理解，下述的各种实施方式只用于举例说明，而非用于限制本发明的保护范围。
在本公开的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。本文中芯片的含义可以包括裸芯片。在涉及方法步骤时，本文图示的先后顺序代表了一种示例性的方案，但不表示对先后顺序的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
针对现有片上光互连技术受限于单颗光子集成电路芯片的尺寸限制的问 题，本发明实施例提出了一种片上光互连结构及其制作方法，旨在实现晶圆级范围内无间断的片上光互连。
图1A是根据本发明实施例提供的一种片上光互连结构的俯视结构示意图，图1B是根据本发明实施例提供的一种片上光互连结构的侧视结构示意图。
如图1A-图1B所示，所述片上光互连结构包括：半导体晶片100，所述半导体晶片100包括多个第一光子集成电路芯片102，每个所述第一光子集成电路芯片102具有相对的第一表面102a和第二表面102b，其中，每个所述第一光子集成电路芯片102包括多个第一光波导110；多个第二光子集成电路芯片200，每个所述第二光子集成电路芯片200包括多个第二光波导210，每个所述第二光子集成电路芯片200固定于相邻的两个所述第一光子集成电路芯片102的部分所述第一表面102a上并覆盖相邻的两个所述第一光子集成电路芯片102在所述半导体晶片100上对应的区域边界；其中，相邻的两个所述第一光子集成电路芯片102通过固定于该相邻的两个所述第一光子集成电路芯片102的部分所述第一表面102a上的所述第二光子集成电路芯片200进行光互连。
需要说明的是，在本发明实施例中，所述半导体晶片100例如是一个母板光子晶圆，在该母板光子晶圆上制备有多个第一光子集成电路芯片102。其中，第一光子集成电路芯片102是用光子为信息载体进行信息的处理与传送，其可以是基于硅的光子集成电路芯片。一般地，在该母板光子晶圆的制造过程中，可在相邻两个第一光子集成电路芯片102之间设置有切割道，该切割道代表母板光子晶圆上预留有用于切割的空间，以便于后续可以根据同一光通信中所需承载光通信容量大小进行芯片之间的分离以选择用于光互连的合适数量的第一光子集成电路芯片102。示例性地，在本实施方式中，相邻的两个所述第一光子集成电路芯片102在所述半导体晶片100上对应的区域边界可以为相邻两个第一光子集成电路芯片102之间设置的切割道，并且，上方固定有所述第二光子集成电路芯片200的相邻两个所述第一光子集成电路芯片102之间的切割道不进行芯片切割分离成单独芯片的步骤，该相邻两个所述第一光子集成电路芯片102是连接在一起的芯片，以增强所述第一光子集成电路芯片102和所述第二光子集成电路芯片200的光路对准度，提高光耦合效率，同时节约了工艺成 本。
本发明实施例提供的技术方案，旨在通过在具有多个第一光子集成电路芯片的所述半导体晶片上设置有覆盖在相邻两个第一光子集成电路芯片的部分所述第一表面的第二光子集成电路芯片，利用第二光子集成电路芯片的多个第二光波导，将相邻的两个所述第一光子集成电路芯片之间进行光互连，从而实现晶圆级无间断的片上光互连，以提高片上光网络(Optical Network-on-Chip，ONOC)的性能和应用价值。突破了单颗第一光子集成电路芯片尺寸的上限，并且可以根据需要选择在同一光通信中的第一光子集成电路芯片的数量，设计灵活。
在示例性的实施例中，所述多个第一光波导110和所述多个第二光波导210以并行的方式进行多通道传输，能够显著增加各个所述第一光子集成电路芯片102中传输的光通信容量。
在一些实施例中，所述多个第二光子集成电路芯片200是无源光子集成电路芯片。也即，每个所述第二光子集成电路芯片200在正常工作时不需要另外给它提供电源。使用每个所述第二光子集成电路芯片200内设置的多个第二光波导210进行光信号传输，而且，每个所述第二光子集成电路芯片200在正常工作时也不会产生任何谐波。
示例性地，每个所述第二光子集成电路芯片200的多个第二光波导210基于半导体层上的第一区域图案化形成，在其中一实施例中，所述半导体层例如是SOI(Silicon on Insulator，绝缘体上硅)结构的顶层硅，在顶层硅上通过湿法刻蚀或者激光烧蚀的方式形成多个第二光波导210。当然，在其他实施例中，也可以采用其他方式在所述第二光子集成电路芯片200上形成多个第二光波导210。本发明实施例在此不做限制。
图2是根据图1A实施例中相邻的两个所述第一光子集成电路芯片的多个第一光波导通过所述第二光子集成电路芯片的所述多个第二光波导进行光互连的第一种实施方式的侧视结构示意图。
在一些实施例中，如图2所示，针对进行光互连的相邻的两个所述第一光子集成电路芯片102，该相邻的两个所述第一光子集成电路芯片102的所述多个第一光波导110与固定于该相邻的两个所述第一光子集成电路芯片102的部 分所述第一表面102a上的所述第二光子集成电路芯片200的所述多个第二光波导210一一对应，以将该相邻的两个所述第一光子集成电路芯片102进行光互连。
在一些实施例中，在所述半导体晶片100的厚度方向上，该相邻的两个所述第一光子集成电路芯片102的所述多个第一光波导110的端部的投影与固定于该相邻的两个所述第一光子集成电路芯片102的部分所述第一表面102a上的每个所述第二光子集成电路芯片200的所述多个第一光波导110的端部与第二光波导210的端部的投影以一一对应的方式交叠。该相邻的两个所述第一光子集成电路芯片102的所述多个第一光波导110的端部通过绝热耦合的方式实现相邻的两个所述第一光子集成电路芯片102之间的光互连。
图3是根据图1A实施例中相邻的两个所述第一光子集成电路芯片的多个第一光波导通过所述第二光子集成电路芯片的所述多个第二光波导进行光互连的第二种实施方式的侧视结构示意图。
示例性地，如图3所示，针对进行光互连的相邻的两个所述第一光子集成电路芯片102，在该相邻的两个所述第一光子集成电路芯片102的所述第一表面102a上靠近该相邻的两个所述第一光子集成电路芯片102在所述半导体晶片100上对应的区域边界各设置有至少一个光束重定向元件810，其中，每个所述光束重定向元件810用于改变光束的方向以进入每个所述第一光波导110和/或每个所述第二光波导210中；针对固定于该相邻的两个所述第一光子集成电路芯片102的部分所述第一表面102a上的所述第二光子集成电路芯片200，在平行该第二光子集成电路芯片200所在平面的方向上，在该第二光子集成电路芯片200的所述多个第二光波导210的两侧均设置有一组光栅耦合器213，每组所述光栅耦合器213分别与该相邻的两个所述第一光子集成电路芯片102的所述多个第一光波导110一一对应并且用于光耦合，其中，每组所述光栅耦合器213包括至少一个光栅耦合器元件；其中，相邻的两个所述第一光子集成电路芯片102通过所述光束重定向元件810、两组光栅耦合器213以及所述多个第二光波导210进行光互连。
示例性地，在本发明实施例中，所述光束重定向元件810可以是棱镜组件，该棱镜组件用于改变光束的传输方向以进入每个所述第一光波导110和/或每 个所述第二光波导210中，具体地，该棱镜组件为三棱镜，该三棱镜具有两个直角边和一个斜边，该相邻的两个所述第一光子集成电路芯片102的所述多个第一光波导110的端部均正对棱镜组件的斜边，以将一个第一光子集成电路芯片102的所述多个第一光波导110传输的光束的传播方向改变90度后经由一组所述光栅耦合器213传输到第二光子集成电路芯片200的所述多个第二光波导中210中，并由另一组所述光栅耦合器213传输到另一个第一光子集成电路芯片102中，从而实现相邻的两个所述第一光子集成电路芯片102的光互连。
在一些实施例中，如图3所示，可在每个所述第一光子集成电路芯片102的第一表面102a上开设有凹槽，并将所述光束重定向元件810容置于该凹槽中，一方面起到固定及限位的作用，另一方面也能够调节该相邻的两个所述第一光子集成电路芯片102的所述多个第一光波导110的光束恰好入射/出射至该光束重定向元件810的中部，以避免发生不必要的光损耗。
在示例性的实施例中，如图1B所示，每个所述第一光子集成电路芯片102包括多个金属连接柱1022，并且所述金属连接柱1022的一侧表面从每个所述第一光子集成电路芯片102的所述第一表面102a露出。
图4A是根据本发明实施例提供的又一种片上光互连结构的俯视结构示意图，图4B是根据本发明实施例提供的又一种片上光互连结构的侧视结构示意图。
如图4A和图4B所示，所述片上光互连结构还包括固定于至少一个所述第一光子集成电路芯片102的所述第一表面102a上的至少一个电子集成电路芯片300。其中，每个所述电子集成电路芯片300是用电子为信息载体进行信息的处理与数据的传送，例如基于硅的电子集成电路芯片、基于锗的电子集成电路芯片或者化合物半导体电子集成电路芯片，通过将至少一个所述第一光子集成电路芯片102和所述至少一个电子集成电路芯片300进行堆叠可实现光子集成电路芯片和电子集成电路芯片的集成。
示例性地，至少一个电子集成电路芯片300例如可以采用焊接或者其他方式进行固定于至少一个所述第一光子集成电路芯片102的所述第一表面102a上的非光耦合区域及非所述第二光子集成电路芯片200所覆盖的区域。本发明实施例中，所述至少一个电子集成电路芯片300采用倒装焊接的方式焊接到所 述至少一个第一光子集成电路芯片102的所述第一表面102a上。可选地，在每个所述电子集成电路芯片300与所述第一表面102a之间的缝隙处填充底胶(under fill)以进一步地加固每个所述电子集成电路芯片300。
本发明实施例中示意了在所述第一光子集成电路芯片102的第一表面102a的上方形成一个所述电子集成电路芯片300，在实际使用中，可以是多于一个的所述电子集成电路芯片300，例如2个、3个、4个或者更多，可以根据实际需要灵活选择。
在一些实施例中，在所述半导体晶片100的所述第一表面102a上设置有多个光耦合区1024，每个所述光耦合区1024内设置有光耦合接口104。一部分的光耦合接口104使得外部光源提供的光可以通过光纤阵列(Fiber Array，FA)等导光结构600输入到光耦合接口104中，进而使光信号在每个所述第一光子集成电路芯片102的多个第一光波导110中进行传输。例如通过与光耦合接口104内的光栅耦合器耦合进第一光子集成电路芯片102。另一部分光耦合接口104使得经过多个所述第一光子集成电路芯片102传输/处理后的光信号通过光纤阵列等导光结构600传输到其衬底上的集成电路芯片结构进行后续处理。在本实施方案中，光耦合接口104的位置可以根据实际需要设置，布局更加灵活。需要说明的是，在其他实施例中，也可以在光耦合接口104内相应的设置其他用于传输光信号的光互连接口或者器件。
图5是根据本发明实施例提供的另一种片上光互连结构的侧视结构示意图。
如图5所示，所述片上光互连结构还包括多个伪芯片400，所述多个伪芯片400一一对应固定于所述半导体晶片100的所述第一表面102a上的所述多个光耦合区1024上，其中，每个所述伪芯片400具有上下开口的空腔，所述空腔的开口面对所述光耦合接口104并覆盖所述光耦合接口104。
继续参考图5所示，所述片上光互连结构还包括塑封层106，所述塑封层106覆盖在所述半导体晶片100的所述第一表面102a上，并且包覆所述多个伪芯片400的侧面、所述至少一个电子集成电路芯片300的侧面以及所述多个第二光子集成电路芯片200。
在一些实施例中，所述片上光互连结构还包括多个导光结构600，所述多 个导光结构600与所述多个伪芯片400一一对应，其中，每个所述导光结构600穿过每个所述伪芯片400的所述空腔，以将光信号耦合至对应的所述光耦合接口104。
根据本发明的又一方面，还提供了一种片上光互连结构的制作方法。
图6是根据本发明实施例提供的片上光互连结构的制作方法的流程图。所述片上光互连结构的制作方法包括：
S101，提供半导体晶片，所述半导体晶片包括多个第一光子集成电路芯片，每个所述第一光子集成电路芯片具有相对的第一表面和第二表面，其中，每个所述第一光子集成电路芯片包括多个第一光波导；
S102，提供多个第二光子集成电路芯片，每个所述第二光子集成电路芯片包括多个第二光波导，将每个所述第二光子集成电路芯片固定在相邻的两个所述第一光子集成电路芯片的部分所述第一表面上并覆盖相邻的两个所述第一光子集成电路芯片在所述半导体晶片上对应的区域边界；
其中，针对进行光互连的相邻的两个所述第一光子集成电路芯片，将每个所述第二光子集成电路芯片的所述多个第二光波导与该相邻的两个所述第一光子集成电路芯片的所述多个第一光波导进行一一对准，以将该相邻的两个所述光子集成电路芯片进行光互连。
图7A-图7I是根据本发明实施例提供的片上光互连结构的制作方法的制作工序示意图。
以下将结合图7A-图7I以及图1A、图1B、图2、图3对本发明实施例进行详细说明。
示例性地，请参阅图7A所示，首先提供半导体晶片100，所述半导体晶片100包括多个第一光子集成电路芯片102，每个所述第一光子集成电路芯片102具有相对的第一表面102a和第二表面102b，其中，每个所述第一光子集成电路芯片102包括多个第一光波导110。
需要说明的是，在本发明实施例中，所述半导体晶片100例如是一个母板光子晶圆，该母板光子晶圆上具有多个第一光子集成电路芯片102，在相邻两个第一光子集成电路芯片102之间可以具有切割道，该切割道代表母板光子晶圆上预留有用于切割的空间，以便于后续可以根据同一光通信中所需承载光通 信容量大小进行芯片之间的分离以选择用于光互连的合适数量的第一光子集成电路芯片102。
请参阅图7B所示，提供多个第二光子集成电路芯片200，每个所述第二光子集成电路芯片200包括多个第二光波导210，将每个所述第二光子集成电路芯片200固定在相邻的两个所述第一光子集成电路芯片102的部分所述第一表面102a上并覆盖相邻的两个所述第一光子集成电路芯片102在所述半导体晶片上100对应的区域边界；其中，相邻的两个所述第一光子集成电路芯片102在所述半导体晶片上100对应的区域边界可以是相邻两个第一光子集成电路芯片102之间的切割道；其中，针对进行光互连的相邻的两个所述第一光子集成电路芯片102，将每个所述第二光子集成电路芯片200的所述多个第二光波导210与该相邻的两个所述第一光子集成电路芯片102的所述多个第一光波导110进行一一对准，以将该相邻的两个所述光子集成电路芯片102进行光互连。
在本发明实施例中，所述多个第二光子集成电路芯片200是无源光子集成电路芯片。每个所述第二光子集成电路芯片200在正常工作时不需要另外给它提供电源。使用每个所述第二光子集成电路芯片200内设置的多个第二光波导210进行光信号传输，而且，每个所述第二光子集成电路芯片200在正常工作时也不会产生任何谐波。
示例性地，每个所述第二光子集成电路芯片200的多个第二光波导210基于半导体层上的第一区域图案化形成，在其中一实施例中，所述半导体层例如是SOI(Silicon on Insulator，绝缘体上硅)结构的顶层硅，在顶层硅上通过湿法刻蚀或者激光烧蚀的方式形成多个第二光波导210。当然，在其他实施例中，也可以采用其他方式在所述第二光子集成电路芯片200上形成多个第二光波导210。本发明实施例在此不做限制。
为了尽可能地能够减少每个所述第二光子集成电路芯片200的多个第二光波导210与位于其下方的相邻两个第一光子集成电路芯片102的多个第一光波导110的耦合距离，可选地，在本发明的一些实施方式中，将每个所述第二光子集成电路芯片200以背面贴装的方式固定在相邻的两个所述第一光子集成电路芯片102的部分所述第一表面102a上并覆盖相邻的两个所述第一光子 集成电路芯片102在所述半导体晶片100上对应的区域边界。
可选地，在本发明的另一些实施方式中，也可以通过去除每个所述第二光子集成电路芯片200的底部半导体层，将已去除底部半导体层的每个所述第二光子集成电路芯片200以正面贴装的方式固定在相邻的两个所述第一光子集成电路芯片102的部分所述第一表面102a上并覆盖相邻的两个所述第一光子集成电路芯片102在所述半导体晶片100上对应的区域边界。
进一步地，结合图2所示，在所述半导体晶片100的厚度方向上，将该相邻的两个所述第一光子集成电路芯片102的所述多个第一光波导110的端部的投影与固定于该相邻的两个所述第一光子集成电路芯片102的部分所述第一表面102a上的每个所述第二光子集成电路芯片200的所述多个第二光波导210的端部的投影以一一对应的方式交叠，以通过绝热耦合的方式实现相邻的两个所述第一光子集成电路芯片102之间的光互连。
进一步地，结合图3所示，在该相邻的两个所述第一光子集成电路芯片102的所述第一表面102a上靠近该相邻的两个所述第一光子集成电路芯片102在所述半导体晶片100上对应的区域边界各放置有至少一个光束重定向元件810；其中，每个所述光束重定向元件810用于改变光束的方向以进入每个所述第一光波导110和/或每个所述第二光波导210中；以及针对固定于该相邻的两个所述第一光子集成电路芯片102的部分所述第一表面102a上的所述第二光子集成电路芯片200，在平行于该第二光子集成电路芯片200所在平面的方向上，在该第二光子集成电路芯片200的所述多个第二光波导210的两侧均形成有一组光栅耦合器213，每组所述光栅耦合器213分别与该相邻的两个所述光子集成电路芯片102的所述多个第一光波导110一一对应并且用于光耦合，其中，每组所述光栅耦合器213包括至少一个光栅耦合器元件；其中，相邻的两个所述第一光子集成电路芯片102通过所述光束重定向元件810、两组光栅耦合器213以及所述多个第二光波导210进行光互连。
示例性地，所述光栅耦合器213例如可以是具有多个通道的回环光栅耦合器。
进一步地，在每个所述第一光子集成电路芯片102内制作多个金属连接柱1022，并将所述金属连接柱1022的一侧表面从每个所述第一光子集成电路芯 片102的所述第一表面102a露出。
具体地，当所述第一光子集成电路芯片102为基于硅的光子集成电路芯片时，在所述第一光子集成电路芯片102中的衬底中制作多个导电通孔，导电通孔可以作为导电通道的一部分，该导电通孔在制造时可采用“硅通孔”(Through Silicon Via，TSV)技术，TSV是一项高密度封装技术，正在逐渐取代目前工艺比较成熟的引线键合技术，被认为是第四代封装技术。TSV技术通过铜、钨、多晶硅等导电物质的填充，实现硅通孔的垂直电气互连。硅通孔技术可以通过垂直互连减小互联长度，减小信号延迟，降低电容/电感，实现芯片间的低功耗、高速通信，增加宽带和实现器件集成的小型化。TSV工艺可以包括深硅刻蚀形成微孔或盲孔、绝缘层/阻挡层/种子层的沉积、深孔填充、化学机械抛光、减薄、以及再分布引线制备等工艺技术，在所述第一光子集成电路芯片102中形成导电通孔的工艺方法包括但不限于激光刻蚀、深反应离子刻蚀等，在形成导电通孔后再采用例如深孔填充等工艺进行导电材料(例如金属)的填充。本发明在此不再赘述。
进一步地，如图7B-图7C所示，在将每个所述第二光子集成电路芯片200固定在相邻的两个所述第一光子集成电路芯片102的部分所述第一表面102a上并覆盖相邻的两个所述第一光子集成电路芯片102在所述半导体晶片100上对应的区域边界之后，针对至少一个所述第一光子集成电路芯片102，提供与该第一光子集成电路芯片102对应的至少一个电子集成电路芯片300，并将所述至少一个电子集成电路芯片300固定在该第一光子集成电路芯片102的所述第一表面102a的对应区域。
进一步地，如图7D所示，在所述半导体晶片100上所述第一表面102a上制作有多个光耦合区1024，在每个所述光耦合区1024内设置光耦合接口104。为了形成对每个所述光耦合区1024内的光耦合接口104的保护，提供多个伪芯片400，每个所述伪芯片400具有单面开口的空腔，将所述多个伪芯片400一一对应固定在所述多个光耦合区1024上，以使每个所述伪芯片400的所述空腔的开口面对所述光耦合接口104并覆盖所述光耦合接口104。所述伪芯片400及其空腔可以对所述光耦合接口104形成封闭的保护空间，以避免后续在对所述片上光互连结构进行塑封的过程中，塑封层中的有机物材料接触光 耦合区后造成有机物残留，从而严重影响到所述光耦合接口104的耦合效率，导致其光损耗严重，进而影响所述第一光子集成电路芯片102的正常运行。
需要说明的是，伪芯片400是指其上不集成或者不具有任何光子器件和电子器件的晶片，例如裸硅片。
进一步地，如图7E所示，在将所述多个伪芯片400一一对应固定在所述多个光耦合区1024上之后，在所述半导体晶片100的所述第一表面102a上制作塑封层106，所述塑封层106包覆所述多个伪芯片400的侧面、所述至少一个电子集成电路芯片300的侧面以及所述多个第二光子集成电路芯片200。具体地，所述塑封层106的注塑材料例如可以是环氧树脂，其在熔融状态下覆盖所述半导体晶片100的所述第一表面102a，并在固化后形成塑封层106，使得所述多个伪芯片400、所述至少一个电子集成电路芯片300以及所述多个第二光子集成电路芯片200均被牢固地固定在所述半导体晶片100的相应位置上，从而能够形成稳定的封装结构。
如图7F所示，在所述塑封层106制作完成之后，在所述半导体晶片100远离所述多个第二光子集成电路芯片200的一侧对所述半导体晶片100的本体进行减薄处理，以露出所述金属连接柱1022远离所述多个第二光子集成电路芯片200一侧的表面。
随后，在露出所述金属连接柱1022远离所述多个第二光子集成电路芯片200一侧的表面之后，在所述半导体晶片100的所述第二表面102b形成与每个所述金属连接柱1022一一对应电连接的布线层以及导电凸块1023，以实现所述金属连接柱1022与外部电连接点进行电连接。
如图7G所示，减薄所述塑封层106、所述多个伪芯片400，使得所述多个伪芯片400的空腔上下贯通以及所述多个电子集成电路芯片300的远离所述半导体晶片100的一侧表面露出。
如图7H所示，在将所述多个伪芯片400的空腔上下贯通以及所述多个电子集成电路芯片300的远离所述半导体晶片100的一侧表面露出之后，将所述半导体晶片100的第二表面102b固定到封装基板500上。
最后，如图7I所示，将导光结构600或者激光器芯片通过每个所述伪芯片400的开口安装至对应的所述光耦合接口104上。示例性地，所示导光结构 600为光纤阵列，光纤阵列穿过每个所述伪芯片400的空腔耦合至所述光耦合接口104，根据一些实施例，可以使用光耦合胶将光纤阵列倾斜地耦合到光耦合接口104。例如，可以相对于所述半导体晶片100的第一表面102a以45°角的方式将光纤阵列耦合至光耦合器的光耦合接口，光纤阵列的另一端连接外部光源，以提供对所述第一光子集成电路芯片102的光信号输入。
由上述内容可知，本发明实施例提供的片上光互连结构及其制作方法，旨在通过在具有多个第一光子集成电路芯片的所述半导体晶片上设置有覆盖在相邻两个第一光子集成电路芯片的部分所述第一表面的第二光子集成电路芯片，利用第二光子集成电路芯片的多个第二光波导，将相邻的两个所述第一光子集成电路芯片之间进行光互连，从而实现晶圆级无间断的片上光互连，以提高片上光网络(Optical Network-on-Chip，ONOC)的性能和应用价值。不仅突破单颗第一光子集成电路芯片尺寸的上限，而且在该晶圆级的片上光互连结构中，光输入端和输出端的端口可以灵活设置在该晶圆级的片上光互连结构的任何位置，并且可以根据需要选择在同一光通信中的第一光子集成电路芯片的数量，设计灵活。
进一步地，所述多个第一光波导和所述多个第二光波导以并行的方式进行多通道传输，能够显著增加每个所述第一光子集成电路芯片中传输的光通信容量。
上文仅为本发明的较佳实施例而已，并非用来限定本发明实施的范围，凡依本发明权利要求范围所述的形状、构造、特征及精神所为的均等变化与修饰，均应包括于本发明的权利要求范围内。

Claims (23)

  1. 一种片上光互连结构，其特征在于，包括：
    半导体晶片，所述半导体晶片包括多个第一光子集成电路芯片，每个所述第一光子集成电路芯片具有相对的第一表面和第二表面，其中，每个所述第一光子集成电路芯片包括多个第一光波导；
    多个第二光子集成电路芯片，每个所述第二光子集成电路芯片包括多个第二光波导，每个所述第二光子集成电路芯片固定于相邻的两个所述第一光子集成电路芯片的部分所述第一表面上并覆盖相邻的两个所述第一光子集成电路芯片在所述半导体晶片上对应的区域边界；
    其中，相邻的两个所述第一光子集成电路芯片通过固定于该相邻的两个所述第一光子集成电路芯片的部分所述第一表面上的所述第二光子集成电路芯片进行光互连。
  2. 如权利要求1所述的片上光互连结构，其特征在于，
    所述多个第二光子集成电路芯片是无源光子集成电路芯片。
  3. 如权利要求2所述的片上光互连结构，其特征在于，
    针对进行光互连的相邻的两个所述第一光子集成电路芯片，该相邻的两个所述第一光子集成电路芯片的所述多个第一光波导与固定于该相邻的两个所述第一光子集成电路芯片的部分所述第一表面上的所述第二光子集成电路芯片的所述多个第二光波导一一对应，以将该相邻的两个所述第一光子集成电路芯片进行光互连。
  4. 如权利要求3所述的片上光互连结构，其特征在于，
    在所述半导体晶片的厚度方向上，该相邻的两个所述第一光子集成电路芯片的所述多个第一光波导的端部的投影与固定于该相邻的两个所述第一光子集成电路芯片的部分所述第一表面上的每个所述第二光子集成电路芯片的所述多个第二光波导的端部的投影以一一对应的方式交叠。
  5. 如权利要求2所述的片上光互连结构，其特征在于，
    针对进行光互连的相邻的两个所述第一光子集成电路芯片，在该相邻的两个所述第一光子集成电路芯片的所述第一表面上靠近该相邻的两个所述第一光子集成电路芯片在所述半导体晶片上对应的区域边界各设置有至少一个光 束重定向元件，其中，每个所述光束重定向元件用于改变光束的方向以进入每个所述第一光波导和/或每个所述第二光波导中；
    针对固定于该相邻的两个所述第一光子集成电路芯片的部分所述第一表面上的所述第二光子集成电路芯片，在平行该第二光子集成电路芯片所在平面的方向上，在该第二光子集成电路芯片的所述多个第二光波导的两侧均设置有一组光栅耦合器，每组所述光栅耦合器分别与该相邻的两个所述第一光子集成电路芯片的所述多个第一光波导一一对应并且用于光耦合，其中，每组所述光栅耦合器包括至少一个光栅耦合器元件；
    其中，相邻的两个所述第一光子集成电路芯片通过所述光束重定向元件、两组光栅耦合器以及所述多个第二光波导进行光互连。
  6. 如权利要求1所述的片上光互连结构，其特征在于，
    每个所述第一光子集成电路芯片包括多个金属连接柱，并且所述金属连接柱的一侧表面从每个所述第一光子集成电路芯片的所述第一表面露出。
  7. 如权利要求6所述的片上光互连结构，其特征在于，
    所述片上光互连结构还包括固定于至少一个所述第一光子集成电路芯片的所述第一表面上的至少一个电子集成电路芯片。
  8. 如权利要求1所述的片上光互连结构，其特征在于，
    在所述半导体晶片的所述第一表面上设置有多个光耦合区，每个所述光耦合区内设置有光耦合接口。
  9. 如权利要求8所述的片上光互连结构，其特征在于，
    所述片上光互连结构还包括多个伪芯片，所述多个伪芯片一一对应固定于所述半导体晶片的所述第一表面上的所述多个光耦合区上，其中，每个所述伪芯片具有上下开口的空腔，所述空腔的开口面对所述光耦合接口并覆盖所述光耦合接口。
  10. 如权利要求9所述的片上光互连结构，其特征在于，
    所述片上光互连结构还包括塑封层，所述塑封层覆盖在所述半导体晶片的所述第一表面上，并且包覆所述多个伪芯片的侧面、至少一个电子集成电路芯片的侧面以及所述多个第二光子集成电路芯片。
  11. 如权利要求10所述的片上光互连结构，其特征在于，
    所述片上光互连结构还包括多个导光结构，所述多个导光结构与所述多个伪芯片一一对应，其中，每个所述导光结构穿过每个所述伪芯片的所述空腔，以将光信号耦合至对应的所述光耦合接口。
  12. 一种片上光互连结构的制作方法，其特征在于，所述方法包括：
    提供半导体晶片，所述半导体晶片包括多个第一光子集成电路芯片，每个所述第一光子集成电路芯片具有相对的第一表面和第二表面，其中，每个所述第一光子集成电路芯片包括多个第一光波导；
    提供多个第二光子集成电路芯片，每个所述第二光子集成电路芯片包括多个第二光波导，将每个所述第二光子集成电路芯片固定在相邻的两个所述第一光子集成电路芯片的部分所述第一表面上并覆盖相邻的两个所述第一光子集成电路芯片在所述半导体晶片上对应的区域边界；
    其中，针对进行光互连的相邻的两个所述第一光子集成电路芯片，将每个所述第二光子集成电路芯片的所述多个第二光波导与该相邻的两个所述第一光子集成电路芯片的所述多个第一光波导进行一一对准，以将该相邻的两个所述光子集成电路芯片进行光互连。
  13. 如权利要求12所述的片上光互连结构的制作方法，其特征在于，所述方法还包括：
    将每个所述第二光子集成电路芯片以背面贴装的方式固定在相邻的两个所述第一光子集成电路芯片的部分所述第一表面上并覆盖相邻的两个所述第一光子集成电路芯片在所述半导体晶片上对应的区域边界；或者
    去除每个所述第二光子集成电路芯片的底部半导体层，将已去除底部半导体层的每个所述第二光子集成电路芯片以正面贴装的方式固定在相邻的两个所述第一光子集成电路芯片的部分所述第一表面上并覆盖相邻的两个所述第一光子集成电路芯片在所述半导体晶片上对应的区域边界。
  14. 如权利要求13所述的片上光互连结构的制作方法，其特征在于，所述方法还包括：
    在所述半导体晶片的厚度方向上，将该相邻的两个所述第一光子集成电路芯片的所述多个第一光波导的端部的投影与固定于该相邻的两个所述第一光子集成电路芯片的部分所述第一表面上的每个所述第二光子集成电路芯片的 所述多个第二光波导的端部的投影以一一对应的方式交叠，以通过绝热耦合的方式将相邻的两个所述第一光子集成电路芯片进行光互连。
  15. 如权利要求13所述的片上光互连结构的制作方法，其特征在于，所述方法还包括：
    在该相邻的两个所述第一光子集成电路芯片的所述第一表面上靠近该相邻的两个所述第一光子集成电路芯片在所述半导体晶片上对应的区域边界各放置有至少一个光束重定向元件；其中，每个所述光束重定向元件用于改变光束的方向以进入每个所述第一光波导和/或每个所述第二光波导中；以及
    针对固定于该相邻的两个所述第一光子集成电路芯片的部分所述第一表面上的所述第二光子集成电路芯片，在平行于该第二光子集成电路芯片所在平面的方向上，在该第二光子集成电路芯片的所述多个第二光波导的两侧均形成有一组光栅耦合器，每组所述光栅耦合器分别与该相邻的两个所述光子集成电路芯片的所述多个第一光波导一一对应并且用于光耦合，其中，每组所述光栅耦合器包括至少一个光栅耦合器元件；
    其中，相邻的两个所述第一光子集成电路芯片通过所述光束重定向元件、两组光栅耦合器以及所述多个第二光波导进行光互连。
  16. 如权利要求12所述的片上光互连结构的制作方法，其特征在于，所述方法还包括：
    在每个所述第一光子集成电路芯片内制作多个金属连接柱，并将所述金属连接柱的一侧表面从每个所述第一光子集成电路芯片的所述第一表面露出。
  17. 如权利要求16所述的片上光互连结构的制作方法，其特征在于，所述方法还包括：
    在将每个所述第二光子集成电路芯片固定在相邻的两个所述第一光子集成电路芯片的部分所述第一表面上并覆盖相邻的两个所述第一光子集成电路芯片在所述半导体晶片上对应的区域边界之后，针对至少一个所述第一光子集成电路芯片，提供与该第一光子集成电路芯片对应的至少一个电子集成电路芯片，并将所述至少一个电子集成电路芯片固定在该第一光子集成电路芯片的所述第一表面的对应区域。
  18. 如权利要求17所述的片上光互连结构的制作方法，其特征在于，所 述方法还包括：
    在所述半导体晶片的所述第一表面上设置多个光耦合区，在每个所述光耦合区内设置光耦合接口；
    提供多个伪芯片，每个所述伪芯片具有单面开口的空腔，将所述多个伪芯片一一对应固定在所述多个光耦合区上，以使每个所述伪芯片的所述空腔的开口面对所述光耦合接口并覆盖所述光耦合接口。
  19. 如权利要求18所述的片上光互连结构的制作方法，其特征在于，所述方法还包括：
    在将所述多个伪芯片一一对应固定在所述多个光耦合区上之后，在所述半导体晶片的所述第一表面上制作塑封层，所述塑封层包覆所述多个伪芯片的侧面、所述至少一个电子集成电路芯片的侧面以及所述多个第二光子集成电路芯片。
  20. 如权利要求19所述的片上光互连结构的制作方法，其特征在于，所述方法还包括：
    在所述塑封层制作完成之后，在所述半导体晶片远离所述多个第二光子集成电路芯片的一侧对所述半导体晶片的本体进行减薄处理，以露出所述金属连接柱远离所述多个第二光子集成电路芯片一侧的表面。
  21. 如权利要求20所述的片上光互连结构的制作方法，其特征在于，所述方法还包括：
    在露出所述金属连接柱远离所述多个第二光子集成电路芯片一侧的表面之后，在所述半导体晶片的所述第二表面形成与每个所述金属连接柱一一对应电连接的布线层以及导电凸块。
  22. 如权利要求21所述的片上光互连结构的制作方法，其特征在于，所述方法还包括：
    减薄所述塑封层、所述多个伪芯片，使得所述多个伪芯片的空腔上下贯通以及所述多个电子集成电路芯片的远离所述半导体晶片的一侧表面露出。
  23. 如权利要求22所述的片上光互连结构的制作方法，其特征在于，所述方法还包括：
    将导光结构或者激光器芯片通过每个所述伪芯片的开口安装至对应的所 述光耦合接口上。
PCT/CN2023/107090 2022-07-25 2023-07-12 片上光互连结构及其制作方法 WO2024022113A1 (zh)

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