JP5882326B2 - 傾斜スタックチップパッケージにおける光通信 - Google Patents
傾斜スタックチップパッケージにおける光通信 Download PDFInfo
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- JP5882326B2 JP5882326B2 JP2013525930A JP2013525930A JP5882326B2 JP 5882326 B2 JP5882326 B2 JP 5882326B2 JP 2013525930 A JP2013525930 A JP 2013525930A JP 2013525930 A JP2013525930 A JP 2013525930A JP 5882326 B2 JP5882326 B2 JP 5882326B2
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- semiconductor die
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- semiconductor
- optical
- optical signal
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1903—Structure including wave guides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
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Description
分野
本開示は、概して半導体チップパッケージの設計に関する。より具体的には、本開示は、スタック内に配置された一群のチップとスタックに対して角度が付けられた傾斜部品とを含み、半導体ダイと光信号を通信する半導体チップパッケージに関する。
スタック状の半導体チップを含むチップパッケージは、プリント回路基板に接続された従来の個別にパッケージ化されたチップに比べて、非常に高い性能を提供することができる。これらのチップパッケージは、スタック内における異なるチップに対して異なるプロセスを用いる能力、高密度のロジックとメモリとを組み合わせる能力、および、より少電力でデータを転送する能力のような特定の利点も提供する。たとえば、ダイナミックランダムアクセスメモリ(DRAM)を実現するチップのスタックは、ベースチップ内において入出力(I/O)およびコントローラ機能を実現するために高金属層カウント(high-metal-layer-count)で高機能な論理プロセスを使用し、残余のスタックのために、より低い金属層カウント(lower metal-layer-count)でDRAM専用のプロセスチップが用いられ得る。このように、結合された一組のチップは、DRAMプロセスを用いて製造されたI/Oおよびコントローラの機能を含む単一のチップ、ロジックプロセスを用いて製造されたメモリ回路を含む単一のチップ、および/または、ロジックおよびメモリ双方の物理構造を製造するために単一のプロセスを用いようと試みることによって構築されたシステムよりも、良好な性能でかつ低コストを有し得る。
本開示の1つの実施形態は、チップパッケージを提供する。このチップパッケージは、垂直スタック内において垂直スタック内の第1の半導体ダイに実質的に垂直な垂直方向に配列された一組の半導体ダイを含む。さらに、第1の半導体ダイの後の各半導体ダイは、垂直スタック内の直前の半導体ダイからあるオフセット値だけ水平方向にオフセットされ、それによって、垂直スタックの一方の側面に階段状テラスを規定する。さらに、チップパッケージ内の傾斜部品(ramp component)が、半導体ダイに堅固に機械的に結合される。この傾斜部品は、垂直スタックの上記の一方の側面に位置付けられるとともに、水平方向と垂直方向との間である階段状スタックに沿った方向に略平行である。さらに、傾斜部品は、光信号を搬送する光導波路と、光信号を一組の半導体ダイ内のある半導体ダイに光学的に結合する光学結合要素とを含む。
チップパッケージ、チップパッケージを含む電子機器、およびチップパッケージにおいて光信号を通信するための方法の実施が説明される。このチップパッケージは、水平方向に互いにオフセットされた半導体ダイまたはチップの垂直スタックを含み、それによって階段状テラスを規定する。高帯域幅の傾斜部品が、階段状テラスに略平行に位置付けられ、半導体ダイに機械的に結合される。さらに、傾斜部品は、光信号を搬送する光導波路と、その光信号を半導体ダイのうちの1つに光学的に結合する光学結合要素とを含み、それによって、半導体ダイと傾斜部品との間において光信号の高帯域幅通信を容易にする。
Claims (16)
- チップパッケージであって、
垂直スタック内において、前記垂直スタック内の第1の半導体ダイに対して実質的に垂直な垂直方向に接着層を介して配列された一組の半導体ダイを備え、
前記第1の半導体ダイの後の各半導体ダイは、前記垂直スタック内の直前の半導体ダイから、あるオフセット値だけ水平方向にオフセットされ、それによって前記垂直スタックの一方の側面に階段状テラスを規定し、
前記チップパッケージは、
前記半導体ダイに、堅固に機械的に結合された傾斜部品をさらに備え、
前記傾斜部品は、前記垂直スタックの前記一方の側面に位置付けられ、
前記傾斜部品は、水平方向と垂直方向との間である前記階段状テラスに沿った方向に略平行であり、
前記傾斜部品は、はんだ、マイクロスプリング(microspring)、および異方性導電膜
のうちの少なくとも1つを用いて、前記半導体ダイの各々に結合され、
前記傾斜部品は、
光信号を搬送するように構成された光導波路と、
前記光信号を前記一組の半導体ダイにおける1つの半導体ダイに光学的に結合するように構成される光学結合要素とを含む、チップパッケージ。 - 前記傾斜部品は、前記光学結合要素を含む一組の光学結合要素を含み、
前記一組の光学結合要素における所与の光学結合要素は、前記半導体ダイを含む前記一組の半導体ダイにおける所与の半導体ダイに、前記光信号を光学的に結合するように構成される、請求項1に記載のチップパッケージ。 - 前記光導波路は、前記階段状テラスに沿った方向に前記光信号を搬送するように構成され、
前記光学結合要素は、前記半導体ダイの平面内に、前記光信号を方向転換する、請求項1に記載のチップパッケージ。 - 前記光信号は、前記半導体ダイの端部を通して、前記半導体ダイに光学的に結合される、請求項3に記載のチップパッケージ。
- 前記光導波路は、前記階段状テラスに沿った方向に、前記光信号を搬送するように構成
され、
前記光学結合要素は、前記半導体ダイの表面の法線に沿って、前記光信号を方向転換する、請求項1に記載のチップパッケージ。 - 前記光信号は、前記半導体ダイの端部以外の、前記半導体ダイの前記表面上の位置において、前記半導体ダイに光学的に結合される、請求項5に記載のチップパッケージ。
- 前記一組の半導体ダイにおける一対の半導体ダイは、前記傾斜部品を用いることなく、前記対における第1の半導体ダイから前記対における第2の半導体ダイに前記光信号を光学的に結合するように構成される、請求項1に記載のチップパッケージ。
- 前記傾斜部品は、半導体以外の材料上において製造される、請求項1に記載のチップパッケージ。
- 前記傾斜部品は、他の半導体ダイである、請求項1に記載のチップパッケージ。
- 前記傾斜部品は、前記半導体ダイの端部を受け入れる溝部を備える、請求項1に記載のチップパッケージ。
- 電子機器であって、
チップパッケージを備え、
前記チップパッケージは、
垂直スタック内において前記垂直スタック内の第1の半導体ダイに対して実質的に垂直な垂直方向に接着層を介して配列された一組の半導体ダイを含み、
前記第1の半導体ダイの後の各半導体ダイは、前記垂直スタック内の直前の半導体ダイから、あるオフセット値だけ水平方向にオフセットされ、それによって前記垂直スタックの一方の側面に階段状テラスを規定し、
前記チップパッケージは、
前記半導体ダイに、堅固に機械的に結合された傾斜部品をさらに備え、
前記傾斜部品は、前記垂直スタックの前記一方の側面に位置付けられ、
前記傾斜部品は、水平方向と垂直方向との間である前記階段状テラスに沿った方向に略平行であり、
前記傾斜部品は、はんだ、マイクロスプリング(microspring)、および異方性導電膜
のうちの少なくとも1つを用いて、前記半導体ダイの各々に結合され、
前記傾斜部品は、
光信号を搬送するように構成された光導波路と、
前記光信号を前記一組の半導体ダイにおける1つの半導体ダイに光学的に結合するように構成される光学結合要素とを含む、電子機器。 - 光信号を通信するための方法であって、
垂直スタック内において垂直方向に接着層を介して配列された一組の半導体ダイに、堅固に機械的に結合された傾斜部品における光導波路内に前記光信号を搬送するステップを備え、
前記半導体ダイは、水平方向に互いにオフセットされて、それによって、前記垂直スタックの一方の側面に階段状テラスを規定し、
前記傾斜部品は、水平方向と垂直方向との間である前記階段状テラスに沿った方向に略平行に、前記垂直スタックの前記一方の側面上に位置づけられ、
前記傾斜部品は、はんだ、マイクロスプリング(microspring)、および異方性導電膜
のうちの少なくとも1つを用いて、前記半導体ダイの各々に結合され、
前記方法は、
光学結合要素を用いて、前記光導波路からの前記光信号を、前記一組の半導体ダイにおける1つの半導体ダイに光学的に結合するステップをさらに備える、方法。 - 前記階段状テラスにおける異なる段について前記オフセット値を異ならせる、請求項1に記載のチップパッケージ。
- 前記半導体ダイおよび前記接着層のいずれかまたは双方の厚みを、前記垂直方向に変化させる、請求項1に記載のチップパッケージ。
- 前記オフセット値は、前記はんだ、マイクロスプリング、又は異方性導電膜の厚みに基づいて決定される、請求項1に記載のチップパッケージ。
- 前記半導体ダイの端部の表面粗さを、光信号の搬送波長よりも小さくする、請求項1に記載のチップパッケージ。
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US12/868,577 US8290319B2 (en) | 2010-08-25 | 2010-08-25 | Optical communication in a ramp-stack chip package |
PCT/US2011/046518 WO2012027081A2 (en) | 2010-08-25 | 2011-08-04 | Optical communication in a ramp-stack chip package |
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TW201230289A (en) | 2012-07-16 |
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CN103081102A (zh) | 2013-05-01 |
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