JP6000952B2 - 静的屈曲部を有する傾斜スタックチップパッケージ - Google Patents
静的屈曲部を有する傾斜スタックチップパッケージ Download PDFInfo
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- JP6000952B2 JP6000952B2 JP2013527083A JP2013527083A JP6000952B2 JP 6000952 B2 JP6000952 B2 JP 6000952B2 JP 2013527083 A JP2013527083 A JP 2013527083A JP 2013527083 A JP2013527083 A JP 2013527083A JP 6000952 B2 JP6000952 B2 JP 6000952B2
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- semiconductor die
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- semiconductor dies
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Classifications
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L25/0657—Stacked arrangements of devices
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- G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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Description
分野
本開示は、概して、半導体チップパッケージの設計に関する。より具体的には、本開示は、スタック内に配置された一群のチップとスタックに対して角度が付けられた傾斜部品とを含むとともに、静的屈曲部を含む半導体ダイの終端部においてチップと通信するチップパッケージに関する。
スタック状の半導体チップを含むチップパッケージは、プリント回路基板に接続された従来の個別にパッケージ化されたチップに比べて、非常に高い性能を提供することができる。これらのチップパッケージは、スタック内における異なるチップに対して異なるプロセスを用いる能力、高密度のロジックとメモリとを組み合わせる能力、および、より少電力でデータを転送する能力のような特定の利点も提供する。たとえば、ダイナミックランダムアクセスメモリ(DRAM)を実現するチップのスタックは、ベースチップ内において入出力(I/O)およびコントローラ機能を実現するために高金属層カウント(high-metal-layer-count)で高機能な論理プロセスを使用し、残余のスタックのために、より低い金属層カウント(lower metal-layer-count)でDRAM専用のプロセスチップが用いられ得る。このように、結合された一組のチップは、DRAMプロセスを用いて製造されたI/Oおよびコントローラの機能を含む単一のチップ、ロジックプロセスを用いて製造されたメモリ回路を含む単一のチップ、および/または、ロジックおよびメモリ双方の物理構造を製造するために単一のプロセスを用いようと試みることによって構築されたシステムよりも、良好な性能でかつ低コストを有し得る。
本開示の1つの実施形態は、チップパッケージを提供する。このチップパッケージは、垂直スタック内において垂直スタック内の第1の半導体ダイに実質的に垂直な垂直方向に配列された一組の半導体ダイを含む。さらに、第1の半導体ダイの後の各半導体ダイは、垂直スタック内の直前の半導体ダイからあるオフセット値だけ水平方向にオフセットされ、それによって、垂直スタックの一方の側面に階段状テラスを規定する。さらに、傾斜部品(ramp component)が、半導体ダイに電気的にかつ堅固に機械的に結合される。この傾斜部品は、垂直スタックの上記の一方の側面に位置付けられるとともに、水平方向と垂直方向との間である階段状スタックに沿った方向に略平行である。さらに、半導体ダイの各々は、静的屈曲部を含み、それによって、半導体ダイの各々の終端部が上記の方向と平行に、傾斜部品に機械的に結合される。
チップパッケージ、チップパッケージを含む電子機器、およびチップパッケージにおいて信号を通信するための方法の実施が説明される。このチップパッケージは、水平方向に互いにオフセットされた半導体ダイまたはチップの垂直スタックを含み、それによって、露出したパッドを有するテラスを規定する。高帯域幅の傾斜部品が、テラスに略平行に位置付けられ、露出したパッドに電気的かつ機械的に結合される。たとえば、傾斜部品は、はんだ、マイクロスプリング(microspring)、および/または、異方性導電膜を用いて、半導体ダイと結合され得る。さらに、各半導体ダイは静的屈曲部を含み、それによって各半導体ダイの終端部がその方向に平行でかつ傾斜部品に機械的に結合される。これらの終端部は、半導体ダイと傾斜部品との間において、たとえば、近接通信を介して、高帯域幅の信号通信を容易にし得る。
Claims (17)
- チップパッケージであって、
垂直スタックにおいて垂直方向に配列され、前記垂直スタック内の第1の半導体ダイに対して略垂直な一組の半導体ダイを備え、
前記第1の半導体ダイの後の各半導体ダイは、前記垂直スタックにおける直前の半導体ダイからあるオフセット値だけ水平方向にオフセットされ、それによって、前記垂直スタックの一方の側面に階段状テラスを規定し、
前記チップパッケージは、
前記半導体ダイに電気的に、かつ堅固に機械的に結合された傾斜部品をさらに備え、
前記傾斜部品は、前記垂直スタックの前記一方の側面に位置付けられ、
前記傾斜部品は、水平方向と垂直方向との間である前記階段状テラスに沿った方向に対して略平行であり、
前記半導体ダイの各々は、静的屈曲部を含み、それによって、前記半導体ダイの各々の終端部が前記階段状テラスに沿った方向に平行に、前記傾斜部品に機械的に結合される、チップパッケージ。 - 前記屈曲部に関連した前記半導体ダイの各々の応力は、前記半導体ダイの降伏強度よりも小さい、請求項1に記載のチップパッケージ。
- 前記半導体ダイの各々の厚みは、前記半導体ダイの各々が前記屈曲を容易にする曲げモーメントを有するように規定される、請求項1に記載のチップパッケージ。
- 前記傾斜部品は、前記半導体ダイの各々にはんだ付けされる、請求項1に記載のチップパッケージ。
- 前記傾斜部品は、マイクロスプリングによって、前記半導体ダイの各々の終端部に電気的に結合される、請求項1に記載のチップパッケージ。
- 前記傾斜部品は、はんだによって、前記半導体ダイの各々の終端部に電気的に結合される、請求項1に記載のチップパッケージ。
- 前記傾斜部品は、異方性導電膜によって、前記半導体ダイの各々の終端部に電気的に結合される、請求項1に記載のチップパッケージ。
- 前記傾斜部品は、
前記階段状テラスに平行な方向に沿って光信号を搬送するように構成された光導波路と、
一組の光学結合要素とを含み、
前記一組の光学結合要素における所与の光学結合要素は、前記一組の半導体ダイにおける所与の半導体ダイの終端部に、前記光信号を光学的に結合するように構成される、請求項1に記載のチップパッケージ。 - 前記一組の光学結合素子における光学結合素子は、光−電気変換器を含む、請求項8に記載のチップパッケージ。
- 前記傾斜部品は、容量結合近接通信を用いて、前記傾斜部品と前記半導体ダイの各々の終端部との間において、電気信号を電気的に結合するように構成される、請求項1に記載のチップパッケージ。
- 前記半導体ダイの各々の終端部の表面は、エッチピットを含み、
前記半導体ダイにおける前記エッチピットの各々に対して、前記傾斜部品は、対応するエッチピットを含み、
前記チップパッケージは、一組のボールをさらに含み、
前記一組のボールにおける所与のボールは、前記終端部の表面におけるエッチピットと前記傾斜部品内の前記対応するエッチピットとを機械的に結合する、請求項1に記載のチップパッケージ。 - チップパッケージを含む電子演算機器であって、
前記チップパッケージは、
垂直スタックにおいて垂直方向に配列され、前記垂直スタック内の第1の半導体ダイに対して略垂直な一組の半導体ダイを含み、
前記第1の半導体ダイの後の各半導体ダイは、前記垂直スタックにおける直前の半導体ダイからあるオフセット値だけ水平方向にオフセットされ、それによって、前記垂直スタックの一方の側面に階段状テラスを規定し、
前記チップパッケージは、
前記半導体ダイに電気的に、かつ堅固に機械的に結合された傾斜部品をさらに備え、
前記傾斜部品は、前記垂直スタックの前記一方の側面に位置付けられ、
前記傾斜部品は、水平方向と垂直方向との間である前記階段状テラスに沿った方向に対して略平行であり、
前記半導体ダイの各々は、静的屈曲部を含み、それによって、前記半導体ダイの各々の終端部が前記階段状テラスに沿った方向に平行に、前記傾斜部品に機械的に結合される、電子演算機器。 - 信号を通信するための方法であって、
垂直スタック内において垂直方向に配列された一組の半導体ダイに、電気的に、かつ堅固に機械的に結合された傾斜部品内において前記信号を搬送するステップを備え、
前記半導体ダイは、水平方向に互いにオフセットされ、それによって前記垂直スタックの一方の側面に階段状テラスを規定し、
前記傾斜部品は、水平方向と垂直方向の間である前記階段状テラスに沿った方向に略平行に、前記垂直スタックの前記一方の側面に位置付けられ、
前記方法は、
前記一組の半導体ダイにおける所与の半導体ダイに、前記所与の半導体ダイの終端部において前記信号を結合するステップをさらに備え、
前記所与の半導体ダイは、静的屈曲部を含み、それによって、前記終端部が前記階段状テラスに沿った方向に平行に、前記傾斜部品に機械的に結合される、方法。 - 前記傾斜部品は、
前記階段状テラスに平行な方向に沿って光信号を搬送するように構成された光導波路と、
一組の光学結合要素とを含み、
前記一組の光学結合要素における所与の光学結合要素は、前記一組の半導体ダイにおける所与の半導体ダイの終端部に、前記光信号を光学的に結合するように構成される、請求項12に記載の電子演算機器。 - 前記一組の光学結合素子における光学結合素子は、光−電気変換器を含む、請求項14に記載の電子演算機器。
- 前記傾斜部品は、容量結合近接通信を用いて、前記傾斜部品と前記半導体ダイの各々の終端部との間において、電気信号を電気的に結合するように構成される、請求項12に記
載の電子演算機器。 - 前記傾斜部品は、容量結合近接通信を用いて、前記傾斜部品と前記半導体ダイの各々の終端部との間において、電気信号を電気的に結合するように構成される、請求項13に記
載の方法。
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PCT/US2011/046519 WO2012030470A2 (en) | 2010-09-02 | 2011-08-04 | Ramp-stack chip package with static bends |
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