TWI503948B - 高頻寬斜堆式晶片封裝 - Google Patents

高頻寬斜堆式晶片封裝 Download PDF

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Publication number
TWI503948B
TWI503948B TW099122481A TW99122481A TWI503948B TW I503948 B TWI503948 B TW I503948B TW 099122481 A TW099122481 A TW 099122481A TW 99122481 A TW99122481 A TW 99122481A TW I503948 B TWI503948 B TW I503948B
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Taiwan
Prior art keywords
semiconductor
semiconductor dies
semiconductor die
wafer
wafer package
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TW099122481A
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English (en)
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TW201123406A (en
Inventor
Robert J Drost
James G Mitchell
David C Douglas
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Oracle America Inc
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Publication of TW201123406A publication Critical patent/TW201123406A/zh
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Publication of TWI503948B publication Critical patent/TWI503948B/zh

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Description

高頻寬斜堆式晶片封裝
本案大致關係於半導體晶片封裝。更明確地說，本案有關於一晶片封裝，其包含一群排列成堆疊之晶片，及一相對於該堆疊成一角度的斜向元件，該斜向元件係耦接至該等晶片。
包含堆疊半導體晶片的晶片封裝相較於連接至印刷電路板的傳統個別封裝晶片可以提供較高之效能及較低成本。這些晶片封裝也提供某些優點，例如可以：在堆疊中之不同晶片上使用不同製程、組合更高密度邏輯及記憶體、及使用較低功率傳送資料。例如，實施動態隨機存取記憶體(DRAM)的一堆疊晶片可以於一基礎晶片中使用高金屬層計數、高效邏輯製程，以實施輸入/輸出(I/O)及控制器功能，及一組較低金屬層計數、特定DRAM製程之晶片可以作為該堆疊的剩餘部份。在此方式中，相較於包含使用DRAM製程製造的I/O及控制器功能的單晶片；使用邏輯製程製造的記憶體電路的單晶片；及/或想要使用單一製程以完成邏輯及記憶體實體結構者，所組合晶片組合可以具有較佳效能及較低成本。
用以堆疊晶片的現行技術包含打線及貫矽導孔(TSV)。打線為低頻寬、低成本技術，其中晶片被彼此偏移開，以界定晶片緣的樓梯部，其包含外露之黏著墊。至晶片的電連接係藉由打線至這些黏著墊加以實施。
相反地，TSV典型具有較打線為高之頻寬。在TSV製造技術中，晶片係被處理，使得在其作用面上之一或更多之金屬層被導電連接至在其背面上之新墊。然後，晶片被黏著連接為一堆疊，使得在一晶片之背面上之新墊與鄰近晶片之作用面上之對應墊作導電接觸。
然而，TSV典型具有較打線為高之成本。這是因為TSV通過晶片的作用矽層。因此，TSV佔用了原先可以用於電晶體或配線的區域。這機會成本可能很大。例如，如果TSV排除或保持安全(keep-out)直徑為20μm，及TSV被以30μm之間距放置，則大約45%的矽面積被TSV所消耗。這大致為在堆疊中之晶片中之任何電路中之每單位面積成本的兩倍。(事實上，因為電路典型散開以容納TSV，所以消耗似乎更大，這浪費更多面積)。另外，製造TSV通常涉及額外製程操作，這也增加晶片成本。
因此，有需要一晶片封裝，其提供堆疊晶片的優點而沒有上述之問題。
本案之一實施例提供晶片封裝，其包含以垂直方向排列之一堆疊的一組半導體晶粒，該垂直方向實質垂直於一平行於垂直堆疊中之第一半導體晶粒的平面。在此垂直堆疊中，在第一半導體晶粒後，一給定半導體晶粒係比在垂直堆疊中之前一半導體晶粒在該平面中在水平方向中上偏移開一偏移值，藉以在垂直堆疊之一側界定一步階梯台。再者，晶片封裝包含斜向元件，其電及機械耦接至半導體晶粒。該斜向元件定位在垂直堆疊的該一側上，並大致平行於沿著步階梯台的一方向，該方向係在水平方向與垂直方向之間。
注意斜向元件可以為被動元件，例如具有金屬軌跡電耦接至半導體晶粒的塑膠基板。或者，斜向元件可以為另一半導體晶粒。再者，斜向元件可以包含緣連接器，其係組態以可配合電及機械耦接至電路板。
在一些實施例中，晶片封裝包含一基板，在第一半導體晶粒下，其係大約平行於該基板至少電耦接至該斜向元件的平面。
再者，於一些實施例中，晶片封裝包含密封體，其包圍該半導體晶粒及該斜向元件的至少一部份。
另外，斜向元件可以焊接至各個半導體晶粒。為了促成斜向元件焊接至該等半導體晶粒，該等半導體晶粒可以包含凸塊。為了容許在垂直方向之機械對準誤差，凸塊的高及間距可以沿著該垂直方向在半導體晶粒間改變。
在一些實施例中，斜向元件藉由微彈簧及/或各向異性導電膜被電耦接至各個半導體晶粒。為了促成於半導體晶粒與斜向元件間之電耦接，半導體晶粒可以包含在該半導體晶粒的頂面上之加壓元件，其當晶片封裝被組裝時，加壓該各向異性導電膜。
注意，斜向元件可以被機械耦接至半導體晶粒，而不必將半導體晶粒插入斜向元件之槽中。在一些實施例中，斜向元件促成於電信號與電力信間之傳送至半導體晶粒，而不必透過在半導體晶粒中之貫晶片導孔。
再者，斜向元件可以包含用於半導體晶粒的機械止動件，以促成晶片封裝的組裝。
另外，於斜向元件與半導體晶粒中之給定半導體晶粒間之電耦接可以具有複數阻抗，其包含同相成份與異相成份。
在一些實施例中，晶片封裝包含在垂直堆疊中之至少兩半導體晶粒間之中間晶片。該中間晶片可以沿著水平方向傳輸至少一半導體晶粒操作所產生之熱。
在一些實施例中，半導體晶粒的表面包含蝕刻坑，及在蝕刻坑中之球維持垂直堆疊中之半導體晶粒的相對對準。
另一實施例提供電腦系統，其包含該晶片封裝。
另一實施例提供電子裝置，其包含該晶片封裝。
以下說明係使任何熟習於本技藝者可以完成並使用本案，並提供於特定應用及其要求的上下文。對所揭示實施例之各種修改將為熟習於本技藝者所迅速了解，於此所界定的一般原理可以在不脫離本案之精神與範圍下，應用至其他實施例及應用。因此，本案並不限於在此所示之實施例，而是依據於此所揭示之原理與特性的最寬範圍。
於此描述晶片封裝、包含該晶片封裝的電子裝置、及包含該晶片封裝的電腦系統的實施例。此晶片封裝包含一堆疊之半導體晶粒或晶片，其係彼此偏移開，藉以界定具有外露墊之一梯台。定位以大致平行於該梯台之高頻寬斜向元件係電耦接至該外露墊。例如，斜向元件可以使用：微彈簧、各向異性膜、及/或焊錫電耦接至半導體晶粒。因此，電接觸可以具有電導性、電容性、或通常為複合式阻抗。再者，晶片及/或斜向元件可以使用球及坑對準技術而彼此相對定位。
藉由移除在半導體晶粒中之昂貴及消耗大面積之貫矽導孔(TSV)，晶片封裝可以促成晶片被堆疊，以提供高頻寬及低成本。例如，成本可以藉由避免有關於在半導體晶粒中之TSV的處理操作及浪費區域而加以降低。因此，在堆疊中之晶片可以使用標準處理加以製造。再者，微彈簧及/或各向異性膜可以具有低成本及/或可以較打線提供改良的可靠度。注意的是，在晶片與斜向元件間之機械及/或電耦合之實施例為可配合，晶片封裝的良率可以藉由允許重工(例如更換在組裝或燒機時指明為壞晶片)而增加。
另外，晶片封裝可以提供較打線為高之元件間通訊頻寬。雖然在原理上，TSV提供較高頻寬，但這典型需要較大數量的TSV，這消耗在半導體晶粒上之相當大百分比之矽面積。對於消耗較少矽面積之適量之TSV，斜向元件可以提供相當的元件間通訊頻寬。
現描述晶片封裝的實施例。圖1A顯示晶片封裝100的側視圖的方塊圖，晶片封裝100包含一組晶片或半導體晶粒110沿著垂直方向120排列成堆疊116，該垂直方向120係實質垂直於平行於半導體晶粒110-1的一平面。在此垂直堆疊中，在半導體晶粒110-1後的各個半導體晶粒(例如半導體110-2)可以在水平方向118在該平面中比在該垂直堆疊116中的前一半導體晶粒偏移至少一最小偏移值126，藉以在垂直堆疊116的一側界定一步階梯台128(具有固定角124)。再者，晶片封裝100包含斜向元件112，其係電及機械耦接至半導體晶粒110。該斜向元件係定位在垂直堆疊116的該一側上，並大致平行於沿著步階梯台128的方向122，該方向122係在水平方向118與垂直方向120之間。
在一些實施例中，半導體晶粒110係使用標準矽處理加以製造。尤其，在這些實施例中，半導體晶粒110並未包含TSV。這些半導體晶粒可以提供矽面積，其支援邏輯及/或記憶體功能。
再者，半導體晶粒110可以透過斜向元件112彼此相通訊在與外部裝置或系統通訊。尤其，如圖1A所示，斜向元件112可以經由微彈簧114電耦接至各個半導體晶粒110。注意，微彈簧114可以製造在各種表面上，包含：印刷電路板(PCB)、有機或陶瓷積體電路(IC)、及/或半導體晶粒的表面上。再者，微彈簧114可以被製造為具有晶片間連接的區域密度超出在高效IC上之輸入/輸出(I/O)信號的密度，並且微彈簧114的順應性可以增加在晶片封裝100中之元件的機械移動及失準的容許度。
微彈簧114也可以提供機械及電氣接觸，而不必使用焊錫。因此，在斜向元件112與半導體晶粒110間之機械及/或電氣耦接可以被移除或重新配合(即這些元件可以可配合地耦接)，這促成在組裝與測試時及/或之後的晶片封裝100的重工。注意該重新配合機械或電氣耦接應被了解為機械或電氣耦接可以重覆地被建立及破壞(即兩或更多次)而不需重工或加熱(例如用焊錫)。在一些實施例中，該可重新配合機械或電氣耦接涉及公及母元件，這些被設計以彼此耦接(例如元件被搭鎖在一起)。因此，可重新配合元件係可以組態以允許可重新配合建立耦接。然而，如以下參考圖2B所詳述，在一些實施例中，在斜向元件112與半導體晶粒110間之機械及/或電氣耦接可以更永久(例如，其可以不是可重新配合的，例如焊錫接觸)。
注意，斜向元件112可以為被動元件，例如具有金屬軌跡以電耦接至半導體晶粒110的塑膠基板。例如，斜向元件112可以使用射出成型塑膠加以製造。或者，斜向元件112可以為具有光微影界定的線或信號線之另一半導體晶粒。在斜向元件112包含半導體晶粒的實施例中，可以包含有例如限制放大器之主動裝置，以降低於信號線間之串音。另外，串音可以藉由在主動或被動斜向元件112中使用差動信號加以降低。
在一些實施例中，斜向元件112包含電晶體及配線，以經由微彈簧114傳送資料及電源信號於半導體晶粒110之間。例如，斜向元件112可以包含高壓信號。這些信號可以使用：降壓調整器(例如電容至電容降壓調整器)、及電容及/或電感分立元件，以耦接至半導體晶粒110來降壓，以用於半導體晶粒110上。
在一些實施例中，晶片封裝100在半導體晶粒110-1下包含選用基板130，其係大致平行於該平面。此選用基板130係至少電耦接至斜向元件112(這可以促成與半導體晶粒110之電或電源信號的傳輸，而不必使用在半導體晶粒110中之TSV)，並且，可以堅固地機械耦接至半導體晶粒110-1。再者，選用基板130可以包含：用於記憶體的緩衝器或邏輯晶片；及/或至外部裝置及/或系統的輸入/輸出(I/O)。例如，I/O可以包含一或更多球黏結或線黏結(如圖1A所示)。
注意，在晶片封裝100的至少一部份旁，有選用密封體132-1。
圖1B表示晶片封裝100的俯視圖的方塊圖，其具有四半導體晶粒110。此圖顯示選用基板130可以延伸超出堆疊116(圖1A)，使得選用基板130有多達四個邊緣可以被取用作通訊，使用：打線、球黏結、及/或鄰近通訊(PxC)。
通常，半導體晶粒110及斜向元件112、斜向元件112及選用基板130、選用基板130及外部裝置或系統、及/或斜向元件112及外部裝置或系統可以使用電磁耦接信號之PxC彼此通訊(這可以稱為“電磁鄰近通訊”)，例如，電容耦合信號及/或光學信號的鄰近通訊(這係分別稱為“電鄰近通訊”及“光鄰近通訊”)。在一些實施例中，電磁鄰近通訊包含電感耦合信號及/或導通耦合信號。
因此，有關於微彈簧114與半導體晶粒110間之電接觸之阻抗可以為電導性(即同相)及/或電容性(即異相)，例如，當有一鈍化層(如玻璃管)時，在金屬墊上或鄰近於半導體晶粒110的表面。通常，阻抗可以為複數，其包含同相成份與異相成份。不管電接觸機制為何(例如微彈簧114、參考圖2A所述之非等向層、或參考圖2B所述之焊錫)，如果相關於接觸的阻抗為導電性，則傳統發射及接收I/O電路可以用於晶片封裝100的元件中。然而，對於具有複數(及可能變數)阻抗，發射及接收I/O電路可能包含一或更多於美國申請案第12/425,871號案所述之實施例中，該案名為“具有可變複數阻抗的連接器接收電路”，為Robert Drost等人所申請於2009年4月17日，其整個文件併入作為參考。
注意，在一些實施例中，其中在給定半導體晶粒上可能有兩或更多微彈簧114幾何。例如，資料信號微彈簧可能較短並具有鈍端，而電源信號微彈簧可能較長並具有尖端。另外，藉由包含額外電源信號微彈簧，即使部份數量之功率信號微彈簧損失其連接性，仍可以加強良率及長期可靠度。
為了增加接觸的電容性，在一些實施例中，導電液、膏或膜可以被加入至接觸區，以填入任一間隙內。這也有增加重疊面積的有利效果，以到達液體、膏或膜延伸超出給定微彈簧的邊緣的程度。
雖然圖1A及1B顯示晶片封裝100的特定組態，但若干技術及組態可以使用以實施：電接觸、機械對準、組裝、及/或與斜向元件112及/或選用基板130的電I/O。現在說明這些實施例之幾個實施例。
圖2A顯示一晶片封裝200的方塊圖，其中斜向元件112係為各向異性膜210，例如各向異性彈性膜(其有時被稱為“各向異性導電膜”)所電耦接至半導體晶粒110。注意，各向異性膜210的各向異性特性加強垂直於各向異性膜210的表面之導電率，同時，也減少正切於各向異性膜210表面的導電率。結果，各向異性膜210電耦接至各向異性膜210的相反面上之機械對準墊。
例如，各向異性膜210可以包含PariPoser材料(來自麻州秋河之Paricon技術公司)，及若干專利各向異性膜包含：美國專利5,624,268之名為“使用各向異性導電膜之電導體”及美國專利4,778,950之名為“各向異性彈性互連系統”。在PariPoser類型之各向異性導電彈性膜中，小導電球係被懸浮於矽膠中，使得球大致對準行並提供垂直於該各向異性膜表面而並非正切的電導。有關於微彈簧114(圖1A)，通常，所得電接觸的阻抗可以為電導及/或電容性的。如果阻抗為電導性，則傳統發射及接收I/O電路可以用於晶片封裝200的元件中。然而，如果，阻抗為複數，則在晶片封裝200中之發射及接收I/O電路可以包含一或更多於美國專利申請12/425,871案中所述之實施例。
在一些實施例中，於經過各向異性膜210的半導體晶粒110與斜向元件112間之電耦接係在半導體晶粒110及/或斜向元件112的頂面上使用加壓元件加以完成(例如，加壓元件212-1及214-1)，該等元件當晶片封裝200被組裝時，加壓各向異性膜210。
或者，如圖2B所示，其顯示晶片封裝250的方塊圖，斜向元件112及半導體晶粒110間之電接觸可以使用焊錫(例如可迴焊錫層)加以實施。例如，微彈簧260(或線)可以焊接至凸塊，例如在半導體晶粒110之表面上的凸塊262-1。為了容許在垂直方向120的機械對準誤差(圖1A)，凸塊的高度及間隔可以沿著垂直方向120在半導體晶粒110間作改變(圖1A)。在一例示實施例中，在斜向元件112被相對於半導體晶粒110及/或選用基板130作機械定位後，晶片封裝250被加熱及焊錫被迴焊，在微彈簧260與半導體晶粒110及/或選用基板130間形成焊接接頭。
雖然在半導體晶粒110中可能沒有TSV，但在一些實施例中，TSV係包含在選用基板130中。這是如圖3A所示，其呈現晶片封裝300的方塊圖。面焊接黏結312也可以使用以電耦接選用基板130至其他半導體晶粒及/或PCB。通常，對於選用基板130在打線及TSV(具有面焊接黏結)間有成本及效能上之取捨。不同於在堆疊中之半導體晶粒110，所增加之成本可能在選用基板130中更能忍受，因為其通常為昂貴晶片，其可以每一晶片封裝使用一次。也可以想到，使用打線與TSV的組合於相同的選用基板130上。
再者，雖然圖1A顯示打線至選用基板130，但在其他實施例中，選用基板130包含連接器。這在圖3B中看出，其顯示出晶片封裝330的方塊圖，其在一端具有連接器340及另一端具有選用連接器342。這些連接器可以包含緣連接器，其係被組態以可電重合及機械耦接至PCB。或者，或額外地，連接器可以包含PxC連接器。
在一些實施例中，連接器340及/或選用連接器342係包含在斜向元件112的前及/或背面上。這是如圖3C所示，其顯示晶片封裝360的方塊圖。
如圖3D所示之另一組態顯示晶片封裝380的方塊圖。在此晶片封裝中，基礎晶片390係藉由在斜向元件392之背面上的一或更多微彈簧(例如微彈簧394)耦接至斜向元件392。這些微彈簧係電耦接至微彈簧114，因此，藉由穿過斜向元件392的一或更多導孔(例如導孔396)而電耦接至半導體晶粒110。
如前所注意，各種類型對準技術可以使用於晶片封裝的實施例中。一對準技術涉及使用蝕刻坑配合在蝕刻坑中之球體，以維持在堆疊中之半導體晶粒110的相對對準。這是如圖4A所示，其呈現晶片封裝400的方塊圖，其包含球(例如球410-1)及相關坑(例如坑412-1)。球-及-蝕刻-坑對準技術可以將半導體晶粒110及/或選用基板130的表面對準，以略微壓力將表面咬在一起，而具有低於1微米的機械公差。在施加此壓力之前，可以使用取放機，以當將元件放在一起時，完成少於10微米的機械公差。以少許額外時間(及所得組裝成本)，這些機器可以將元件對準，而有少於1微米的機械公差。假定這些啟始對準，則有可能將選用基板130及半導體晶粒110黏著，以在半導體晶粒110間形成空間上良好定義的梯台128。在此例子中，其足夠將斜向元件112對準至選用基板130或對準半導體晶粒110之至少一個。
例如，一最小配置可使用兩坑，以將斜向元件112的表面的x-y位置固定至選用基板130及固定至半導體晶粒110群。施加至斜向元件112及選用基板130的背面之機械力將壓縮斜向元件112以與選用基板130及半導體晶粒110接觸。然而，熱失真或其他機械力可能造成弱黏著技術無法提供堅固的長期晶片封裝技術。雖然選用基板130及半導體晶粒110的堅強永久黏著很堅固，但在組裝及測試及/或在佈署後，可能防止重工。通常，當面對低半導體晶粒良率或對封裝及組裝前的密集測試成本高時，允許部份重工之封裝技術係較符成本效益的。因此，避免堅強黏著，對於封裝技術可能有利的。
在晶片封裝400中，球及坑係被使用以對準斜向元件112，及選用基板130與半導體晶粒110。在此配置中，這些元件均不需要永久或弱黏著。除了球-及-蝕刻-坑對準技術外，相關半球形凸塊-及-坑技術也可以使用以對準該等元件，以組合或替換任一球及蝕刻坑。通常，在斜向元件112、選用基板130及/或半導體晶粒110之機械正鎖及負面特性的任意組合可以對準元件，而不必或組合黏劑。
注意在一些實施例中，使用電子對準技術，以校正在晶片封裝中之平面機械失準。例如，如果給定微彈簧接觸一陣列之發射或接收微墊或微柱，則電子對準可以與電導及/或電容性接觸一起使用。
在一些實施例中，斜向元件112包含促進晶片封裝組裝的特性。這是如圖4B所示，其顯示一方塊圖，顯示一晶片封裝450，其包含機械止動件，例如在半導體晶粒110上之機械止動件460-1。例如，機械止動件可以使用聚醯亞胺製造。藉由將半導體晶粒110沿著水平方向118推向斜向元件112(圖1A)，這些機械止動件可以促成在半導體晶粒110與斜向元件112間之良好機械接觸。另外，機械止動件可以降低對半導體晶粒110的粗糙緣(及可能差界定)的靈敏度。在一些實施例中，斜向元件112機械耦接至半導體晶粒110，而不必將半導體晶粒110插入在斜向元件112中之槽內。
在一些實施例中，一晶片封裝包含特性，以移除於電路操作而產生在一或更多半導體晶粒110、斜向元件112及/或選用基板130上的熱。這係在圖5所示，圖5顯示一晶片封裝500的方塊圖。尤其，晶片封裝500包含於至少兩半導體晶粒110間之中間晶片或層510。此中間晶片可以傳送至少一半導體晶粒操作所產生之熱量沿著水平方向118(圖1A)。再者，熱傳送也可以藉由在中間晶片510上之微流體促成。注意，在一些實施例中，中間晶片510也可以降低於兩或更多半導體晶粒110間之串音。
在一例示實施例中，堆疊116(圖1A)包含DRAM記憶體單元及一些用於這些記憶體單元的支援電路。再者，選用基板130包含I/O電路及/或另外DRAM支援電路(例如電路以選擇位元、列、行、方塊及/或排，及晶片冗餘)。
替代或外加地，堆疊116(圖1A)可以包含靜態隨機存取記憶體(SRAM)巨集及一些用於這些巨集的支援電路。在這些實施例中，選用基板130可以包含額外SRAM支援電路(例如冗餘)，及開關及I/O電路。
我們現在描述電子裝置及電腦系統的實施例。圖6呈現一方塊圖，其顯示電子裝置600，其包含一或更多晶片封裝612，例如先前實施例之晶片封裝之一。
圖7呈現一方塊圖，其顯示一電腦系統700，其包含一或更多晶片封裝708，其例如先前實施例之晶片封裝之一。電腦系統700包含：一或更多處理器(或處理器核心)710、通訊界面712、使用者界面714、及將這些元件耦接在一起之一或更多信號線722。注意，一或更多處理器(或處理器核心)710可以支援平行處理及/或多線運算，該通訊界面712可以具有永久通訊連接，及該一或更多信號線722可以構成一通訊匯流排。再者，使用者界面714可以包含：顯示器716、鍵盤718、及/或指標720，例如滑鼠。
在裝置700中之記憶體724可以包含揮發記憶體及/或非揮發記憶體。更明確地說，記憶體724可以包含：ROM、RAM、EPROM、EEPROM、快閃、一或更多智慧卡、一或更多磁碟儲存裝置、及/或一或更多光學儲存裝置。記憶體724可以儲存作業系統726，其包含用以處理各種基本系統服務，以執行硬體相關工作之程序(或一組指令)。再者，記憶體724也可以儲存通訊程序(或一組指令)於通訊模組728中。這些通訊程序也可以用於與一或更多電腦、裝置及/或伺服器相通訊，這些包含相對於裝置700為遠端定位的電腦、裝置及/或伺服器。
記憶體724也可以包含一或更多程式模組730(或一組指令)。注意，一或更多程式模組730可以構成一電腦程式機制。在各種模組中之指令也可以以：高階程序語言、物件導向程式語言、及/或組合或機器語言實施在記憶體724中。程式語言可以被編譯或解譯，即可組態或組態為該一或更多處理器(或處理器核心)710執行。
電腦系統700可以包含但並不限於：伺服器、膝上型電腦、個人電腦、工作站、主機電腦、刀鋒(blade)、企業電腦、資料中心、攜帶式計算裝置、超級電腦、連網路儲存(NAS)系統、儲存區域網路(SAN)系統、及/或另一電子計算裝置。例如，晶片封裝708可以包含於耦接至多處理器刀鋒之背板(backplane)中，或者，晶片封裝708可以耦接不同類型之元件(例如處理器、記憶體、I/O裝置、及/或週邊裝置)。因此，晶片封裝708可以執行功能有：開關、集線器、橋接器、及/或路由器。注意電腦系統700可以在一位置或可以分散在多個地理上分開之位置。
晶片封裝100(圖1A及1B)、晶片封裝200(圖2A)、晶片封裝250(圖2B)、晶片封裝300(圖3A)、晶片封裝330(圖3B)、晶片封裝360(圖3C)、晶片封裝380(圖3D)、晶片封裝400(圖4A)、晶片封裝450(圖4B)、晶片封裝500(圖5)、電子裝置600(圖6)及/或電腦系統700可以包含較少元件或額外元件。例如，參考回到圖1A，在堆疊116中之半導體晶粒110可以具有不同厚度或寬度。為了維持斜向元件112相對於選用基板130及半導體晶粒110的表面固定角度124，較厚半導體晶粒110的水平位置中之偏移可以大於較薄半導體晶粒110的水平位置中的偏移。
再者，也可以採用若干加強法，以改良由選用基板130及半導體晶粒110的電力分佈。也可以使用傳統打線法，組合斜向元件112，以連接選用基板130及半導體晶粒110。一些半導體晶粒110及/或斜向元件112可以在啟始矽製造後再包含厚頂金屬層或再分佈層(RDL)，以降低電力分佈網路的電阻。另外，斜向元件112可以包含額外供應器解耦電容，例如，藉由製造電容於矽晶粒上或藉由將分立電容焊至其背面並使用TSV，在另一技術中，以電連接分立電容至電源供應器輸送或調整電路。電力也可以透過主動調整網路輸送。例如，例如升壓轉換器或電容-至-電容轉換器的電路可以包含在斜向元件112及/或選用基板130上，以改良輸送至半導體晶粒110的電源供應的品質。
再者，雖然這些裝置及系統係被顯示為具有若干分立項目，但這些實施例係想要各種特性的功能說明，其可以顯示為於此所述實施例以外之結構示意。因此，在這些實施例中，兩或更多元件可以被組合為單一元件及/或一或更多元件的位置可以改變。再者，在兩或更多先前實施例中之特性可以被彼此組合。
注意，有些或所有電子裝置600(圖6)及/或電腦系統700的功能可以被實施於一或更多特定應用積體電路(ASIC)及/或一或更多數位信號處理器(DSP)。再者，在前述實施例中之功能可以被實施為硬體多些及軟體少些，或者硬體少些及軟體多些，如同於本技藝中所知。
雖然前述實施例使用半導體晶粒110(例如矽)於晶片封裝中，但在其他實施例中，半導體以外之不同材料也可以使用為在一或更多這些晶片之基板材料。
本案之實施例的前述說明已經為了顯示及說明的目的加以進行。它們並不是用以排除或限制本發明至所揭示之形式。因此，很多修改及變化將為熟習於本技藝者所知。另外，以上之揭示並不想用以限制本案。本案之範圍係為隨附之申請專利範圍所界定。
100．．．晶片封裝
110-1-4．．．半導體晶粒
112．．．斜向元件
114．．．微彈簧
116．．．垂直堆疊
118．．．水平方向
120．．．垂直方向
122．．．方向
124．．．角
126．．．偏移值
128．．．步階梯台
130．．．選用基板
200．．．晶片封裝
210．．．各向異性膜
212．．．加壓元件
214．．．加壓元件
250．．．晶片封裝
260．．．微彈簧
262-1．．．凸塊
300．．．晶片封裝
312．．．面焊接黏結
310-1．．．導孔
330．．．晶片封裝
340．．．連接器
342．．．選用連接器
132-1．．．選用密封體
360．．．晶片封裝
380．．．晶片封裝
390．．．基礎晶片
392．．．斜向元件
394．．．微彈簧
396．．．導孔
400．．．晶片封裝
410-1．．．球
412-1．．．坑
450．．．晶片封裝
460-1．．．機械止動件
500．．．晶片封裝
510．．．中間層
600．．．電子裝置
612．．．晶片封裝
700．．．電腦系統
708．．．晶片封裝
710．．．處理器
712．．．通訊界面
714．．．使用者界面
716．．．顯示器
718．．．鍵盤
720．．．指標
722．．．信號線
724．．．記憶體
726．．．作業系統
728．．．通訊模組
730．．．程式模組
圖1A為顯示依據本案實施例之晶片封裝的方塊圖。
圖1B為顯示依據本案實施例之晶片封裝的方塊圖。
圖2A為顯示依據本案實施例之晶片封裝的方塊圖。
圖2B為顯示依據本案實施例之晶片封裝的方塊圖。
圖3A為顯示依據本案實施例之晶片封裝的方塊圖。
圖3B為顯示依據本案實施例之晶片封裝的方塊圖。
圖3C為顯示依據本案實施例之晶片封裝的方塊圖。
圖3D為顯示依據本案實施例之晶片封裝的方塊圖。
圖4A為顯示依據本案實施例之晶片封裝的方塊圖。
圖4B為顯示依據本案實施例之晶片封裝的方塊圖。
圖5為顯示依據本案實施例之晶片封裝的方塊圖。
圖6為顯示包含依據本案實施例之一或更多晶片封裝的電子裝置的方塊圖。
圖7為顯示包含依據本案實施例之一或更多晶片封裝的電腦系統之方塊圖。
注意，相類似元件符號表示所有圖式中之對應元件。再者，相同元件的多個實例係以與數字分開橫線之共同字首加以表示。
100．．．晶片封裝
110-1,110-2,110-N．．．半導體晶粒
112．．．斜向元件
114．．．微彈簧
116．．．垂直堆疊
118．．．水平方向
120．．．垂直方向
122．．．方向
124．．．角
126．．．偏移值
128．．．步階梯台
130．．．選用基板
132-1．．．選用密封體

Claims (20)

  1. 一種晶片封裝，包含：一組半導體晶粒，於垂直方向排列成一堆疊，該垂直方向係實質垂直於平行該垂直堆疊中的第一半導體晶粒的平面，其中，在該第一半導體晶粒後的給定半導體晶粒係比在該垂直堆疊中的前一半導體晶粒於該平面中的水平方向偏移一偏移值，藉以在該垂直堆疊的一側，界定一步階梯台；及一斜向元件，電及機械耦接至該半導體晶粒，其中該斜向元件係定位在該垂直堆疊的該一側上，及其中該斜向元件係大約平行於沿著該步階梯台的介於該水平方向與該垂直方向之間的方向，其中該等半導體晶粒的一或多者包括至少一機械止動件，由該至少一或多者半導體晶粒平行於該平面的表面以該垂直方向突出，其中該斜向元件的大約平行於沿著該步階梯台方向的一側停放在該至少一機械止動件上，及其中該等機械止動件促成該晶片封裝的組裝。
  2. 如申請專利範圍第1項所述之晶片封裝，其中該斜向元件為被動元件。
  3. 如申請專利範圍第2項所述之晶片封裝，其中該被動元件包含具有金屬軌跡的塑膠基板，以電耦接至該半導體晶粒。
  4. 如申請專利範圍第1項所述之晶片封裝，其中該斜向元件為另一半導體晶粒。
  5. 如申請專利範圍第1項所述之晶片封裝，其中該斜向元件包含一緣連接器，其係組態以可配合地電及機械耦接至電路板。
  6. 如申請專利範圍第1項所述之晶片封裝，更包含密封體，包圍住該等半導體晶粒及該斜向元件的至少一部份。
  7. 如申請專利範圍第1項所述之晶片封裝，其中該斜向元件係被焊接至各個該等半導體晶粒。
  8. 如申請專利範圍第7項所述之晶片封裝，其中該等半導體晶粒包含凸塊，其促成該斜向元件至該等半導體晶粒的焊接，其中該等凸塊的高度及間距沿著該垂直方向在半導體晶粒間變化。
  9. 如申請專利範圍第1項所述之晶片封裝，其中該斜向元件被微彈簧所電耦接至各個該等半導體晶粒。
  10. 如申請專利範圍第1項所述之晶片封裝，其中該斜向元件係為各向異性導電膜所電耦接至各個該等半導體晶粒。
  11. 如申請專利範圍第10項所述之晶片封裝，其中該等半導體晶粒包含在該等半導體晶粒頂面上的加壓單元，其當該晶片封裝被組裝時，加壓該各向異性導電膜，藉以促成該等半導體晶粒與該斜向元件間之電耦接。
  12. 如申請專利範圍第1項所述之晶片封裝，其中該斜向元件被機械耦接至該等半導體晶粒，而不必將該等半導體晶粒插入在該斜向元件的槽中。
  13. 如申請專利範圍第1項所述之晶片封裝，其中在 該斜向元件與在該等半導體晶粒中的一給定半導體晶粒間之電耦接具有複數阻抗，其包含同相成份與異相成份。
  14. 如申請專利範圍第1項所述之晶片封裝，其中該斜向元件促成該等電信號與電源信號的傳送至該等半導體晶粒，而不需在該等半導體晶粒中之貫片導孔。
  15. 如申請專利範圍第1項所述之晶片封裝，更包含一中間晶片在該垂直堆疊中的至少兩該等半導體晶粒間，其中該中間晶片係被組態以沿著該水平方向傳送至少一該等半導體晶粒之操作所產生之熱。
  16. 如申請專利範圍第1項所述之晶片封裝，其中該等半導體晶粒的表面包含蝕刻坑；及其中在該等蝕刻坑中的球維持該等半導體晶粒在該垂直堆疊中的相對對準。
  17. 如申請專利範圍第1項所述之晶片封裝，其中該等半導體晶粒係沿著該水平方向被推壓向該斜向元件，使得該斜向元件中平行於大致沿著該步階梯台的該方向的一側與該至少一機械止動件機械接觸，及其中該機械止動件並未提供電接觸。
  18. 如申請專利範圍第1項所述之晶片封裝，更包含一基板在該第一半導體晶粒下，大致平行該平面，其中該基板藉由使用微彈簧被至少電耦接至該斜向元件，其中該斜向元件並未接觸該基板。
  19. 一種電腦系統，包含晶片封裝，其中該晶片封裝包含： 一組半導體晶粒，在垂直方向排列成堆疊，該垂直方向係實質垂直於平行該垂直堆疊中的第一半導體晶粒的平面，其中在該第一半導體晶粒後的給定半導體晶粒比在該垂直堆疊中的前一半導體晶粒，在該平面的水平方向中偏移一偏移值，藉以在該垂直堆疊的一側界定一步階梯台；及一斜向元件，電及機械耦接至該等半導體晶粒，其中該斜向元件係定位在該垂直堆疊的該一側上，及其中該斜向元件係大約平行於沿著該步階梯台的介於該水平方向與該垂直方向之間的方向，其中該等半導體晶粒的一或多者包括至少一機械止動件，由該至少一或多者半導體晶粒平行於該平面的表面以該垂直方向突出，其中該斜向元件的大約平行於沿著該步階梯台方向的一側停放在該至少一機械止動件上，及其中該等機械止動件促成該晶片封裝的組裝。
  20. 一種包含晶片封裝之電子裝置，其中該晶片封裝包含：一組半導體晶粒，在垂直方向排列成堆疊，該垂直方向係實質垂直於一平面，該平面係平行於在該垂直堆疊中的第一半導體晶粒，其中在該第一半導體晶粒後的給定半導體晶粒比在該垂直堆疊中的前一半導體晶粒在該平面中的水平方向偏移一偏移值，藉以在該垂直堆疊的一側界定一步階梯台；及一斜向元件，電及機械耦接至該等半導體晶粒，其中 該斜向元件係定位在該垂直堆疊的該一側上，及其中該斜向元件大約平行於沿著該步階梯台介於該水平方向與該垂直方向之間的方向，其中該等半導體晶粒的一或多者包括至少一機械止動件，由該至少一或多者半導體晶粒平行於該平面的表面以該垂直方向突出，其中該斜向元件的大約平行於沿著該步階梯台方向的一側停放在該至少一機械止動件上，及其中該等機械止動件促成該晶片封裝的組裝。
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EP2958143B1 (en) 2017-12-27
EP2958143A1 (en) 2015-12-23
US20110018120A1 (en) 2011-01-27
CN102484108A (zh) 2012-05-30
EP2457253A1 (en) 2012-05-30
WO2011011212A1 (en) 2011-01-27
US8476749B2 (en) 2013-07-02
TW201123406A (en) 2011-07-01

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