JP2007258448A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2007258448A JP2007258448A JP2006080903A JP2006080903A JP2007258448A JP 2007258448 A JP2007258448 A JP 2007258448A JP 2006080903 A JP2006080903 A JP 2006080903A JP 2006080903 A JP2006080903 A JP 2006080903A JP 2007258448 A JP2007258448 A JP 2007258448A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- semiconductor chip
- package substrate
- heat spreader
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
【解決手段】実装面においてパッケージ基板1に実装され、反対面にはんだ接合面2を備える半導体チップ3と、パッケージ基板1に対向して半導体チップ3の収容空間4の内壁面を構成する基板対向面5から半導体チップ3のはんだ接合面2に向けて突出する接合突部6を備えたヒートスプレッダ7とを有し、ヒートスプレッダ7と半導体チップ3とは、接合突部6と半導体チップ3との突き当て部を越えて、前記接合突部6をほぼ等幅で包囲する基板対向面5上の領域まで広がったはんだ層8を介して接合される。
【選択図】 図1
Description
2 はんだ接合面
3 半導体チップ
4 収容空間
5 基板対向面
6 接合突部
7 ヒートスプレッダ
8 はんだ層
9 凹溝
10 はんだシート
Claims (5)
- 実装面においてパッケージ基板に実装され、反対面にはんだ接合面を備える半導体チップと、
パッケージ基板に対向して半導体チップの収容空間の内壁面を構成する基板対向面から半導体チップのはんだ接合面に向けて突出する接合突部を備えたヒートスプレッダとを有し、
前記ヒートスプレッダと半導体チップとは、接合突部と半導体チップとの突き当て部を越えて、前記接合突部をほぼ等幅で包囲する基板対向面上の領域まで広がったはんだ層を介して接合される半導体装置。 - 前記接合突部の基端部全周に前記はんだ層の展開領域を規制する凹溝が形成される請求項1記載の半導体装置。
- 請求項1または2記載の半導体装置が実装されたプリント基板。
- 請求項1または2記載の半導体装置が実装されたプリント基板が搭載された電子装置。
- パッケージ基板上に実装された半導体チップにヒートスプレッダをはんだ付けする工程を有し、
該はんだ付け工程が、半導体チップに比して大面積のはんだシートをリフローして行われる半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006080903A JP2007258448A (ja) | 2006-03-23 | 2006-03-23 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006080903A JP2007258448A (ja) | 2006-03-23 | 2006-03-23 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2007258448A true JP2007258448A (ja) | 2007-10-04 |
Family
ID=38632385
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006080903A Pending JP2007258448A (ja) | 2006-03-23 | 2006-03-23 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2007258448A (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010182855A (ja) * | 2009-02-05 | 2010-08-19 | Nec Corp | 半導体の冷却構造及びその製造方法 |
US8299607B2 (en) | 2010-05-17 | 2012-10-30 | Fujitsi Semiconductor Limited | Semiconductor device |
WO2017179264A1 (ja) * | 2016-04-15 | 2017-10-19 | オムロン株式会社 | 半導体装置の放熱構造 |
CN115954274A (zh) * | 2021-10-06 | 2023-04-11 | 星科金朋私人有限公司 | 具有开窗式散热器的封装 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04263457A (ja) * | 1991-02-18 | 1992-09-18 | Fujitsu Ltd | 半導体装置 |
JPH05183076A (ja) * | 1992-01-07 | 1993-07-23 | Fujitsu Ltd | 半導体パッケージ |
JPH06232299A (ja) * | 1993-02-03 | 1994-08-19 | Nec Corp | 半導体装置 |
JP2005136018A (ja) * | 2003-10-29 | 2005-05-26 | Denso Corp | 半導体装置 |
-
2006
- 2006-03-23 JP JP2006080903A patent/JP2007258448A/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04263457A (ja) * | 1991-02-18 | 1992-09-18 | Fujitsu Ltd | 半導体装置 |
JPH05183076A (ja) * | 1992-01-07 | 1993-07-23 | Fujitsu Ltd | 半導体パッケージ |
JPH06232299A (ja) * | 1993-02-03 | 1994-08-19 | Nec Corp | 半導体装置 |
JP2005136018A (ja) * | 2003-10-29 | 2005-05-26 | Denso Corp | 半導体装置 |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010182855A (ja) * | 2009-02-05 | 2010-08-19 | Nec Corp | 半導体の冷却構造及びその製造方法 |
US8299607B2 (en) | 2010-05-17 | 2012-10-30 | Fujitsi Semiconductor Limited | Semiconductor device |
US8933560B2 (en) | 2010-05-17 | 2015-01-13 | Fujitsu Semiconductor Limited | Semiconductor device |
US9472482B2 (en) | 2010-05-17 | 2016-10-18 | Socionext Inc. | Semiconductor device |
WO2017179264A1 (ja) * | 2016-04-15 | 2017-10-19 | オムロン株式会社 | 半導体装置の放熱構造 |
JP2017191903A (ja) * | 2016-04-15 | 2017-10-19 | オムロン株式会社 | 半導体装置の放熱構造 |
EP3327768A4 (en) * | 2016-04-15 | 2019-05-01 | Omron Corporation | HEAT DISTRIBUTION STRUCTURE AND SEMICONDUCTOR ELEMENT |
US10304754B2 (en) | 2016-04-15 | 2019-05-28 | Omron Corporation | Heat dissipation structure of semiconductor device |
CN115954274A (zh) * | 2021-10-06 | 2023-04-11 | 星科金朋私人有限公司 | 具有开窗式散热器的封装 |
US20230118190A1 (en) * | 2021-10-06 | 2023-04-20 | STATS ChipPAC Pte. Ltd. | Package with Windowed Heat Spreader |
US11830785B2 (en) * | 2021-10-06 | 2023-11-28 | STATS ChipPAC Pte. Ltd. | Package with windowed heat spreader |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3196762B2 (ja) | 半導体チップ冷却構造 | |
TWI549204B (zh) | Manufacturing method of semiconductor device | |
JP2010103244A (ja) | 半導体装置及びその製造方法 | |
JP6197319B2 (ja) | 半導体素子の実装方法 | |
US7833831B2 (en) | Method of manufacturing an electronic component and an electronic device | |
JP5897584B2 (ja) | 半導体装置における鉛フリー構造 | |
JP3180800B2 (ja) | 半導体装置及びその製造方法 | |
JPH06260532A (ja) | フリップチップの接続構造 | |
JP6492768B2 (ja) | 電子装置及びはんだ実装方法 | |
JP4978054B2 (ja) | 半導体装置及びその製造方法並びに回路基板装置 | |
KR20020044577A (ko) | 개선된 플립-칩 결합 패키지 | |
JP2007243106A (ja) | 半導体パッケージ構造 | |
JP2007258448A (ja) | 半導体装置 | |
JP2009105209A (ja) | 電子装置及びその製造方法 | |
JP2006100385A (ja) | 半導体装置 | |
JP2011108814A (ja) | 面実装電子部品の接合方法及び電子装置 | |
JP2005340448A (ja) | 半導体装置及びその製造方法、回路基板並びに電子機器 | |
JPH10112515A (ja) | ボールグリッドアレイ半導体装置及びその製造方法 | |
JP2010123676A (ja) | 半導体装置の製造方法、半導体装置 | |
JP2008130992A (ja) | 実装構造体とその製造方法および半導体装置とその製造方法 | |
JP2016162813A (ja) | プリント基板及びハンダ付け方法 | |
JP2008098328A (ja) | 電子部品の表面実装構造 | |
TW201003864A (en) | Chip package structure | |
JP5104149B2 (ja) | 半導体装置およびその製造方法 | |
JP2000164774A (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080818 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20101101 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20101101 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20101201 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110119 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110125 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20111004 |