TWI549204B - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
TWI549204B
TWI549204B TW099126510A TW99126510A TWI549204B TW I549204 B TWI549204 B TW I549204B TW 099126510 A TW099126510 A TW 099126510A TW 99126510 A TW99126510 A TW 99126510A TW I549204 B TWI549204 B TW I549204B
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TW
Taiwan
Prior art keywords
solder
flip
semiconductor wafer
pad
wiring substrate
Prior art date
Application number
TW099126510A
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English (en)
Other versions
TW201106434A (en
Inventor
Kazuyuki Nakagawa
Shinji Baba
Satoshi Yamada
Takashi Karashima
Original Assignee
Renesas Electronics Corp
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Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of TW201106434A publication Critical patent/TW201106434A/zh
Application granted granted Critical
Publication of TWI549204B publication Critical patent/TWI549204B/zh

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0415—Small preforms other than balls, e.g. discs, cylinders or pillars
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps

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Description

半導體裝置之製造方法
本發明涉及一種半導體裝置之製造方法。特別涉及一種適用於提高半導體晶片倒裝連接在佈線基板上而形成之半導體裝置之可靠性有效之技術。
例如，在專利文獻1中公開了以下發明內容：在球陣列封裝(BGA：Ball Grid Array)型半導體裝置中，基板之電極墊由銅(Cu)形成，為在銅之表面施加了鍍鎳及鍍金之結構及其組裝之技術。
[先前技術文獻] [專利文獻] [專利文獻1]
日本特開2002-26073號公報
作為多引腳半導體封裝體之一例，被稱為BGA之半導體裝置已為眾所周知。為了使BGA之信號之傳送速度更加高速化，在多引腳高散熱封裝體中，以倒裝連接之方式將半導體晶片搭載於佈線基板(也稱為BGA基板)上之封裝技術已廣為人知。
本案申請發明人對在倒裝晶片BGA之組裝中所用佈線基板之端子(如焊盤等電極墊)之表面處理進行了研究，結果發現了以下問題。
被稱為BGA基板等之佈線基板之端子之表面處理，一般較多地採用化學鍍鎳-金處理。這是因為：通過採用化學鍍，便能夠解決採用電解電鍍時所產生之問題。
也就是說，在對如倒裝晶片BGA那樣多引腳且設有高密度佈線之佈線基板採用電解電鍍之情況下，必須設置鍍層引線。由於鍍層引線之影響，存在如下問題：佈線基板中佈線之設計自由度下降之問題以及傳送路徑信號品質惡化之問題。
但是，這些問題都是電解電鍍所特有之問題，通過採用化學鍍便無需鍍層引線，因此大多情況下都採用化學鍍。也就是說，由於採用化學鍍便可以省去鍍層引線，所以可提高佈線設計之自由度以及消除因鍍層引線造成之傳送路徑信號品質惡化之問題。
但是，另一方面，由於化學鍍鎳金之耐衝擊性不好，結果又出現了如下問題：在佈線基板之焊球搭載用焊盤與焊球之接合部之介面處很容易遭到破壞(斷裂)。這是因為，在進行化學鍍鎳金時，一般都要混合上磷(P)，但是在化學鍍鎳金過程中會在磷濃縮層產生微小空洞而變脆，這是造成耐衝擊性不良之主要原因。
此外，在上述專利文獻1上述之BGA型半導體裝置之組裝過程中，對佈線基板之焊盤(電極墊)之表面也進行鍍鎳-金處理，所以就會產生焊盤和焊球之接合部耐衝擊性惡化之問題。
為解決上述課題而進行了本發明研究。目的在於：提供一種可提高倒裝連接有半導體晶片之半導體裝置之可靠性之技術。
本發明之另一個目的在於：提供一種可提高倒裝連接有半導體晶片之半導體裝置之品質穩定性之技術。
本發明之上述內容及上述內容以外之目的和新特徵在本說明書之描述及圖式簡單說明中寫明。
下面簡要說明關於本專利申請書中所公開之發明中具有代表性實施方式之概要。
也就是說，本發明涉及一種半導體裝置之製造方法，上述半導體裝置係一種半導體晶片倒裝焊接連接於具有上表面和下表面之佈線基板之上述上表面側，並在上述佈線基板之上述下表面側具有可與安裝基板連接之焊球者，其中上述下表面位於上述上表面之相反側。上述半導體裝置之製造方法包括：步驟a，其係進行上述焊接連接將上述半導體晶片倒裝連接至上述佈線基板之上述上表面；在對上述半導體晶片進行上述焊接連接時，在連接上述焊球之上述佈線基板之上述下表面側之焊盤表面形成有預塗焊料，其中，上述焊盤以銅為主要成分。
本發明涉及一種半導體裝置之製造方法，上述半導體裝置係一種半導體晶片倒裝焊接連接於具有上表面和下表面之佈線基板之上述上表面側，並在上述佈線基板之上述下表面側具有可與安裝基板連接之焊球者，其中上述下表面位於上述上邊面之相反側。上述半導體裝置之製造方法包括以下步驟：步驟a，將焊膏或焊球配置於上述佈線基板之上述上表面側之複數個倒裝用電極，進而將焊膏塗敷於上述佈線基板之上述下表面側之複數個焊盤；步驟b，在上述步驟a之後，藉由回流將上述上表面側之上述焊膏或焊球和上述下表面側之上述焊膏熔化，而於上述複數個焊盤之表面上形成預塗焊料；步驟c，將上述半導體晶片之主面和上述佈線基板之上述上表面相對向配置：步驟d，在上述步驟c之後，在上述預塗焊料已形成在上述佈線基板之上述下表面側之上述複數個焊盤表面之狀態下，以第一頭構件對上述半導體晶片背面進行加熱，進而以第二頭構件對上述佈線基板之上述下表面進行加熱，而對上述半導體晶片進行上述焊接連接至上述佈線基板。
下面簡要說明關於本專利申請書中所公開之發明中根據具有代表性之實施方式所得到之效果。
即，在倒裝連接型半導體裝置之組裝過程中，能夠提高焊盤和焊球連接部之耐衝擊性，從而可提高半導體裝置之可靠性。
通過在突起連接部採用球架法(ball mounting method)，可提高半導體裝置之品質穩定性。
在以下實施方式中，除了需要特別說明以外，對具有同一或同樣之部分原則上不進行重複說明。
以下實施方式中，為了便於敘述，在必要時將幾個部分或將實施方式分割來說明，除了需要特別說明的以外，這些都不是彼此獨立且無關係的，而係與其他一部分或者全部之變形例、詳細內容及補充說明等相互關聯的。
另外，在以下實施方式中提及要素數等(包括個數、數值、量、範圍等)時，除了特別說明及原理上已經明確限定了特定之數量等除外，上述之特定數並非指固定之數量，而係可大於等於該特定數或可小於等於該特定數。
而且，在以下實施方式中，除了特別說明及原理上已經明確了是必要時除外，上述之構成要素(包括要素步驟等)也並非必須之要素。
在實施形態等敍述上，對於構成要素方面之敍述等方面，除了特別說明及從前後文之敍述上來看已經明確了並非如此等除外，在「由A構成」、「由A形成」、「具有A」、「包括A」等表述還指主要構成要素除了A以外還有其他主要要素。同樣地，對於構成要素等形狀及位置關係之敍述方面，除了特別說明的及原理上已經明確了並非如此等除外，實際上還包括與該形狀相近及類似的。同理，在數值及範圍的敍述方面也一樣。
以下根據附圖詳細說明本發明之實施方式。為了說明實施方式之所有圖中，原則上對具有同一功能之構件採用同一符號，省略掉重複之說明。
(實施方式)
圖1係對本發明實施方式中半導體裝置構造之一例進行部分剖切後之立體圖。圖2係圖1所示之半導體裝置構造之一例之剖面圖。圖3係圖1上述之半導體裝置之組裝步驟之一例之製造流程圖。圖4係在圖1所示之半導體裝置之組裝過程中所用之佈線基板之構造之一例之剖面圖。圖5係將圖4中A部之構造之一例之部分放大後之剖面圖。圖6係在圖1所示之半導體裝置之組裝過程中所用之佈線基板之預塗焊料之形成方法之一例之剖面圖。圖7係圖6所示之預塗焊料之形成方法之詳細一例之部分剖面圖。圖8係在圖1所示之半導體裝置之組裝過程中，倒裝連接步驟之一例之部分剖面圖。圖9係在圖1所示之半導體裝置之組裝過程中，植球步驟之一例之部分剖面圖。圖10係在圖1所示之半導體裝置之組裝過程中，所用之佈線基板之第1變形例中預塗焊料之形成方法之部分剖面圖。圖11係在圖1所示之半導體裝置之組裝過程中，所用之佈線基板之第2變形例中預塗焊料之形成方法之部分剖面圖。圖12係在圖1所示之半導體裝置之組裝過程中，第3變形例中倒裝連接步驟之部分剖面圖。
圖1及圖2所示之本實施方式之半導體裝置，係一種半導體晶片1以倒裝安裝之方式被焊接連接在佈線基板2之上表面2a上而形成之半導體封裝體。在本實施方式中，以BGA9作為上述半導體裝置之一例進行說明，上述BGA9由複數個外部端子即焊球5以柵狀設在佈線基板2之下表面2b上而形成。
以下對BGA9之詳細結構進行說明。BGA9具有佈線基板(也稱為BGA基板)2、半導體晶片1以及作為外部端子之焊球5。其中，佈線基板2具有：上表面2a、圖5所示之形成在上表面2a上複數個倒裝用電極2c、位於上表面2a相反側之下表面2b以及形成在下表面2b上之複數個焊盤2j；半導體晶片1具有主面1a及形成在主面1a上之複數個電極墊1c，且被倒裝連接在佈線基板2之上表面2a上；複數個外部端子即焊球5分別設置在佈線基板2之下表面2b之複數個焊盤2j上。
也就是說，BGA9之結構為半導體晶片1倒裝安裝在佈線基板2上之倒裝連接結構。在上述半導體晶片1之主面1a和佈線基板2之上表面2a相向之狀態下將半導體晶片1搭載於佈線基板2上。此時，半導體晶片1通過焊接連接與佈線基板2電性連接，通過複數個焊料凸塊8倒裝連接。
此外，在位於佈線基板2和半導體晶片1之間之倒裝連接部及其周圍填充有底部填充樹脂6，以固定和保護倒裝連接部。
在佈線基板2之上表面2a之周緣部安裝有加強環(Stiffener Ring)7，上述加強環7呈包圍半導體晶片1之狀態。加強環7利用環狀膠帶7a粘接在佈線基板2上。在加強環7之上部設有散熱片4。散熱片4通過半導體晶片1上之散熱樹脂13和環/散熱片4之間之粘接材(例如膠帶材)7b接合在加強環7及半導體晶片1之背面1b上。
由此，從半導體晶片1散發出之熱便經過散熱樹脂13傳遞給散熱片4，再從散熱片4散發到外部，同時，還經焊料凸塊8並通過佈線基板2從焊球5傳給安裝基板。而且，熱還從散熱片4經粘接材7b和加強環7傳給佈線基板2，再經過佈線基板2從焊球5傳給安裝基板而散發出去。
如圖5所示，佈線基板2具有：基材層即核心層2h、形成在核心層2h上下之堆焊(build-up)層2f、形成在堆焊層2f表面一側之面(佈線基板2之上表面2a)上之複數個倒裝用電極2c以及形成在堆焊層2f背面一側之面(佈線基板2之下表面2b)上之複數個焊盤2j。
此外，在各個倒裝用電極2c周圍及複數個焊盤2j周圍形成有作為絕緣膜之阻焊膜2g。
如圖5所示，上表面2a一側之倒裝用電極2c和與上述倒裝用電極2c相對應之下表面2b一側之焊盤2j，經由形成在核心層2c上之通孔佈線2d、形成在堆焊層2f上之導通孔2i及內部佈線2e電性連接。此外，填孔樹脂2k填充在通孔佈線2d內。
在這裏，半導體晶片1例如由矽形成。底部填充樹脂6例如為環氧系列樹脂。加強環7和散熱片4等由導熱率較高之金屬形成，而且，倒裝連接之焊料凸塊8及作為外部端子之焊球5由無鉛焊料等焊料材形成，例如由錫-銀-銅系列無鉛焊料形成。
佈線基板2之倒裝用電極2c、導通孔2i、內部佈線2e以及通孔佈線2d等，例如由純銅或者銅裏添加了少量(不超過1%)鋁、矽(Si)等雜質之銅合金形成。
此外，在本實施方式之BGA9中，在佈線基板2之上表面2a一側之複數個倒裝用電極2c之各個表面、下表面2b一側之複數個焊盤2j之各個表面，都沒形成有化學鎳金鍍層等化學鍍層或電解鍍層。也就是說，在未對複數個倒裝用電極2c之各個表面進行化學鍍鎳金等化學鍍和電解電鍍等之狀態下形成了複數個焊料凸塊8。另一方面，在未對複數個焊盤2j之各個表面進行化學鍍鎳金等化學鍍和電解電鍍等之狀態下形成了複數個焊球5。
接下來，按照圖3所示之組裝步驟對本實施方式中BGA(半導體裝置)9之製造方法進行說明。本實施方式中BGA9之製造方法，係一種半導體晶片1倒裝焊接連接在具有上表面2a和下表面2b之佈線基板2之上表面2a一側，且具有能夠在佈線基板2之下表面2b一側與安裝基板連接之焊球5之BGA9之製造方法，其中，上述下表面2b位於上述上表面2a之相反側。
首先，進行圖3所示之步驟S1，即準備基板之步驟。在這裏係備好圖4及圖5所示之佈線基板(也稱作BGA基板或者封裝基板等)2。如圖5所示，佈線基板2係由焊料凸塊2m分別連接在其上表面2a上之複數個倒裝用電極2c之每個倒裝用電極2c上，且預塗焊料3形成在下表面2b上之複數個焊盤2j之每個焊盤2j上。
下面參考圖6及圖7，說明上表面2a一側之焊料凸塊2m及下表面2b一側之預塗焊料3之形成方法。
首先，進行圖6上述之步驟S11，即形成開口之步驟。這裏，在覆蓋上表面2a一側之複數個倒裝用電極2c之各個倒裝用電極2c之阻焊膜2g上形成開口，且在覆蓋下表面2b一側之複數個焊盤2j之各個焊盤2j之阻焊膜2g上形成開口。這些開口例如通過光蝕刻等處理形成。由此可使複數個倒裝用電極2c在佈線基板2之上表面2a一側露出，同時也可使複數個焊盤2j在下表面2b一側露出。
複數個倒裝用電極2c和焊盤2j例如由純銅或者銅裏添加了少量(不超過1%)鋁、矽(Si)等雜質之銅合金形成。例如可以對複數個倒裝用電極2c和焊盤2j進行鍍錫處理或者防銹處理。通過進行上述鍍錫處理或者防銹處理，便可防止複數個倒裝用電極2c和焊盤2j氧化。
之後，進行圖6所示之步驟S12，即進行焊膏印刷/焊膏印刷。這裏，通過上述焊膏印刷分別在複數個倒裝用電極2c上塗敷焊膏2n，且分別對複數個焊盤2j上塗敷焊膏3a。此外，如圖7之焊膏印刷步驟即步驟S12所示，在往各個焊盤2j上印刷焊膏3a時，將焊接印刷掩膜10之開口部10a之位置與焊盤2j之位置對齊設置，並以將焊膏3a填埋在上述開口部10a之方式進行印刷。此時，為保證所形成之預塗焊料3之高度不會過高，優選使用焊接印刷掩膜10之開口部10a較焊盤2j小之阻止膜。
之後，進行如圖6所示之步驟S13和圖7所示之步驟S13，即進行回流/助焊劑清洗。此時，利用回流使各焊膏2n和各焊膏3a熔化而在各個倒裝用電極2c上形成焊料凸塊2m，並且在各個焊盤2j上形成預塗焊料3。在各個焊盤2j中，由於阻焊膜2g之開口寬大，所以當焊膏3a由於回流而熔化時，阻焊膜2g之形狀就會變成帶R形，這就成為預塗焊料3。也就是說，由於純銅或者銅裏添加了少量(不超過1%)鋁、矽(Si)等雜質之銅合金之焊盤2j和焊料之相互熱擴散，而在焊盤2j上形成了錫銅系列或者錫銀銅系列合金層。
此外，當在各個焊盤2j上形成預塗焊料3時，使預塗焊料3形成為在其厚度方向上比覆蓋焊盤2j之周緣部之阻焊膜2g內凹之狀態。
由此，在以後之倒裝連接步驟中，當由第二頭構件吸附支撐佈線基板2時，便可防止預塗焊料3與上述第二頭構件接觸，從而能夠阻止第二頭構件被沾污，並且能夠防止其他預塗焊料3之汙物附著到預塗焊料3表面上。結果，可抑制BGA9之品質下降。
如上上述，在佈線基板2之各個倒裝用電極2c上形成了焊料凸塊2m，並且在各個焊盤2j上形成了預塗焊料3。進行完回流後，進行助焊劑之清洗。
之後，進行圖3所示之步驟S2，即進行倒裝連接。也就是說，如圖8所示，利用倒裝連接將半導體晶片1搭載於佈線基板2上。這裏，將半導體晶片1倒裝焊接連接在佈線基板2之上表面2a上。
首先，準備佈線基板2，在上述佈線基板2之下表面2b一側之複數個焊盤2j之表面上形成有預塗焊料3，其中，上述複數個焊盤2j由純銅或者銅裏添加了少量(不超過1%)鋁、矽(Si)等雜質之銅合金形成。
另一方面，準備半導體晶片1，並利用第一頭構件即晶片一側之頭11真空吸附上述半導體晶片1之背面1b，其中，上述半導體晶片1之主面1a上之複數個電極墊1c(參照圖2)連接有焊料凸塊1d。由於在晶片一側之頭11上設有加熱構件(例如加熱器等)，所以如圖8所示之晶片加熱即步驟S21所示，半導體晶片1在被真空吸附之狀態下由晶片一側之頭11加熱。此時加熱溫度例如在200-350℃左右。
此外，連接在半導體晶片1之主面1a上之複數個電極墊1c(參照圖2)上之複數個焊料凸塊1d例如由錫-銀-銅形成。而且，即使在倒裝連接後之熱處理步驟(底部填充樹脂6之固化步驟、安裝上散熱片4後之烘烤步驟等)中，也可通過對佈線基板2之下表面2b之焊盤2j上形成預塗焊料3，以抑制焊盤2j被氧化。
之後，進行圖8所示之步驟S22，即對基板加熱。此時，由第二頭構件即基板側頭(也稱為加熱台或者加熱塊)12利用真空吸附來支撐佈線基板2之下表面2b。由於在基板側頭12也設有加熱構件(例如加熱器等)，所以佈線基板2在被真空吸附之狀態下由基板側頭12加熱。此時之加熱溫度例如為150-250℃左右。
在上述狀態下(使由基板側頭12真空吸附之佈線基板2之上表面2a和由晶片側頭11真空吸附之半導體晶片1之主面1a相向之狀態下)進行倒裝連接即圖8之步驟S23。此外，在進行倒裝連接時，在上述佈線基板2之下表面2b一側之複數個焊盤2j之表面上形成預塗焊料3，其中，上述複數個焊盤2j由純銅或者銅裏添加了少量(不超過1%)鋁、矽(Si)等雜質之銅合金形成。上述預塗焊料3優選無鉛焊料，例如錫-銅系列焊料。
例如與63Sn/37Pb系列之共晶焊料塗層相比，通過採用錫-銅系列無鉛焊料作為形成在焊盤2j之表面上之預塗焊料3之焊料，那麼，即使在倒裝連接等熱處理步驟中對預塗焊料3施加了熱歷史，預塗焊料3也難以熔化。
在利用回流熔化預塗焊料3時，也需要事先使預塗焊料3形成為高度不超出阻焊膜2g之高度。通過使預塗焊料3之高度不超出阻焊膜2g之高度，可防止在預塗焊料3熔化時，由此預塗焊料3之焊料異物附著在基板側頭12上，從而能夠防止基板側頭12被沾污。
預塗焊料3形成在佈線基板2之下表面2b之複數個焊盤2j之表面上，由此，可防止在倒裝連接時之熱歷史施加在焊盤2j上時，焊盤2j出現氧化而導致隨後之焊球形成步驟中焊球5無法附著。也就是說，通過在各個焊盤2j表面上形成預塗焊料3，便能夠在隨後之焊球形成步驟中將焊球5連接在焊盤2j上。
在進行倒裝連接時，通過晶片側頭11對半導體晶片1加熱之溫度(如為200-350℃)比通過基板側頭12對佈線基板2加熱之溫度(如為150-250℃)高。
如上上述，通過使由基板側頭12進行之加熱溫度低於由晶片側頭11進行之加熱溫度，便能夠減少帶給佈線基板2之熱應力，從而能夠減少對佈線基板2造成之損傷。
在倒裝連接時，在佈線基板2被真空吸附在已加熱之基板側頭12上之狀態下，從半導體晶片1之背面1b一側(上側)推壓由已被加熱之晶片側頭11真空吸附之半導體晶片1進行倒裝連接。由此，便可在各個平坦性一致之狀態下，使設在半導體晶片1上之複數個焊料凸塊1d和連接在佈線基板2之倒裝用電極2c之複數個焊料凸塊2m進行倒裝連接。
結果可提高倒裝連接部之連接可靠性。
此外，在倒裝連接時對佈線基板2之加熱過程中，也採用錫-銅系列無鉛焊料作為預塗焊料3之焊料，因此，即使倒裝連接時之熱歷史被施加在預塗焊料3上，預塗焊料3也難以熔化。
因此就能夠抑制自預塗焊料3產生焊料異物，從而能夠抑制焊料異物附著在基板側頭12上。結果，能夠降低焊料異物吸附在隨後搬送來之下一個佈線基板2上，並且能夠抑制佈線基板2之平坦性惡化及基板側頭12之吸附性惡化。
最後，如圖8之步驟S23所示，將半導體晶片1上之複數個焊料凸塊1d和與其相對應之佈線基板2之複數個焊料凸塊2m分別連接至此，便完成了倒裝連接。
完成倒裝連接後，進行底部填充注入即圖3所示之步驟S3。這裏，將底部填充樹脂6填充在佈線基板2和半導體晶片1之間，並在半導體晶片1之側面周圍塗敷底部填充樹脂6。由此可使底部填充樹脂6設置在倒裝連接部周圍，倒裝連接部便得到保護。底部填充樹脂6填充完之後，再進行底部填充樹脂6之固化處理。
接下來，進行圖3所示之步驟S4即搭載散熱片。首先，如圖2所示，以包圍半導體晶片1之方式，經由環狀膠帶7a將加強環7貼在佈線基板2之上表面2a之周緣部。之後，將散熱樹脂13塗敷在半導體晶片1之背面1b，再經由上述散熱樹脂13將散熱片4安裝在半導體晶片1上。在加強環7和散熱片4之間裝有粘接材(例如膠帶材)7b。也就是說，散熱片4經由散熱樹脂13與半導體晶片1接觸，經由粘接材7b與加強環7接觸。結果，半導體晶片1成為在佈線基板2之上表面上被加強環7和散熱片4覆蓋之狀態。
配置好散熱片4後，對散熱樹脂13進行烘烤處理，以完成散熱片4之安裝。
此外，採用由錫-銀-銅等製成之無鉛焊料形成倒裝連接部之焊料凸塊1d及焊料凸塊2m，採用錫-銅系列無鉛焊料形成佈線基板2之下表面2b之焊盤2j上之預塗焊料3。
之後，進行植球即圖3所示之步驟S5。也就是說，對佈線基板2之下表面2b之焊盤2j上之預塗焊料3施加熱，將作為外部端子之複數個焊球5與佈線基板2之焊盤2j電性連接。
首先，如圖9之步驟S31所示，將焊膏5a印刷在佈線基板2之各個焊盤2j之預塗焊料3上。此時，也可以塗敷助溶劑來代替焊膏5a。之後，進行步驟S32所示之植球。在這裏，暫時將焊球5固定在焊膏5a上。之後，進行步驟S33所示之回流/清洗處理。首先，通過回流對焊球5和焊膏5a加熱並使其熔化。之後，進行清洗，並通過焊接連接將焊球5與複數個焊盤2j電性連接。
此外，用於焊球5之焊料中，如為含鉛焊料之情況下，可為63Sn37Pb等；為無鉛焊料之情況下，可為Sn3Ag0.5Cu等。
通過採用錫-銀-銅等製成之無鉛焊料形成倒裝連接部之焊料凸塊1d及焊料凸塊2m，再採用錫-銅系列無鉛焊料形成佈線基板2之下表面2b之焊盤2j上之預塗焊料3，則即使連接焊球5時回流之熱歷史施加在焊料凸塊1d、焊料凸塊2m以及預塗焊料3上，結果也與以上述一樣，由於這些焊料之熔點很高，所以焊料凸塊1d、焊料凸塊2m以及預塗焊料3將難以熔化。
如上上述，便完成了圖1及圖2所示之BGA9之組裝。
在本實施方式之半導體裝置之製造方法中，通過倒裝連接將半導體晶片1進行焊接連接時，預塗焊料3形成在佈線基板2之下表面2b一側之焊盤2j之表面上，由於焊盤2j和作為外部端子之焊球5之連接便成為焊接連接。因此，可提高焊盤2j和焊球5連接部之耐衝擊性。也就是說，由於在焊盤2j和焊球5連接部例如通過化學鎳金鍍層等方式而不含磷(P)，所以將不產生富磷(P)層而導致出現微小空洞，從而能夠提高焊盤2j和焊球5連接部之耐衝擊性。
由此便可提高BGA9之可靠性。
此外，在佈線基板2之複數個焊盤2j表面上未形成有預塗焊料3之情況下，由於焊盤2j之純銅或者銅裏添加了少量(不超過1%)鋁、矽等雜質之銅合金露出來了，所以在植球步驟之前還有各種施加熱歷史之步驟，雖然也存在因焊盤2j表面氧化而導致在植球步驟中無法將焊球5連接在焊盤2j上之可能性。但是在本實施方式中BGA9之安裝過程中，由於在焊盤2j表面已形成有預塗焊料3，所以能夠抑制焊盤2j表面被氧化，從而能夠在植球步驟中將焊球5連接在焊盤2j上。
在進行倒裝連接之佈線基板2之倒裝用電極2c和半導體晶片1之焊料凸塊1d之連接過程中，由於無需經由鎳金鍍層等就能進行焊接連接，所以可提高倒裝用電極2c和焊料凸塊1d連接部之耐衝擊性。
由於不使用電解電鍍，所以無需在佈線基板2上設置鍍層引線，因而能夠提高佈線設計之自由度，並且能夠解決鍍層引線引起之傳送路徑信號品質惡化之問題。
形成在佈線基板2之焊盤2j之表面上之預塗焊料3採用無鉛焊料，由於無鉛焊料熔點高，所以即使在進行烘烤處理、固化處理等過程中在預塗焊料3上施加了熱歷史，上述預塗焊料3也難以熔化。而且，也不會在倒裝連接時沾汙基板側頭12(台)，從而能夠維持BGA9之品質。
而且，通過採用無鉛焊料即錫-銅系列焊料作預塗焊料3之焊料，那麼，不管作為外部端子而被連接之焊球5係共晶(有鉛)焊料還是無鉛焊料，都可提高焊球5之連接強度。結果，可應用於共晶(有鉛)焊料及無鉛焊料，從而能夠謀求佈線基板2之共通化。由此，可降低佈線基板2之成本，即可降低BGA9之成本。
此外，也可用化學鍍鎳-鈀-金來代替預塗焊料3之技術，但由於鍍液之管理/膜厚-膜質之管理都很難，而且很難應用於共晶(含鉛)/無鉛二者之表面技術，所以，如本實施方式上述之易用於製造之焊接預塗技術是最為有效的。
接下來，對本實施方式之變形例進行說明。
圖10所示之第1變形例之內容為：在進行了佈線基板2之倒裝連接之倒裝用電極2c上形成焊料凸塊2m時，採用了搭載焊球2p而不是搭載焊料膏2n之球架法。
首先，進行圖10所示之步驟S41即形成開口。也就是說，在佈線基板2之上表面2a一側之阻焊膜2g上形成開口，及在下表面2b一側之阻焊膜2g上形成開口，且使上表面2a一側之複數個倒裝用電極2c和下表面2b一側之複數個焊盤2j露出。
之後，進行圖10所示之步驟S42，即進行焊膏印刷/搭載焊球。焊膏2n可為助焊劑。首先，在佈線基板2之上表面2a一側，通過印刷將焊膏2n塗敷在複數個倒裝用電極2c之各個倒裝用電極2c上，塗敷後，再將焊球2p搭載在(配置在)各個焊膏2n上。另一方面，在佈線基板2之下表面2b一側，通過印刷將焊膏3a塗敷在複數個焊盤2j之各個焊盤2j上。其中，焊膏3a可為助焊劑。
之後，進行如圖10所示之步驟S43，即進行回流/助焊劑清洗。這裏，利用回流分別熔化焊膏2n和焊球2p、焊膏3a，並在各個倒裝用電極2c上形成焊料凸塊2m，同時在各個焊盤2j之表面上形成預塗焊料3。在各個焊盤2j中，由於阻焊膜2g之開口寬大，所以當焊膏3a由於回流而熔化時，阻焊膜2g之形狀就會變為帶R形，因而成為預塗焊料3。也就是說，由於純銅或者銅裏添加了少量(不超過1%)鋁、矽等雜質之銅合金之焊盤2j和焊料之相互熱擴散作用，而在各焊盤2j上形成了錫銅系列合金層。
此外，當在各個焊盤2j上形成預塗焊料3時，使預塗焊料3形成為在其厚度方向上比覆蓋焊盤2j之周緣部之阻焊膜2g內凹之狀態。
在回流之後，進行助焊劑清洗，完成助焊劑清洗後，再進行倒裝連接。
如上上述，通過採用搭載焊球2p來形成突起(球)連接部(焊料凸塊2m)之球架法，便能夠謀求窄間隙且多突起之連接品質之穩定，從而能夠謀求倒裝連接型BGA(半導體裝置)9之品質穩定。
通過在倒裝連接部採用球架法，便能夠使球之高度均勻，從而能夠提高半導體晶片1之平坦性。而且，解決了膏印刷時下垂(sagging)之問題，從而使突起之高度形成得均勻且很高。
圖11所示之第2變形例係採用與對上述佈線基板2之球架法相同之球架法在半導體晶片1上形成突起。也就是說，即使在晶片一側採用球架法和而在基板一側採用印刷法，也能夠改善突起之平坦性，從而可提高接合之穩定性。
具體地說就是，首先，進行圖11所示之步驟S51，即搭載焊球。這裏，利用球架法在半導體晶片1之主面1a上設置複數個焊料凸塊(焊球)1d。
接著，進行圖11所示之步驟S52，即進行回流。也就是說，以超過突起熔點之溫度進行回流，以此來進行圖11所示之步驟S53即進行倒裝連接。
此外，晶片一側/基板一側雙方可以組合採用球架法。
之後，如圖9之步驟S31所示，將焊膏5a印刷在佈線基板2之各個焊盤2j之預塗焊料3上。此外，可以塗敷助焊劑用以代替焊膏5a。進一步進行步驟S32所示之植球。這裏，暫時將焊球5固定在焊膏5a上。
之後，進行步驟S33所示之回流/清洗。首先，利用回流對焊球5和焊膏5a加熱並使其熔化。然後在進行清洗後，進行焊接連接將焊球5連接在複數個焊盤2j上以完成電性連接。
如上上述，在上述第2變形例中也可提高窄間隙且多突起之連接品質之穩定性，從而能夠謀求倒裝連接型BGA(半導體裝置)9品質之穩定。還能夠進一步使球之高度均勻一致，從而可提高半導體晶片1之平坦性。
接下來，圖12所示之第3變形例為倒裝連接方法之變形例。首先，進行圖12所示之步驟S61即暫時固定突起。這裏，將助焊劑1e轉印到設在半導體晶片1之主面1a之複數個焊料凸塊1d上，轉印後，再將連接有利用顫動等壓印之焊料凸塊2q之狀態下之佈線基板2和半導體晶片1倒裝連接在各個倒裝用電極2c上。此時，首先，對連接在佈線基板2之各個倒裝用電極2c之複數個焊料凸塊2q和半導體晶片1之複數個焊料凸塊1d暫時進行固定。
之後，進行圖12所示之步驟S62，即回流。也就是說，以超過突起熔點之溫度進行回流，由此進行倒裝連接即圖12所示之步驟S63。
此時，回流後有可能需要對佈線基板2和半導體晶片1之間隙部分進行助焊劑清洗。但是如果使用無清洗型助焊劑或者利用等離子體處理等除去助焊劑時則可以略去清洗步驟。
如上上述，可以採取不用頭構件推壓半導體晶片1和佈線基板2之方法進行倒裝連接。此時，通過在佈線基板2之下表面2b一側之焊盤2j形成預塗焊料3便可防止焊盤2j被氧化。
以上按照實施方式具體地說明瞭本案發明人所作之發明，但是本發明並不受到上述實施方式之限定，在不超出其要旨範圍下能夠進行種種變更，在此無需贅言。
例如，在上述實施方式中，以安裝了加強環7之BGA9作為半導體裝置為例進行了說明，但是也可以不設加強環7。但此時，散熱片4通過散熱樹脂13僅與半導體晶片1之背面1b接合。
[產業上之可利性]
本發明可廣泛應用於倒裝連接型電子器件。
1．．．半導體晶片
1a．．．主面
1b．．．背面
1c．．．電極墊
1d．．．焊料凸塊
1e．．．助焊劑
2．．．佈線基板
2a．．．上表面
2b．．．下表面
2c．．．倒裝用電極
2d．．．通孔佈線
2e．．．內部佈線
2f．．．堆焊層
2g．．．阻焊膜(絕緣膜)
2h．．．核心層
2i．．．導通孔
2j．．．焊盤
2k．．．填孔樹脂
2m．．．焊料凸塊
2n．．．焊膏
2p．．．焊球
2q．．．焊料凸塊
3．．．預塗焊料
3a．．．焊膏
4．．．散熱片
5．．．焊球(外部端子)
5a．．．焊膏
6．．．底部填充樹脂
7．．．加強環
7a．．．環狀膠帶
7b．．．粘接材
8．．．焊料凸塊
9．．．BGA(半導體裝置)
10．．．焊接印刷掩膜
10a．．．開口部
11．．．晶片側頭(第一頭構件)
12．．．基板側頭(第二頭構件)
13．．．散熱樹脂
圖1係對本發明實施方式中半導體裝置構造之一例進行部分剖切後之透視立體圖。
圖2係圖1中半導體裝置構造之一例之剖面圖。
圖3係圖1中半導體裝置組裝步驟之一例之製造流程圖。
圖4係在圖1所示之半導體裝置組裝過程中所用之佈線基板之構造之一例之剖面圖。
圖5係將圖4中A部之構造之一例之部分放大後之剖面圖。
圖6係在圖1所示之半導體裝置組裝過程中所用之佈線基板之預塗焊料之形成方法之一例之剖面圖。
圖7係圖6之預塗焊料之形成方法之詳細一例之部分剖面圖。
圖8係在圖1所示之半導體裝置之組裝過程中，倒裝連接步驟之一例之部分剖面圖。
圖9係在圖1所示之半導體裝置之組裝過程中，植球步驟之一例之部分剖面圖。
圖10係在圖1所示之半導體裝置組裝過程中，所用之佈線基板之第1變形例中預塗焊料形成方法之部分剖面圖。
圖11係在圖1所示之半導體裝置之組裝過程中，所用之佈線基板之第2變形例中預塗焊料形成方法之部分剖面圖。
圖12係在圖1所示之半導體裝置之組裝過程中，第3變形例中倒裝連接步驟之部分剖面圖。
1．．．半導體晶片
1a．．．主面
1b．．．背面
1d．．．焊料凸塊
2．．．佈線基板
2a．．．上表面
2b．．．下表面
2c．．．倒裝用電極
2d．．．通孔佈線
2e．．．內部佈線
2f．．．堆焊層
2g．．．阻焊膜(絕緣膜)
2h．．．核心層
2i．．．導通孔
2j．．．焊盤
2k．．．填孔樹脂
2m．．．焊料凸塊
3．．．預塗焊料
8．．．焊料凸塊
11．．．晶片側頭(第一頭構件)
12．．．基板側頭(第二頭構件)

Claims (2)

  1. 一種半導體裝置之製造方法，其包含以下步驟：(a)準備佈線基板，其包含：上表面、形成於前述上表面之倒裝晶片用電極、前述上表面之相反側的下表面，形成於前述下表面之焊盤(land)、形成於前述焊盤之表面的預塗焊料、及覆蓋前述焊盤之周緣部之絕緣膜，其中上述焊盤係包含以銅為主要成份之材料，上述預塗焊料係錫銅系列或者錫銀銅系列之無鉛焊料，且上述預塗焊料係於其厚度方向上，較上述絕緣膜內凹；(b)於上述(a)步驟後，以包含主表面、形成於前述主表面之電極墊、連接於前述電極墊之凸塊、及前述主表面之相反側的背面之半導體晶片之前述主表面與上述佈線基板之上述上表面對向之方式，將前述半導體晶片搭載於上述佈線基板之上述上表面上，且將前述半導體晶片之前述凸塊與前述佈線基板之前述倒裝晶片用電極電性連接，其中上述(b)步驟中，以第一頭構件對上述半導體晶片之上述背面進行加熱，又以第二頭構件對上述佈線基板之上述下表面進行加熱，上述第一頭構件進行之上述半導體晶片之加熱溫度係 高於上述第二頭構件進行之上述佈線基板之加熱溫度；(c)於上述(b)步驟後，將焊球配置於上述佈線基板之上述焊盤上之上述預塗焊料，而加熱上述焊球，藉此將包含上述焊球之外部端子形成於上述焊盤之上述表面。
  2. 如請求項1之半導體裝置之製造方法，其中上述凸塊係包含錫銀銅之焊料凸塊。
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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8624323B2 (en) * 2011-05-31 2014-01-07 International Business Machines Corporation BEOL structures incorporating active devices and mechanical strength
JP2013030712A (ja) * 2011-07-29 2013-02-07 Toshiba Corp 半導体モジュールおよび半導体モジュールの製造方法
JP5800674B2 (ja) * 2011-10-25 2015-10-28 日本特殊陶業株式会社 配線基板及びその製造方法
US9881898B2 (en) * 2011-11-07 2018-01-30 Taiwan Semiconductor Manufacturing Co.,Ltd. System in package process flow
WO2013132953A1 (ja) * 2012-03-05 2013-09-12 株式会社村田製作所 接合方法、電子装置の製造方法、および電子部品
JP6021441B2 (ja) 2012-05-25 2016-11-09 ラピスセミコンダクタ株式会社 半導体装置
CN109637995B (zh) * 2013-09-03 2022-11-22 日月光半导体制造股份有限公司 基板结构、封装结构及其制造方法
US9282649B2 (en) * 2013-10-08 2016-03-08 Cisco Technology, Inc. Stand-off block
JP2015144188A (ja) * 2014-01-31 2015-08-06 株式会社東芝 半導体装置及びその製造方法
US9674940B2 (en) * 2014-08-14 2017-06-06 Samsung Electronics Co., Ltd. Electronic device and semiconductor package with thermally conductive via
CN104599978B (zh) * 2014-12-31 2017-08-01 广州兴森快捷电路科技有限公司 一种在倒装芯片基板上小间距之间制备高凸点锡球的制备方法
JP6513950B2 (ja) * 2015-01-07 2019-05-15 ナミックス株式会社 無洗浄フラックス、および半導体パッケージの製造方法
US10515884B2 (en) 2015-02-17 2019-12-24 Advanced Semiconductor Engineering, Inc. Substrate having a conductive structure within photo-sensitive resin
CN105895539B (zh) * 2016-06-08 2018-08-10 华进半导体封装先导技术研发中心有限公司 芯片倒装封装中间结构和倒装封装结构及倒装封装方法
CN106145026B (zh) * 2016-06-30 2018-03-27 清华大学 用于mems的气密性封装结构和封装方法
JP2019052355A (ja) 2017-09-15 2019-04-04 上村工業株式会社 電解Ｓｎ又はＳｎ合金めっき液及びＳｎ又はＳｎ合金めっき物の製造方法
CN108091621A (zh) * 2017-12-21 2018-05-29 乐健科技（珠海）有限公司 内嵌开关芯片的器件模组及其制作方法
CN112185928A (zh) * 2020-10-22 2021-01-05 上海艾为电子技术股份有限公司 一种芯片封装结构及其制备方法、封装芯片

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040235221A1 (en) * 2001-06-22 2004-11-25 Kazuyuki Taguchi Electronic device and method for manufacturing the same
US20080258300A1 (en) * 2007-04-13 2008-10-23 Shinko Electric Industries Co., Ltd. Wiring board manufacturing method, semiconductor device manufacturing method and wiring board

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002026073A (ja) 2000-07-07 2002-01-25 Hitachi Ltd 半導体装置およびその製造方法
JP2003258156A (ja) * 2002-03-05 2003-09-12 Ngk Spark Plug Co Ltd 配線基板
JP2005159102A (ja) * 2003-11-27 2005-06-16 Ngk Spark Plug Co Ltd 配線基板及びその製造方法
JP2005191122A (ja) * 2003-12-24 2005-07-14 Kyocera Corp 配線基板およびその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040235221A1 (en) * 2001-06-22 2004-11-25 Kazuyuki Taguchi Electronic device and method for manufacturing the same
US20080258300A1 (en) * 2007-04-13 2008-10-23 Shinko Electric Industries Co., Ltd. Wiring board manufacturing method, semiconductor device manufacturing method and wiring board

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