CN115954274A - 具有开窗式散热器的封装 - Google Patents

具有开窗式散热器的封装 Download PDF

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Publication number
CN115954274A
CN115954274A CN202211070549.9A CN202211070549A CN115954274A CN 115954274 A CN115954274 A CN 115954274A CN 202211070549 A CN202211070549 A CN 202211070549A CN 115954274 A CN115954274 A CN 115954274A
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Prior art keywords
package
substrate
semiconductor
stiffener
over
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CN202211070549.9A
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李泰根
金荣民
金用敏
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Publication of CN115954274A publication Critical patent/CN115954274A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

具有开窗式散热器的封装。一种半导体器件具有衬底和设置在衬底上方的第一半导体管芯。子封装也设置在衬底上方。加强件设置在围绕第一半导体管芯和子封装的衬底上方。散热器设置在加强件上方。散热器热耦合到第一半导体管芯。散热器具有子封装上方的开口。

Description

具有开窗式散热器的封装
技术领域
本发明总体上涉及半导体器件，并且更特别地涉及半导体器件和形成具有开窗式散热器的半导体器件的方法。
背景技术
半导体器件通常在现代电子产品中找到。半导体器件执行宽范围的功能，诸如信号处理、高速计算、发射和接收电磁信号、控制电子器件、将太阳光变换成电力以及为电视显示器创建可视图像。半导体器件在通信、电源转换、网络、计算机、娱乐和消费产品领域中找到。半导体器件也在军事应用、航空、汽车、工业控制器和办公设备中找到。
随着器件大小的减小并且以更高的频率操作，半导体部件的热生成成为更多的设计考虑因素。许多半导体封装包括连接到半导体管芯的散热器。散热器通过将热能分散到更大的表面积上来帮助消散来自半导体管芯的热量。散热器还通过允许经由散热器附接外部散热部件来改进热处理能力。
散热器通常是设置在半导体管芯或封装上方的单独部件。散热器通常形成围绕半导体封装的部件并在其上方延伸的外壳的部分。现有技术散热器的一个问题是外壳可以将热能截留在封装内，并且引起其它封围部件的热管理问题。因此，存在一种用于半导体封装的改进的散热器的需要。
附图说明
图1a-1c图示了具有由锯道分离的多个半导体管芯的半导体晶片；
图2a-2h图示了形成具有开窗式散热器的半导体封装；
图3图示了双面实施例；
图4a-4c图示了具有分隔加强件的实施例；
图5a-5c图示了适于具有不同高度的封装和半导体管芯的实施例；
图6a-6c图示了使用网格开口代替单一窗口的实施例；和
图7a和图7b图示了将封装集成到电子器件中。
具体实施方式
在以下描述中，参考各图，在一个或多个实施例中描述了本发明，其中相同的标号表示相同或相似的元件。虽然依据用于实现本发明目的的最佳模式描述了本发明，但是本领域技术人员将领会，本发明旨在覆盖如可能包括在由所附权利要求及其等价物所限定的本发明的精神和范围内的替代、修改和等价物，所述权利要求及其等价物由以下公开内容和附图所支持。如本文使用的术语“半导体管芯”指代单词的单数和复数形式二者，并且因此可以指代单个半导体器件和多个半导体器件二者。
通常使用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含有源和无源电子部件，它们电连接以形成功能电路。诸如晶体管和二极管之类的有源电子部件具有控制电流流动的能力。诸如电容器、电感器和电阻器之类的无源电部件在执行电路功能所必需的电压和电流之间创建关系。
后端制造指代将成品晶片切割或分割成个体半导体管芯，并封装半导体管芯以用于结构支撑、电互连和环境隔离。为了分割半导体管芯，沿着晶片的非功能区域（称为锯道或划线）对晶片进行刻痕和断裂。使用激光切割工具或锯片对晶片进行分割。在分割之后，个体半导体管芯被安装到封装衬底，该封装衬底包括用于与其他系统部件互连的引脚或接触焊盘。然后，在半导体管芯上方形成的接触焊盘连接到封装内的接触焊盘。电连接可以用导电层、凸块、柱形凸块、导电胶、接合线或其他合适的互连结构制成。密封剂或其他模制化合物沉积在封装上方，以提供物理支撑和电绝缘。然后将成品封装插入到电系统中，并且使半导体器件的功能性对其他系统部件可用。
图1a示出了具有基础衬底材料102的半导体晶片100，基础衬底材料102诸如是硅、锗、磷化铝、砷化铝、砷化镓、氮化镓、磷化铟、碳化硅或其它块状半导体材料。多个半导体管芯或部件104形成在如上所述由无源管芯间晶片区域或锯道106分离的晶片100上。锯道106提供切割区域以将半导体晶片100分割成个体半导体管芯104。在一个实施例中，半导体晶片100具有100-450毫米（mm）的宽度或直径。
图1b示出了半导体晶片100的一部分的横截面视图。每个半导体管芯104具有背面或非有源表面108和有源表面110，其包含模拟或数字电路，该模拟或数字电路被实现为在管芯内或上方形成的有源器件、无源器件、导电层和介电层，并且根据管芯的电设计和功能进行电互连。例如，电路可以包括形成在有源表面110内的一个或多个晶体管、二极管和其他电路元件，以实现模拟电路或数字电路，诸如数字信号处理器（DSP）、ASIC、MEMS、存储器或其他信号处理电路。半导体管芯104还可以包含用于RF信号处理的集成无源器件（IPD），诸如电感器、电容器和电阻器。半导体晶片100的背面108可以经历可选的背面研磨操作，该背面研磨操作具有机械研磨或蚀刻工艺，以移除基础材料102的一部分并减小半导体晶片100和半导体管芯104的厚度。
使用PVD、CVD、电解电镀、非电解电镀工艺或其他合适的金属沉积工艺在有源表面110上方形成导电层112。导电层112包括铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、银（Ag）或其他合适的导电材料的一个或多个层。导电层112作为电连接到有源表面110上的电路的接触焊盘来操作。
导电层112可以形成为与半导体管芯104的边缘相距第一距离并排设置的接触焊盘，如图1b中所示。替代地，导电层112可以形成为在多行中偏移的接触焊盘，使得第一行接触焊盘设置在距管芯边缘的第一距离，并且与第一行交替的第二行接触焊盘设置在距管芯边缘的第二距离。导电层112表示在半导体管芯104上方形成的最后导电层，其具有用于后续电互连到更大系统的接触焊盘。然而，在有源表面110上的实际半导体器件和用于信号路由的接触焊盘112之间形成的一个或多个中间导电和绝缘层可以存在。
使用蒸镀、电解电镀、非电解电镀、落球或丝网印刷工艺在导电层112上方沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料和具有可选助焊剂溶液的它们的组合。例如，凸块材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附接或接合工艺将凸块材料接合到导电层112。在一些实施例中，通过将材料加热到其熔点以上来回流凸块材料，以形成导电球或凸块114。在一个实施例中，导电凸块114形成在具有润湿层、阻挡层和粘附层的凸块下金属化层（UBM）上方。导电凸块114也可以压缩接合或热压接合到导电层112。导电凸块114表示可以在导电层112上方形成的一种类型的互连结构以便至衬底的电连接。互连结构也可以使用接合线、导电膏、柱形凸块、微型凸块或其他电互连。
在图1c中，使用锯片或激光切割工具118通过锯道106将半导体晶片100分割成个体半导体管芯104。个体半导体管芯104可以被检查和电测试，以在分割后标识KGD。
图2a-2h图示了形成具有半导体管芯104和开窗式散热器的半导体封装150。图2a是用作制造封装150的基础的衬底152的局部横截面视图。衬底152可以是从较大的面板分割的单元衬底，或者保持为较大的衬底面板的一部分。数百或数千个封装通常形成在单个衬底面板中，或者使用本文所述相同步骤形成在单个载体上的单独的单元衬底上。
衬底152包括与一个或多个导电层156交错的一个或多个绝缘层154。在一个实施例中，绝缘层154是芯绝缘板，其中导电层156在顶面和底面上方被图案化，例如覆铜层压衬底。导电层156还包括竖直地通过绝缘层154电耦合的导电通孔。衬底152可以包括任何数量的在彼此上方交错的导电层和绝缘层。焊料掩模或钝化层可以形成在衬底152的任一侧上方。在其它实施例中，任何合适类型的衬底或引线框用于衬底152。
对实现封装150的预期功能性所期望的任何部件安装到衬底152或设置在衬底152上方，并与导电层156电连接。衬底152具有两个主表面：顶面157和底面159。部件可以以任何合适的配置安装到顶面157和底面159上。在图2b中，在衬底152上制造封装150开始于使用例如任何合适的拾取和放置方法或设备在顶面157上表面安装半导体管芯104、分立部件164和子封装170。
半导体管芯104表示任何一个或多个电部件，其将在后续制造步骤中热连接或耦合至上覆的散热器，用于热管理。子封装170和分立部件164表示不需要直接耦合到散热器的部件。子封装170可以是任何合适类型或配置的任何合适的封装。子封装170也可以是类似于半导体管芯104的裸管芯，或者可以仅使用分立部件164而没有单独的子封装170。
图示的子封装170包括类似于衬底152的衬底172、类似于管芯104的管芯174、密封剂176和类似于凸块114的焊料凸块178。按照期望，可以在顶面157或159上安装附加的管芯、子封装或分立部件，以实现封装150的预期功能性。例如电阻器、电容器、电感器、晶体管或二极管的分立部件164使用焊膏或其他合适的附接和连接机构安装在顶面157上。焊膏在分立部件164的端子和顶面157上的导电层156的接触焊盘之间回流。凸块114和178通常在同一工艺步骤中回流，以分别将管芯104和子封装170物理和电连接到衬底152。
在图2c中，粘附层200设置在顶面157上。在一个实施例中，使用喷嘴将粘附层200分配成完全围绕衬底152周界的环。在其他实施例中，粘附层200围绕衬底152的周界是不连续的。
在图2d和图2e中，粘附层200用于将加强环202附接到衬底152。加强环202形成围绕半导体管芯104、子封装170和分立部件168的环。在图示的实施例中，加强环202完全延伸到衬底152的所有边缘，并连续围绕衬底的周界。在其他实施例中，衬底152可以延伸到加强环202的边界之外，并且附加部件可以设置在加强环边界之外的衬底上。加强环202直接坐落于粘附层200上，并且具有近似相同的形状。在其中加强环202不沿着衬底152的周界的实施例中，粘附层200被修改以相应地沿着加强环的形状。粘附层200将加强环202固定到衬底152。加强环202物理支撑最终封装以减少翘曲。
热界面材料（TIM）204设置在半导体管芯104的后表面108上。TIM 204促进了从半导体管芯104到将在后续制造步骤中放置的上覆的散热器的热传递。TIM 204可以以任何合适的图案施加，并且可以不完全覆盖后表面108。
图2e示出了衬底152上的加强环202的平面视图，揭示了多个分立部件164和一对子封装170a和170b。可以使用部件的任何合适组合。在一个实施例中，子封装170a是图2d的横截面中图示的子封装，而子封装170b是类似于管芯104的裸管芯。该平面视图示出了加强环202如何完全围绕衬底152上的部件延伸。加强环202也可以是不连续的。
在图2f和图2g中，散热器210设置在加强环202上。散热器210使用机械或激光切割从金属板材切割，或者使用任何其他合适的工艺形成。用于散热器210的材料是铜、钢、铝、钛、碳、它们的混合物、它们的合金或任何其他合适的金属或非金属散热器材料。散热器210包括与环202的外周界近似相同的外周界。在将散热器设置在加强环上之前，将粘附层214设置在散热器210、加强环202或两者上。粘附层214将散热器210机械固定到加强环202。选择加强环202的高度，使得散热器210的底面接触并且下压在TIM 204上。
散热器210将TIM 204压成薄层。TIM 204增强了从半导体管芯104到散热器210的导热性。一般而言，散热器210将被下压，直到散热器物理接触半导体管芯104。TIM 204填充在散热器210和半导体管芯104的背面108之间的微小间隙中，所述微小间隙是由于表面中的粗糙和其他缺陷而存在的。所有下面的实施例通常还包括它们相应的散热器，它们相应的散热器与它们相应的管芯或被冷却的其它电部件物理接触。
散热器210包括窗口212，该窗口212形成为完全穿过子封装170上方的散热器的开口。图2g示出了子封装170a和170b完全包含在窗口212的覆盖区内的平面视图。如果散热器210完全填充在加强环202内的区域中，则使子封装170完全位于窗口212的覆盖区内允许子封装比通常将被允许的要高。然而，如果子封装比加强环202短，则子封装170可以在散热器210下面延伸到窗口212的覆盖区之外。散热器210在分立部件168上方延伸，但是分立部件168也可以位于窗口212的覆盖区内。主要基于不需要与散热器210直接热接触的下覆部件的布局，窗口212以任何合适的形状形成。
通过以任何合适的方法将焊料凸块220应用于衬底152的底面159，类似于图1b中凸块114的应用，完成图2h中的封装150。凸块220后续用于将封装150安装到更大的电系统中。在一些实施例中，多个封装150形成为面板，并且然后在完成之后彼此分割。
半导体管芯104通过TIM 204热连接到散热器210，这允许从半导体管芯高效地移除热能。散热部件可以稍后附接到散热器210的与半导体管芯104相对的顶面，以增加暴露的表面积，并且从而增加向周围环境的热传递速率。散热器210中的开口212允许来自子封装170的热能从封装150逸出到周围环境。子封装170可能不需要经由散热器进行热管理，但是如果被完全封围在衬底152、加强环202和散热器210之间形成的没有窗口212的完整气泡内，则仍然可以产生足够的热量而引起故障。与在散热器210完全封围封装的情况下相比，窗口212允许封装150内的热量更快地逸出。需要散热部件或散热器的任何部件被放置在散热器210的下方，而不需要散热器的部件被放置在窗口212的下方或附近，以允许对流离开封装150。
图3示出了双面半导体封装222。半导体封装222类似于封装150，其中主要差异在于设置在底面159上的半导体管芯224和分立部件226。包括有源或无源分立部件、集成电路和子封装的部件的任何组合都可以安装在底面159上。
图4a-4c图示了其中加强环包括穿过封装以分隔电部件的杆的实施例。图4a中的加强件230包括一起形成为单个连续材料块的环形加强件230a和隔间加强件230b。隔间加强件230b为衬底152上的电部件创建了两个不同的隔间。替代地，如图4b中所示，除了环形加强件210之外，还可以添加单独的隔间加强件240。
隔间加强件帮助进一步支撑所得半导体封装防止翘曲，并减少从半导体管芯104经由辐射或对流到达子封装170的热量。图4c示出了具有隔间加强件的封装250的横截面。具有环形加强件210的隔间加强件240和具有内置隔间加强件230b的加强件230二者具有基本上相同的横截面外观，除了在加强件210和240之间存在间隙的横截面。作为示例，图4c还图示了延伸到窗口212中和散热器210的顶面上方的较高的子封装170c。任何实施例都可以包括较高的子封装170c。
在一些情况下，半导体管芯104的高度不适合用于设置在可用的特定厚度的环形加强件202上的扁平散热器。图5a-5c图示了适应不同高度的半导体管芯104的各种实施例。在图5a中，封装260包括比环形加强件202高的半导体管芯104a，并且因此散热器210将不能平放在环形加强件上。
因此，使用具有空腔264的散热器262，该空腔264形成在散热器的底面上。空腔264具有近似等于或略大于半导体管芯104a和环形加强件202之间的高度差的进入散热器262的深度。当散热器262被放置在环形加强件202上时，在空腔264的水平表面和半导体管芯104a的背面108之间存在微小间隙，以容纳TIM 266。
图5b示出了同一封装260的另一个横截面视图。图5b的横截面仅延伸穿过散热器262，并且不穿过窗口212。两个半导体管芯104a和104b耦合到散热器262用于冷却。如先前讨论的，半导体管芯104a比环形加强件202高，并且空腔264用于容纳超出的高度。另一方面，半导体管芯104b足够短，使得散热器210将离得太远而不能做出令人满意的热耦合。散热器262形成有突起268，以降低半导体管芯104b上方的散热器的底面。突起268将散热器262的底面带到下面，使得散热器和半导体管芯104b之间的间隙适于TIM 266热连接二者。突起268具有倾斜的边缘，但是边缘也可以是竖直的，如同空腔264一样。同样，空腔264可以具有倾斜的边缘，而不是图示的竖直边缘。
图5c示出了具有散热器272的封装270。封装270包括来自封装260的相同的两个半导体管芯104a和104b，其中管芯104a比环形加强件202高，并且管芯104b比环形加强件202短。散热器272被冲压或以其他方式弯曲、成形或形成为包括与散热器的其余部分相比具有不同高度的区域274和280，散热器的其余部分近似与环形加强件202的顶部齐平。从顶部冲压区域274，以朝向半导体管芯104b降低底面。因为散热器272以均匀的厚度开始，并且在冲压过程中没有材料被移除，所以散热器在区域274内的厚度保持近似等于区域274周围的厚度。通过向下移动区域274，在散热器272的顶部上形成凹面276，并且在散热器的底部上形成凸面278。
同样，从底部冲压区域280，以抬高散热器272的表面，并在顶部上形成凸面282，并且在底部上形成凹面284。在将散热器272安装到封装270上之前执行冲压。冲压将散热器272的金属弯曲成图示的形状或其他合适的形状。任何数量和高度的半导体管芯、半导体封装或其他合适的器件都可以经由图5a-5c中公开的任何方法与散热器进行热接触。
图6a-6c图示了其中通过散热器形成网格而不是窗口的各种实施例。该网格包括穿过散热器形成的多个较小的开口或孔，而不是一个较大的窗口。在图6a中，散热器290包括形成在子封装170a和170b上方的网格291。网格291包括多个菱形开口292。图6b中的散热器293包括包含多个方形开口295的网格294。图6c中的散热器296包括具有多个圆形开口298的网格297。开口292、295和298可以通过机械钻孔、机械冲孔、激光切割或其他合适的工艺形成。任何形状的开口都可以用来形成网格。在子封装170a和170b上方形成网格帮助在物理上保护子封装的顶部免受外部接触，同时仍然允许热对流离开封装。保留在网格孔之间的散热器材料提供物理保护，同时网格孔允许热对流离开封装。
图7a和图7b图示了将上述半导体封装（例如，封装150）并入电子器件300。图7a图示了作为电子器件300的部分安装在印刷电路板（PCB）或其他衬底302上的封装150的部分横截面。凸块220回流到PCB 302的导电层304上，以将封装150物理附接和电连接到PCB。在其他实施例中，使用热压或其他合适的附接和连接方法。在一些实施例中，在封装150和PCB302之间使用粘附层或底部填充层。半导体管芯104、分立部件168和子封装170通过衬底152和凸块220彼此电耦合并电耦合到导电层304。
图7b图示了包括PCB 302的电子器件300，其中PCB表面上安装有多个半导体封装、包括封装150。取决于应用，电子器件300可以具有一种类型的半导体封装或多种类型的半导体封装。电子器件300可以是使用半导体封装来执行一个或多个电功能的独立系统。替代地，电子器件300可以是更大系统的子部件。例如，电子器件300可以是平板计算机、蜂窝电话、数码相机、通信系统或其他电子器件的部分。电子器件300也可以是图形卡、网络接口卡或插入计算机的另一信号处理卡。半导体封装可以包括微处理器、存储器、ASIC、逻辑电路、模拟电路、RF电路、分立的有源或无源器件或其他半导体管芯或电部件。
在图7b中，PCB 302为安装在PCB上的半导体封装的结构支撑和电互连提供了通用衬底。使用蒸镀、电解电镀、非电解电镀、丝网印刷或其他合适的金属沉积工艺，在PCB 302的表面上方或层内形成导电信号迹线304。信号迹线304提供在半导体封装、安装的部件和其他外部系统或部件之间的电通信。迹线304还按照需要向半导体封装提供电源和接地连接。
在一些实施例中，半导体器件具有两个封装级。第一级封装是用于将半导体管芯机械地和电气地附接到中间衬底的技术。第二级封装涉及将中间衬底机械地和电气地附接到PCB 302。在其他实施例中，半导体器件可以仅具有第一级封装，其中管芯被机械地和电气地直接安装到PCB 302。
出于说明目的，PCB 302上示出了几种类型的第一级封装，包括焊线封装346和倒装芯片348。附加地，包括球栅阵列（BGA）350、凸块芯片载体（BCC）352、陆栅阵列（LGA）356、多芯片模块（MCM）358、方形扁平无引线封装（QFN）360、方形扁平封装362和嵌入式晶片级球栅阵列（eWLB）364的几种类型的第二级封装被示出连同封装150一起安装在PCB 302上。导电迹线304将设置在PCB 302上的各种封装和部件电耦合到封装150，从而给出将封装150内的部件对PCB上的其他部件的用途。
取决于系统要求，配置有第一级和第二级封装类型的任何组合的半导体封装的任何组合以及其他电子部件可以连接到PCB 302。在一些实施例中，电子器件300包括单个附接的半导体封装，而其他实施例要求多个互连的封装。通过在单个衬底上方组合一个或多个半导体封装，制造商可以将预制部件并入电子器件和系统中。因为半导体封装包括复杂的功能性，所以可以使用不太昂贵的部件和流水线制造工艺来制造电子器件。所得到的器件不太可能失效，并且制造不太昂贵，从而导致降低的消费者成本。
虽然已详细说明了本发明的一个或多个实施例，但技术人员将领会到，可以在不偏离如以下权利要求书中阐明的本发明的范围的情况下对这些实施例进行修改和调整。

Claims (15)

1.一种制造半导体器件的方法，包括：
提供衬底；
在衬底上方设置第一半导体管芯；
在衬底上方设置子封装；
在围绕第一半导体管芯和子封装的衬底上方设置加强件；和
在加强件上方设置散热器，其中散热器热耦合到第一半导体管芯，并且其中散热器包括子封装上方的开口。
2.根据权利要求1所述的方法，进一步包括在子封装上方的散热器中形成多个开口。
3.根据权利要求1所述的方法，其中，所述子封装完全设置在开口的覆盖区内。
4.根据权利要求1所述的方法，进一步包括将第二半导体管芯设置在衬底上方并热耦合到散热器，其中第一半导体管芯的高度不同于第二半导体管芯的高度。
5.根据权利要求1所述的方法，进一步包括在第一半导体管芯上方的散热器上形成空腔或突起。
6.根据权利要求1所述的方法，其中，所述加强件包括隔间加强件。
7.一种制造半导体器件的方法，包括：
提供衬底；
在衬底的第一表面上方设置加强件；和
在加强件上方设置散热器，其中散热器包括开口。
8.根据权利要求7所述的方法，进一步包括在散热器的开口下方的衬底的第一表面上方设置第一电部件。
9.根据权利要求7所述的方法，进一步包括将电部件设置在衬底上方并且热耦合到散热器。
10.根据权利要求7所述的方法，进一步包括在散热器中形成的突起或空腔。
11.一种半导体器件，包括：
衬底；
设置在衬底上方的加强件；和
设置在加强件上方的散热器，其中散热器包括开口。
12.根据权利要求11所述的半导体器件，进一步包括设置在散热器的开口下方的衬底上方的电部件。
13.根据权利要求12所述的半导体器件，进一步包括在电部件上方的散热器中形成的多个开口。
14.根据权利要求11所述的半导体器件，进一步包括设置在衬底上方并且热耦合到散热器的电部件。
15.根据权利要求11所述的半导体器件，其中，所述加强件包括隔间加强件。
CN202211070549.9A 2021-10-06 2022-09-02 具有开窗式散热器的封装 Pending CN115954274A (zh)

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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230187374A1 (en) * 2021-12-10 2023-06-15 Advanced Semiconductor Engineering, Inc. Electronic device and method of manufacturing the same

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050047094A1 (en) * 2003-08-28 2005-03-03 Shih-Ping Hsu Heat sink structure with embedded electronic components for semiconductor package
TW200531242A (en) * 2004-03-11 2005-09-16 Advanced Semiconductor Eng Multi package module with heat spreader
JP2007243106A (ja) * 2006-03-13 2007-09-20 Fujitsu Ltd 半導体パッケージ構造
JP2007258448A (ja) * 2006-03-23 2007-10-04 Fujitsu Ltd 半導体装置
US20080128897A1 (en) * 2006-12-05 2008-06-05 Tong Wa Chao Heat spreader for a multi-chip package
US7459782B1 (en) * 2005-10-05 2008-12-02 Altera Corporation Stiffener for flip chip BGA package
US20120050996A1 (en) * 2010-08-31 2012-03-01 Stmicroelectronics Asia Pacific Pte Ltd. Semiconductor package with thermal heat spreader
CN102456638A (zh) * 2010-10-20 2012-05-16 台湾积体电路制造股份有限公司 用于倒装芯片封装的顺应式散热器
CN103681544A (zh) * 2012-08-29 2014-03-26 美国博通公司 用于具有集成散热器的ic封装件的混合热界面材料
CN103871981A (zh) * 2012-12-13 2014-06-18 辉达公司 具有经改造的散热器的低外形芯片封装
CN212342623U (zh) * 2018-09-28 2021-01-12 赛灵思公司 芯片封装组件和高带宽存储器芯片封装组件
US20210259134A1 (en) * 2020-02-19 2021-08-19 Intel Corporation Substrate cooling using heat pipe vapor chamber stiffener and ihs legs

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6117352A (en) * 1997-11-20 2000-09-12 Lsi Logic Corporation Removal of a heat spreader from an integrated circuit package to permit testing of the integrated circuit and other elements of the package
US8115301B2 (en) * 2006-11-17 2012-02-14 Stats Chippac, Inc. Methods for manufacturing thermally enhanced flip-chip ball grid arrays
US9496199B2 (en) * 2012-12-04 2016-11-15 General Electric Company Heat spreader with flexible tolerance mechanism
JP6853774B2 (ja) 2017-12-21 2021-03-31 ルネサスエレクトロニクス株式会社 半導体装置
JP2020004821A (ja) 2018-06-27 2020-01-09 ルネサスエレクトロニクス株式会社 半導体装置
KR20200097659A (ko) * 2019-02-08 2020-08-19 마벨 아시아 피티이 엘티디. 플립 칩 볼 그리드 어레이용 히트 싱크 설계
US10804205B1 (en) * 2019-08-22 2020-10-13 Bridge Semiconductor Corp. Interconnect substrate with stiffener and warp balancer and semiconductor assembly using the same
US11532535B2 (en) * 2021-04-14 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die package with thermal management features and method for forming the same
US11616000B2 (en) * 2021-06-25 2023-03-28 Intel Corporation Methods and apparatus to provide electrical shielding for integrated circuit packages using a thermal interface material

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050047094A1 (en) * 2003-08-28 2005-03-03 Shih-Ping Hsu Heat sink structure with embedded electronic components for semiconductor package
TW200531242A (en) * 2004-03-11 2005-09-16 Advanced Semiconductor Eng Multi package module with heat spreader
US7459782B1 (en) * 2005-10-05 2008-12-02 Altera Corporation Stiffener for flip chip BGA package
JP2007243106A (ja) * 2006-03-13 2007-09-20 Fujitsu Ltd 半導体パッケージ構造
JP2007258448A (ja) * 2006-03-23 2007-10-04 Fujitsu Ltd 半導体装置
US20080128897A1 (en) * 2006-12-05 2008-06-05 Tong Wa Chao Heat spreader for a multi-chip package
US20120050996A1 (en) * 2010-08-31 2012-03-01 Stmicroelectronics Asia Pacific Pte Ltd. Semiconductor package with thermal heat spreader
CN102456638A (zh) * 2010-10-20 2012-05-16 台湾积体电路制造股份有限公司 用于倒装芯片封装的顺应式散热器
CN103681544A (zh) * 2012-08-29 2014-03-26 美国博通公司 用于具有集成散热器的ic封装件的混合热界面材料
CN103871981A (zh) * 2012-12-13 2014-06-18 辉达公司 具有经改造的散热器的低外形芯片封装
CN212342623U (zh) * 2018-09-28 2021-01-12 赛灵思公司 芯片封装组件和高带宽存储器芯片封装组件
US20210259134A1 (en) * 2020-02-19 2021-08-19 Intel Corporation Substrate cooling using heat pipe vapor chamber stiffener and ihs legs

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