JP2006100385A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2006100385A
JP2006100385A JP2004282017A JP2004282017A JP2006100385A JP 2006100385 A JP2006100385 A JP 2006100385A JP 2004282017 A JP2004282017 A JP 2004282017A JP 2004282017 A JP2004282017 A JP 2004282017A JP 2006100385 A JP2006100385 A JP 2006100385A
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JP
Japan
Prior art keywords
semiconductor chip
wiring board
opening
semiconductor device
solder resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004282017A
Other languages
English (en)
Inventor
Kazuma Tanida
一真 谷田
Osamu Miyata
修 宮田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2004282017A priority Critical patent/JP2006100385A/ja
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to CN2005800145828A priority patent/CN1950939B/zh
Priority to US10/594,561 priority patent/US8405227B2/en
Priority to PCT/JP2005/013355 priority patent/WO2006035541A1/ja
Priority to KR1020067022851A priority patent/KR101158139B1/ko
Priority to TW094129372A priority patent/TW200614475A/zh
Publication of JP2006100385A publication Critical patent/JP2006100385A/ja
Priority to US13/782,580 priority patent/US8754535B2/en
Priority to US14/276,255 priority patent/US9117774B2/en
Priority to US14/824,706 priority patent/US9721865B2/en
Priority to US15/635,478 priority patent/US9831204B2/en
Priority to US15/806,847 priority patent/US10522494B2/en
Priority to US16/703,266 priority patent/US10818628B2/en
Priority to US17/039,089 priority patent/US11355462B2/en
Priority to US17/752,835 priority patent/US11842972B2/en
Priority to US18/496,069 priority patent/US20240055384A1/en
Pending legal-status Critical Current

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Abstract

【課題】封止層中のボイドの形成を防止できる半導体装置を提供する。
【解決手段】この半導体装置１は、配線基板２と、この配線基板２の表面２ａに機能面３ａを対向させて接続された半導体チップ３とを含んでいる。配線基板２の表面２ａには、矩形状の接続パッドが形成されており、配線基板２と半導体チップ３とは、接続パッドに接続された接続部材５によって、所定間隔を保つように接合され、かつ互いに電気的に接続されている。配線基板２の表面２ａには、ソルダレジスト膜６が形成されている。ソルダレジスト膜６には、表面２ａを垂直に見下ろす平面視において、半導体チップ３よりも大きなサイズ、すなわち、その内部に半導体チップ３が完全に含まれるように形成された開口６ａが設けられている。配線基板２と半導体チップ３との隙間Ｇおよび開口６ａを埋めるようにアンダーフィル層７が形成されている。
【選択図】 図１

Description

この発明は、フリップチップ接続された半導体チップを有する半導体装置に関する。
半導体装置の小型化および高密度実装のために、半導体チップの機能素子が形成された機能面を固体装置に対向させて、半導体チップを固体装置に接続するフリップチップ接続構造が注目されている。
図４は、フリップチップ接続構造の半導体装置の図解的な断面図である。この半導体装置５１は、配線基板５２と、この配線基板５２の表面５２ａに機能面５３ａを対向させて接続された半導体チップ５３とを含んでいる。
配線基板５２の表面５２ａには、矩形状の接続パッド５８が形成されており、配線基板５２と半導体チップ５３とは、その接続パッド５８に接続された接続部材５５によって、所定間隔を保つように接合され、かつ互いに電気的に接続されている。また、配線基板５２の表面５２ａには、その表面５２ａと半導体チップ５３の機能面５３ａとの間隔より小さい厚みを有するソルダレジスト膜５６が形成されている。
ソルダレジスト膜５６には、接続パッド５８を露出させるための矩形状の開口５６ａが形成されている。この開口５６ａは、図５に示すように、平面視で接続パッド５８よりも大きく形成されており、この開口５６ａ内において、接続パッド５８に接続部材５５が接続されている。
また、ソルダレジスト膜５６の表面と半導体チップ５３の機能面５３ａとの間には、微小な隙間が形成されており、この隙間は、アンダーフィル層５７によって封止されている。このアンダーフィル層５７は、配線基板５２と半導体チップ５３との接合後に、それらの間に液状のアンダーフィル材を注入することによって形成される。
具体的には、配線基板５２と半導体チップ５３との接合後、図６Ａに示すように、半導体チップ５３の外周部の近傍に、ディスペンサ６０が配置されて、このディスペンサ６０からソルダレジスト膜５６の表面と半導体チップ５３の機能面５３ａとの間に液状のアンダーフィル材が流し込まれる。アンダーフィル材は、毛細管現象によって、図６Ｂに示すように、ソルダレジスト膜５６の表面と半導体チップ５３の機能面５３ａとの間に進入して広がっていく。そして、ソルダレジスト膜５６の表面と半導体チップ５３の機能面５３ａとの間の全域がアンダーフィル材で埋められると、ディスペンサ６０からのアンダーフィル材の吐出が停止され、その後、アンダーフィル材が硬化されることによって、アンダーフィル層５７が得られる。
Chee Choong Kooi、他６名、"Capillary Underfill and Mold Encapsulation Materials for Exposed Die Flip Chip Molded Matrix Array Package with Thin Substrate"、2003 Electronics Packaging Technology Conference、p.324-330
ところが、開口５６ａ内と開口５６ａ外との間に段差が生じ、また、開口５６ａの上方が半導体チップ５３で制限されているため、アンダーフィル材が開口５６ａ内に流れ込むときに、その開口５６ａの周縁部（段差部分）に存在している空気が上手く抜けずに、アンダーフィル材に取り込まれて、アンダーフィル層５７に、いわゆるボイド６１を生じることがあった。たとえば、アンダーフィル層５７にボイドが生じていると、リフロー工程で、アンダーフィル層５７にクラックが発生し、半導体装置の信頼性の低下を招く。
そこで、この発明の目的は、封止層中のボイドの形成を防止できる構成の半導体装置を提供することである。
上記の目的を達成するための請求項１記載の発明は、固体装置（２，２２）と、機能素子（４）が形成された機能面（３ａ）を有し、その機能面を上記固体装置の表面に対向させて、上記固体装置の表面との間に所定間隔を保持して接合される半導体チップ（３）と、上記固体装置の上記半導体チップとの対向面（２ａ，２２ａ）に設けられ、その対向面を垂直に見下ろす平面視において、上記半導体チップよりも大きなサイズに形成された開口（６ａ）を有する絶縁膜（６）と、上記固体装置と上記半導体チップとの間を封止する封止層（７）とを含むことを特徴とする半導体装置（１，２１）である。
なお、括弧内の数字は、後述の実施形態における対応構成要素等を表す。以下、この項において同じ。
この発明によれば、絶縁膜の開口は、固体装置の半導体チップとの対向面を垂直に見下ろす平面視において、半導体チップよりも大きなサイズに形成されている。言い換えれば、絶縁膜の開口は、固体装置の対向面を垂直に見下ろす平面視において、その中に半導体チップが完全に含まれるように形成されている。これにより、固体装置と半導体チップとの隙間に、絶縁膜の開口による段差が生じることを防止できるとともに、その開口周縁部の上方のスペースが半導体チップによって制限されることを防止できる。
そのため、この半導体装置の製造工程において、絶縁膜の形成および固体装置と半導体チップとの接合の後、封止層を形成するために、液状の封止樹脂材を固体装置と半導体チップとの隙間に充填する際、液状の封止樹脂材に空気が取り込まれることによるボイドの形成を防止することができる。その結果、この半導体装置の信頼性を向上させることができる。
固体装置の半導体チップとの対向面を垂直に見下ろす平面視において、半導体チップの外周と絶縁膜の開口縁部との間隔は、０．１ｍｍ以上であることが好ましい。
固体装置は、絶縁基板に配線が形成されてなる配線基板であってもよく、半導体基板であってもよい。
絶縁膜は、ソルダレジストであってもよい。この場合、ソルダレジストで覆われた領域における電気的短絡（ショート）を防止することができる。
上記封止層は、請求項２記載のように、上記開口内を埋めつくすように設けられていてもよい。これにより、固体装置において、絶縁膜の開口からの露出部を封止層により保護することができる。
以下では、この発明の実施の形態を、図面を参照して詳細に説明する。
図１は、本発明の第１の実施形態に係る半導体装置の図解的な断面図である。
この半導体装置１は、配線基板２と、この配線基板２の表面２ａに機能面３ａを対向させて接続された半導体チップ３とを含んでいる。配線基板２の表面２ａには、矩形状の接続パッド（図２Ｃおよび図２Ｄ参照）が形成されており、配線基板２と半導体チップ３とは、その接続パッドに接続された接続部材５によって、所定間隔を保つように接合され、かつ互いに電気的に接続されている。
配線基板２の表面２ａには、その表面２ａと半導体チップ３との間隔より小さい厚みを有するソルダレジスト膜６が形成されている。このソルダレジスト膜６により、配線基板２の表面に形成されている配線間での電気的短絡が防止されている。ソルダレジスト膜６には、表面２ａを垂直に見下ろす平面視において、半導体チップ３よりも大きなサイズを有する開口６ａが形成されている。言い換えれば、ソルダレジスト膜６には、表面２ａを垂直に見下ろす平面視において、その内部に半導体チップ３が完全に含まれるようなサイズの開口６ａが形成されている。これにより、配線基板２と半導体チップ３との隙間Ｇ（配線基板２と半導体チップ３との間であって、表面２ａを垂直に見下ろす平面視において、半導体チップ３と重なる領域）には、ソルダレジスト膜６が存在していない。
表面２ａを垂直に見下ろす平面視において、半導体チップ３の外周とソルダレジスト膜６の開口６ａの縁部との間隔Ｄは、０．１ｍｍ以上にされている。
配線基板２と半導体チップ３との隙間Ｇおよびその周辺には、アンダーフィル層７が設けられている。アンダーフィル層７は、ソルダレジスト膜６の開口６ａを埋めつくすように形成されており、アンダーフィル層７によって、隙間Ｇが封止されるとともに、機能面３ａ、接続部材５、および開口６ａからの表面２ａの露出部が保護されている。
配線基板２の端部には、図示しない配線により接続部材５と電気的に接続された端面電極８が形成されている。端面電極８は、配線基板２の表面２ａから端面を経て、表面２ａの反対側の外部接続面２ｂに至るように形成されている。この半導体装置１は、端面電極８において、他の配線基板（実装基板）との電気的接続を達成することができる。
図２Ａないし図２Ｄは、図１に示す半導体装置１の製造方法を説明するための図解的な断面図である。半導体装置１は、配線基板２の表面２ａに対して、半導体チップ３を、その機能面３ａを対向させて接合した後、ソルダレジスト膜６の開口６ａ内にアンダーフィル材７Ｐを注入し、そのアンダーフィル材７Ｐを硬化させてアンダーフィル層７を形成することによって得られる。
具体的には、先ず、複数の配線基板２が作り込まれた基板１５が用意される。
次に、この基板１５の表面１５ａ（配線基板２の表面２ａに対応する面）の全面に液状で感光性を有するソルダレジスト膜６が塗布（たとえば、スピンコートによる）または印刷された後、露光および現像により、半導体チップ３よりも大きなサイズを有する開口６ａが形成される。
次に、機能素子４の電極に接続された突起電極（バンプ）１８を有する半導体チップ３が用意される。突起電極１８は、はんだ材料を含む。
続いて、基板１５が、表面１５ａを上に向けられ、ほぼ水平な姿勢で保持される。そして、内部にヒータを備えて加熱することが可能なボンディングツール１９により、半導体チップ３が、その機能面３ａと反対側の面を吸着されて保持される。半導体チップ３は、機能面３ａが下方に向けられて基板１５の表面１５ａに対向される。この状態が、図２Ａに示されている。
続いて、半導体チップ３の突起電極１８が基板１５の接続パッド１６に当接するように位置合わせされた後、ボンディングツール１９が下降されて、半導体チップ３が基板１５に接合される。この際、ボンディングツール１９により、半導体チップ３が加熱され、その熱により突起電極１８のはんだ材料が溶融されて、突起電極１８と接続パッド１６とが接合される。これにより、基板１５と半導体チップ３とを機械的に接合する接続部材５が形成される。接続部材５により、基板１５の表面１５ａに形成された配線と、半導体チップ３の機能素子４とが電気的に接続される。
続いて、ソルダレジスト膜６の開口６ａの周縁部上方に、ディスペンサ１０が配置されて、そのディスペンサ１０から開口６ａ内にアンダーフィル材７Ｐが注入される（図２Ｂ参照）。
アンダーフィル材７Ｐは、毛細管現象により、基板１５と半導体チップ３との隙間Ｇに進入していき、この隙間Ｇ内を表面２ａに沿って広がっていく（図２Ｃ参照。アンダーフィル材７Ｐが広がる方向を、図２Ｃに矢印Ａで示す。）。そして、ディスペンサ１０から適当な量のアンダーフィル材７Ｐが吐出され、隙間Ｇおよびソルダレジスト膜６の開口６ａの内部がアンダーフィル材７Ｐで埋められると、アンダーフィル材７Ｐの吐出は停止される。その後、アンダーフィル材７Ｐを硬化させるための処理が行われて、開口６ａ内にアンダーフィル層７が形成される。
その後、基板１５が配線基板２の個片に切断され（切断位置を、図２Ａに符号Ｃで示す。）、配線基板２の端部に端面電極８が形成されて、図１に示す半導体装置１が得られる。
以上のように、ソルダレジスト膜６の開口６ａは、表面１５ａを垂直に見下ろす平面視において、その中に半導体チップ３が完全に含まれるように形成される。これにより、基板１５と半導体チップ３との隙間Ｇに、ソルダレジスト膜６の開口６ａによる段差が生じることを防止できるとともに、その開口６ａ周縁部の上方のスペースが半導体チップ３によって制限されることを防止できる。
このため、液状のアンダーフィル材７Ｐを基板１５と半導体チップ３との隙間Ｇに充填する際、アンダーフィル材７Ｐに空気が取り込まれることによるボイドの形成を防止することができる。その結果、得られたこの半導体装置１の信頼性を向上させることができる。
アンダーフィル層７にボイドが含まれていないことにより、この半導体装置１を、たとえば、リフローにより他の配線基板に接合してもボイドに起因するクラックは生じない。
図３は、本発明の第２の実施形態に係る半導体装置の図解的な断面図である。図３において、図１に示す各部に対応する部分には、図１と同じ参照符号を付している。
この半導体装置２１は、配線基板２２と、この配線基板２２の表面２２ａに機能面３ａを対向させて接続された半導体チップ３とを含んでいる。
配線基板２２の表面２２ａには、ソルダレジスト膜６が形成されている。ソルダレジスト膜６には、表面２２ａを垂直に見下ろす平面視において、半導体チップ３よりも大きなサイズの、すなわち、その内部に半導体チップ３が完全に含まれるように形成された開口６ａが設けられている。
配線基板２２において、表面２２ａと反対側の外部接続面２２ｂには、金属ボール２３が設けられている。金属ボール２３は、配線基板２２の内部および／または表面で再配線されて、表面２２ａ側の接続部材５に電気的に接続されている。この半導体装置２１は、金属ボール２３を介して、他の配線基板（実装基板）に接合できる。
この半導体装置２１を製造する場合は、基板１５の代わりに、複数の配線基板２２に相当する領域が密に形成された基板を用いて、上記と同様の製造方法（図２Ａないし図２Ｄ参照）を実施すればよい。金属ボール２３は、基板を配線基板２２の個片に切り出す前に、この基板に接合されてもよく、配線基板２２の個片が切り出された後に、この配線基板２２に接合されてもよい。
本発明の実施形態の説明は以上の通りであるが、本発明は、別の形態でも実施できる。たとえば、配線基板２，２２には、２つ以上の半導体チップ３がフリップチップ接続されていてもよい。この場合、ソルダレジスト膜６には、表面２ａ，２２ａを垂直に見下ろす平面視において、各半導体チップ３を完全に含む１つまたは２つ以上の開口６ａが形成されているものとすることができる。
その他、特許請求の範囲に記載された事項の範囲で種々の変更を施すことが可能である。
本発明の第１の実施形態に係る半導体装置の図解的な断面図である。 図１に示す半導体装置の製造方法を説明するための図解的な断面図である。 図１に示す半導体装置の製造方法を説明するための図解的な断面図である。 図１に示す半導体装置の製造方法を説明するための図解的な断面図である。 図１に示す半導体装置の製造方法を説明するための図解的な断面図である。 本発明の第２の実施形態に係る半導体装置の図解的な断面図である。 フリップチップ接続された半導体チップを有する従来の半導体装置の構造を示す図解的な断面図である。 図４に示す配線基板の接続面を垂直に見下ろす図解的な平面図である。 図４に示す半導体装置の製造方法を説明するための図解的な断面図である。 図４に示す半導体装置の製造方法を説明するための図解的な断面図である。
符号の説明
１，２１ 半導体装置
２，２２ 配線基板
２ａ，２２ａ 表面
３ 半導体チップ
３ａ 機能面
４ 機能素子
６ ソルダレジスト膜
６ａ ソルダレジスト膜の開口
７ 封止樹脂
Ｇ 配線基板と半導体チップとの隙間

Claims (2)

  1. 固体装置と、
    機能素子が形成された機能面を有し、その機能面を上記固体装置の表面に対向させて、上記固体装置の表面との間に所定間隔を保持して接合される半導体チップと、
    上記固体装置の上記半導体チップとの対向面に設けられ、その対向面を垂直に見下ろす平面視において、上記半導体チップよりも大きなサイズに形成された開口を有する絶縁膜と、
    上記固体装置と上記半導体チップとの間を封止する封止層とを含むことを特徴とする半導体装置。
  2. 上記封止層が、上記開口を埋めつくすように設けられていることを特徴とする請求項１記載の半導体装置。
JP2004282017A 2004-09-28 2004-09-28 半導体装置 Pending JP2006100385A (ja)

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JP2004282017A JP2006100385A (ja) 2004-09-28 2004-09-28 半導体装置
CN2005800145828A CN1950939B (zh) 2004-09-28 2005-07-21 半导体装置
US10/594,561 US8405227B2 (en) 2004-09-28 2005-07-21 Semiconductor device with a semiconductor chip connected in a flip chip manner
PCT/JP2005/013355 WO2006035541A1 (ja) 2004-09-28 2005-07-21 半導体装置
KR1020067022851A KR101158139B1 (ko) 2004-09-28 2005-07-21 반도체 장치
TW094129372A TW200614475A (en) 2004-09-28 2005-08-26 Semiconductor device
US13/782,580 US8754535B2 (en) 2004-09-28 2013-03-01 Semiconductor device with a semiconductor chip connected in a flip chip manner
US14/276,255 US9117774B2 (en) 2004-09-28 2014-05-13 Semiconductor device with a semiconductor chip connected in a flip chip manner
US14/824,706 US9721865B2 (en) 2004-09-28 2015-08-12 Semiconductor device with a semiconductor chip connected in a flip chip manner
US15/635,478 US9831204B2 (en) 2004-09-28 2017-06-28 Semiconductor device with a semiconductor chip connected in a flip chip manner
US15/806,847 US10522494B2 (en) 2004-09-28 2017-11-08 Semiconductor device with a semiconductor chip connected in a flip chip manner
US16/703,266 US10818628B2 (en) 2004-09-28 2019-12-04 Semiconductor device with a semiconductor chip connected in a flip chip manner
US17/039,089 US11355462B2 (en) 2004-09-28 2020-09-30 Semiconductor device with a semiconductor chip connected in a flip chip manner
US17/752,835 US11842972B2 (en) 2004-09-28 2022-05-24 Semiconductor device with a semiconductor chip connected in a flip chip manner
US18/496,069 US20240055384A1 (en) 2004-09-28 2023-10-27 Semiconductor device with a semiconductor chip connected in a flip chip manner

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