JP7189672B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP7189672B2 JP7189672B2 JP2018079689A JP2018079689A JP7189672B2 JP 7189672 B2 JP7189672 B2 JP 7189672B2 JP 2018079689 A JP2018079689 A JP 2018079689A JP 2018079689 A JP2018079689 A JP 2018079689A JP 7189672 B2 JP7189672 B2 JP 7189672B2
- Authority
- JP
- Japan
- Prior art keywords
- pads
- semiconductor chip
- bonding
- circuit forming
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 125
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 229920005989 resin Polymers 0.000 claims description 40
- 239000011347 resin Substances 0.000 claims description 40
- 239000000463 material Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 23
- 238000007789 sealing Methods 0.000 claims description 14
- 230000007423 decrease Effects 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 description 44
- 238000010586 diagram Methods 0.000 description 11
- 238000012986 modification Methods 0.000 description 9
- 230000004048 modification Effects 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05555—Shape in top view being circular or elliptic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/0801—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13116—Lead [Pb] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1705—Shape
- H01L2224/17051—Bump connectors having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
[第1の実施の形態に係る半導体装置の構造]
まず、第1の実施の形態に係る半導体装置の構造について説明する。図1は、第1の実施の形態に係る半導体装置を例示する図であり、図1(a)は断面図、図1(b)は図1(a)の配線基板10とパッド11及び12のみを示した平面図である。
次に、第1の実施の形態に係る半導体装置の製造方法について説明する。図2~図4は、第1の実施の形態に係る半導体装置の製造工程を例示する図である。
第1の実施の形態の変形例1では、辺101側から辺102側に向かって接合面の面積が漸次小さくなるように、接合面の面積が異なる3種以上のパッドを配置する例を示す。なお、第1の実施の形態の変形例1において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第2の実施の形態では、第1の実施の形態とは異なる方法で半導体チップを傾けて配線基板に実装する例を示す。なお、第2の実施の形態において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
10、10A、10B、10S、10T 配線基板
10a、10Sa、10Ta 配線基板の一方の面
11、12、13、14 パッド
16 突起部
20、20A 半導体チップ
20a 回路形成面
30 はんだバンプ
40 封止樹脂
101、101S、101T、102、102S、102T 辺
501 下型
502 上型
503 注入口
A 半導体チップ搭載領域
A1 第1辺
A2 第2辺
A3 第3辺
A4 第4辺
C 切断位置
Claims (8)
- 一方の面に複数のパッドが形成された配線基板と、
回路形成面に複数の電極が形成され、前記回路形成面が前記一方の面と対向するように前記配線基板に実装された半導体チップと、
互いに対向する位置にある前記パッドと前記電極とを電気的に接続する、同一材料からなる複数の接合材と、
前記一方の面に形成され、前記半導体チップを封止すると共に前記回路形成面と前記一方の面との隙間を充填する樹脂と、を有し、
前記半導体チップは、前記回路形成面と前記一方の面との間隔が第1側から第2側に向かって漸次大きくなるように前記配線基板に実装され、
複数の前記パッドは、前記接合材と接合される接合面の面積が異なるパッドを含み、
前記第2側に配置されたパッドの接合面の面積が前記第1側に配置されたパッドの接合面の面積よりも小さく、
前記第2側に配置されたパッドは、1つの前記電極と対向して1つの前記接合材により接続され、
前記第1側に配置されたパッドは、1つの前記電極と対向して1つの前記接合材により接続される半導体装置。 - 前記第1側から前記第2側に向かって接合面の面積が異なる3種以上のパッドが配置され、
前記3種以上のパッドは、前記第1側から前記第2側に向かって前記接合面の面積が漸次小さくなるように配置されている請求項1に記載の半導体装置。 - 前記第2側において、前記回路形成面と前記一方の面との間に1つ以上の突起部が設けられている請求項1に記載の半導体装置。
- 前記半導体チップの平面形状は矩形状であり、
前記回路形成面は、平面視において前記第1側を向く第1辺、前記第1辺と平行で前記第2側を向く第2辺、前記第1辺の一端と前記第2辺の一端とを接続する第3辺、及び前記第1辺の他端と前記第2辺の他端とを接続する第4辺を備え、
前記1つ以上の突起部は、前記第2辺と前記第3辺とが形成する角部、及び前記第2辺と前記第4辺とが形成する角部と接するように設けられた2つの突起部を含む請求項3に記載の半導体装置。 - 一方の面に複数のパッドが形成された配線基板と、回路形成面に複数の電極が形成され各々の前記電極に接合材が形成された半導体チップと、を準備し、各々の前記接合材が各々の前記パッドと接するように前記一方の面側に前記半導体チップを配置し、前記接合材を溶融後凝固させて前記回路形成面と前記一方の面との間隔が第1側から第2側に向かって漸次大きくなるように前記配線基板に前記半導体チップを実装する工程と、
前記一方の面に、前記半導体チップを封止すると共に前記回路形成面と前記一方の面との隙間を充填する樹脂を形成する工程と、を有し、
複数の前記パッドは、前記接合材と接合される接合面の面積が異なるパッドを含み、
前記第2側に配置されたパッドの接合面の面積が前記第1側に配置されたパッドの接合面の面積よりも小さく、
前記半導体チップを実装する工程では、互いに対向する位置にある前記パッドと前記電極とを同一材料からなる複数の接合材で電気的に接続し、前記第1側に配置されたパッドの接合面上の前記接合材の厚さが、前記第2側に配置されたパッドの接合面上の前記接合材の厚さよりも薄くなるように前記半導体チップが実装され、
前記第2側に配置されたパッドは、1つの前記電極と対向して1つの前記接合材により接続され、
前記第1側に配置されたパッドは、1つの前記電極と対向して1つの前記接合材により接続され、
前記樹脂を形成する工程では、前記第2側から前記樹脂を注入する半導体装置の製造方法。 - 前記第1側から前記第2側に向かって接合面の面積が異なる3種以上のパッドが配置され、
前記3種以上のパッドは、前記第1側から前記第2側に向かって前記接合面の面積が漸次小さくなるように配置されている請求項5に記載の半導体装置の製造方法。 - 前記配線基板の前記第2側に1つ以上の突起部が設けられ、
前記半導体チップを実装する工程では、前記1つ以上の突起部が前記回路形成面の前記第2側と接するように前記半導体チップが実装される請求項5に記載の半導体装置の製造方法。 - 前記半導体チップの平面形状は矩形状であり、
前記回路形成面は、平面視において前記第1側を向く第1辺、前記第1辺と平行で前記第2側を向く第2辺、前記第1辺の一端と前記第2辺の一端とを接続する第3辺、及び前記第1辺の他端と前記第2辺の他端とを接続する第4辺を備え、
前記1つ以上の突起部は、前記第2辺と前記第3辺とが形成する角部、及び前記第2辺と前記第4辺とが形成する角部と接するように設けられた2つの突起部を含む請求項7に記載の半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018079689A JP7189672B2 (ja) | 2018-04-18 | 2018-04-18 | 半導体装置及びその製造方法 |
US16/380,166 US10784177B2 (en) | 2018-04-18 | 2019-04-10 | Semiconductor device with encapsulating resin |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018079689A JP7189672B2 (ja) | 2018-04-18 | 2018-04-18 | 半導体装置及びその製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2019192667A JP2019192667A (ja) | 2019-10-31 |
JP2019192667A5 JP2019192667A5 (ja) | 2021-03-25 |
JP7189672B2 true JP7189672B2 (ja) | 2022-12-14 |
Family
ID=68238233
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018079689A Active JP7189672B2 (ja) | 2018-04-18 | 2018-04-18 | 半導体装置及びその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10784177B2 (ja) |
JP (1) | JP7189672B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11024608B2 (en) | 2017-03-28 | 2021-06-01 | X Display Company Technology Limited | Structures and methods for electrical connection of micro-devices and substrates |
US11101417B2 (en) | 2019-08-06 | 2021-08-24 | X Display Company Technology Limited | Structures and methods for electrically connecting printed components |
US11316086B2 (en) | 2020-07-10 | 2022-04-26 | X Display Company Technology Limited | Printed structures with electrical contact having reflowable polymer core |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003243818A (ja) | 2002-02-15 | 2003-08-29 | Denso Corp | 半導体電子部品の実装方法 |
JP2010161425A (ja) | 2010-04-26 | 2010-07-22 | Panasonic Corp | モジュールの製造方法と、その製造設備 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS538566A (en) * | 1976-07-12 | 1978-01-26 | Citizen Watch Co Ltd | Mounting structure of semiconductor ic circuit |
EP0248566A3 (en) * | 1986-05-30 | 1990-01-31 | AT&T Corp. | Process for controlling solder joint geometry when surface mounting a leadless integrated circuit package on a substrate |
KR100192766B1 (ko) * | 1995-07-05 | 1999-06-15 | 황인길 | 솔더볼을 입출력 단자로 사용하는 볼그리드 어레이 반도체 패키지의 솔더볼 평탄화 방법 및 그 기판구조 |
TW434856B (en) * | 2000-05-15 | 2001-05-16 | Siliconware Precision Industries Co Ltd | Manufacturing method for high coplanarity solder ball array of ball grid array integrated circuit package |
JP3891838B2 (ja) * | 2001-12-26 | 2007-03-14 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
JP2006196728A (ja) * | 2005-01-14 | 2006-07-27 | Seiko Epson Corp | 電子部品、電気光学装置、及び電子機器 |
JP2009049499A (ja) * | 2007-08-14 | 2009-03-05 | Fujifilm Corp | 半導体チップの実装方法及び半導体装置 |
JP2009117767A (ja) * | 2007-11-09 | 2009-05-28 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法及びそれにより製造した半導体装置 |
JP5375708B2 (ja) * | 2010-03-29 | 2013-12-25 | パナソニック株式会社 | 半導体装置の製造方法 |
JP2011243683A (ja) * | 2010-05-17 | 2011-12-01 | Fujitsu Ltd | 電子部品の実装方法、電子部品の製造方法および電子部品、電子部品の製造装置 |
KR101712043B1 (ko) * | 2010-10-14 | 2017-03-03 | 삼성전자주식회사 | 적층 반도체 패키지, 상기 적층 반도체 패키지를 포함하는 반도체 장치 및 상기 적층 반도체 패키지의 제조 방법 |
US8367475B2 (en) * | 2011-03-25 | 2013-02-05 | Broadcom Corporation | Chip scale package assembly in reconstitution panel process format |
JP5820991B2 (ja) * | 2012-01-17 | 2015-11-24 | パナソニックIpマネジメント株式会社 | 半導体装置製造方法および半導体装置 |
US9343419B2 (en) * | 2012-12-14 | 2016-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structures for semiconductor package |
US9070644B2 (en) * | 2013-03-15 | 2015-06-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging mechanisms for dies with different sizes of connectors |
US8970051B2 (en) * | 2013-06-28 | 2015-03-03 | Intel Corporation | Solution to deal with die warpage during 3D die-to-die stacking |
JP6303373B2 (ja) | 2013-10-02 | 2018-04-04 | 住友ベークライト株式会社 | 圧縮成形用モールドアンダーフィル材料、半導体パッケージ、構造体および半導体パッケージの製造方法 |
KR20160004065A (ko) * | 2014-07-02 | 2016-01-12 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조방법 |
JP2016063013A (ja) * | 2014-09-17 | 2016-04-25 | 株式会社東芝 | 半導体装置 |
CN106206633A (zh) * | 2015-05-28 | 2016-12-07 | 精材科技股份有限公司 | 影像感测装置 |
-
2018
- 2018-04-18 JP JP2018079689A patent/JP7189672B2/ja active Active
-
2019
- 2019-04-10 US US16/380,166 patent/US10784177B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003243818A (ja) | 2002-02-15 | 2003-08-29 | Denso Corp | 半導体電子部品の実装方法 |
JP2010161425A (ja) | 2010-04-26 | 2010-07-22 | Panasonic Corp | モジュールの製造方法と、その製造設備 |
Also Published As
Publication number | Publication date |
---|---|
US20190326189A1 (en) | 2019-10-24 |
US10784177B2 (en) | 2020-09-22 |
JP2019192667A (ja) | 2019-10-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100652242B1 (ko) | 플립칩형 반도체장치, 이의 제조를 위한 제조방법 및 이런 플립칩형 반도체장치를 사용하여 전자제품을 제조하기 위한 제조방법 | |
US8021932B2 (en) | Semiconductor device, and manufacturing method therefor | |
US20140295620A1 (en) | Method of manufacturing semiconductor device having plural semiconductor chips stacked one another | |
JP7189672B2 (ja) | 半導体装置及びその製造方法 | |
TW200414471A (en) | Semiconductor device and manufacturing method for the same | |
WO2006035541A1 (ja) | 半導体装置 | |
WO2006035548A1 (ja) | 配線基板および半導体装置 | |
JP2008159955A (ja) | 電子部品内蔵基板 | |
JP2012069903A (ja) | 半導体装置及びその製造方法 | |
JP2013021058A (ja) | 半導体装置の製造方法 | |
JP2012015142A (ja) | 半導体パッケージおよびその製造方法 | |
US8179686B2 (en) | Mounted structural body and method of manufacturing the same | |
JP2005085931A (ja) | 半導体チップ及びその実装回路基板 | |
JP2007294560A (ja) | 半導体装置およびその製造方法 | |
JP4324773B2 (ja) | 半導体装置の製造方法 | |
KR20120032764A (ko) | 플립칩 패키지용 기판 및 이를 이용한 플립칩 패키지의 제조 방법 | |
JP2004363289A (ja) | 半導体装置の製造方法 | |
WO2018150809A1 (ja) | 半導体装置、チップ状半導体素子、半導体装置を備えた電子機器、及び、半導体装置の製造方法 | |
JP4561969B2 (ja) | 半導体装置 | |
TW201306197A (zh) | 以金屬柱銲接為晶片連接之半導體封裝構造 | |
JP4591715B2 (ja) | 半導体装置の製造方法 | |
TWI429041B (zh) | 非陣列凸塊之覆晶接合方法與構造 | |
JP2015053374A (ja) | 半導体装置及び半導体装置の製造方法 | |
JPH11274235A (ja) | 半導体装置およびその製造方法 | |
JP2015076539A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20210205 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20210205 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20211108 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20211221 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20220214 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20220712 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20220913 |
|
C60 | Trial request (containing other claim documents, opposition documents) |
Free format text: JAPANESE INTERMEDIATE CODE: C60 Effective date: 20220913 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20220926 |
|
C21 | Notice of transfer of a case for reconsideration by examiners before appeal proceedings |
Free format text: JAPANESE INTERMEDIATE CODE: C21 Effective date: 20221004 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20221108 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20221202 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7189672 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |