WO2024099219A1 - 芯片封装方法及封装结构 - Google Patents

芯片封装方法及封装结构 Download PDF

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Publication number
WO2024099219A1
WO2024099219A1 PCT/CN2023/129349 CN2023129349W WO2024099219A1 WO 2024099219 A1 WO2024099219 A1 WO 2024099219A1 CN 2023129349 W CN2023129349 W CN 2023129349W WO 2024099219 A1 WO2024099219 A1 WO 2024099219A1
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WIPO (PCT)
Prior art keywords
layer
chip
electrical component
substrate
filled
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Application number
PCT/CN2023/129349
Other languages
English (en)
French (fr)
Inventor
刘飞
Original Assignee
矽磐微电子(重庆)有限公司
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Publication of WO2024099219A1 publication Critical patent/WO2024099219A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers

Definitions

  • the present disclosure relates to the field of packaging technology, and in particular to a chip packaging method and a packaging structure.
  • the existing chip packaging method mainly includes the following steps: printing solder paste on the pad of the substrate; flipping the chip on the pad; performing reflow soldering to solder the solder bumps (or solder joints) of the chip on the pad; filling the bottom filler and curing the bottom filler.
  • the fluidity and viscosity of the bottom filler may easily cause incomplete filling of the chip bottom, and voids may easily appear between two adjacent solder bumps of the chip.
  • the solder bumps of the chip will melt again.
  • the molten material will flow through the voids and cause the adjacent solder bumps of the chip to connect, thus causing a short circuit defect in the chip.
  • the present disclosure provides a chip packaging method and a packaging structure.
  • the present disclosure provides a chip packaging method.
  • the chip packaging method includes: providing a substrate, the first surface of the substrate having a plurality of pads; forming a pre-filled layer on the first surface of the substrate, the pre-filled layer having a plurality of bump placement openings, the plurality of bump placement openings respectively exposing the plurality of pads; and mounting an electrical component on the pre-filled layer, the electrical component having a plurality of solder bumps, each solder bump of the electrical component being embedded in a corresponding bump placement opening in the plurality of bump placement openings and connected to a corresponding pad in the plurality of pads.
  • forming a pre-filled layer on the first surface of the substrate includes: forming a pre-filled layer on the first surface of the substrate; and forming the plurality of bump placement openings in the pre-filled layer by laser drilling.
  • forming a pre-filled layer on the first surface of the substrate includes: forming a pre-filled layer having the plurality of bump placement openings on the first surface of the substrate by means of spot coating or printing.
  • the step of mounting the electrical component on the pre-filled layer comprises: applying solder paste on the plurality of pads in the plurality of bump placement openings; mounting the electrical component on the substrate, wherein each solder bump of the electrical component is embedded in the corresponding bump placement opening and in contact with the applied solder paste; and performing reflow soldering.
  • each solder bump of the electrical component is melted and welded on the corresponding pad.
  • providing a substrate includes: providing a first carrier, mounting a first chip and a conductor on the first carrier, the conductor including a conductive structure and a molding material for molding the conductive structure, and a portion of the conductive structure is exposed from the molding material; forming a first molding layer on the first carrier, the first molding layer at least covering the side walls of the first chip and the side walls of the conductor; and forming a first rewiring layer on the first molding layer, the first rewiring layer being electrically connected to one end of the conductor, the first rewiring layer including the multiple pads.
  • the chip packaging method includes: after mounting the electrical component on the pre-filled layer, filling a bottom filler at the bottom of the electrical component, wherein the bottom filler is at least filled between the electrical component and the pre-filled layer; and curing the bottom filler.
  • the pre-fill layer is made of the same material as the bottom filler.
  • the chip packaging method includes: after curing the bottom filler, forming a second plastic encapsulation layer on the first surface of the substrate, the second plastic encapsulation layer covering the electrical components, the bottom filler, the pre-filling layer and the first rewiring layer.
  • the front side of the first chip faces the first carrier
  • the chip packaging method includes: removing the first carrier to expose the front side of the first chip and the other end of the conductor; and forming a second rewiring layer on the surface of the first plastic encapsulation layer away from the first rewiring layer, the second rewiring layer being electrically connected to the front side of the first chip and the other end of the conductor.
  • the present disclosure also provides a packaging structure.
  • the packaging structure includes a substrate, a prefilled layer, and an electrical component.
  • the first surface of the substrate has a plurality of pads;
  • the prefilled layer is located on the first surface of the substrate and has a plurality of bump placement openings corresponding to the plurality of pads;
  • the electrical component has a plurality of solder bumps and is mounted on the prefilled layer, and each solder bump of the electrical component is located in a corresponding bump placement opening in the plurality of bump placement openings and is connected to a corresponding pad in the plurality of pads.
  • a surface of the electrical component close to the pre-filled layer has a distance greater than zero from the pre-filled layer; the packaging structure also includes a bottom filler, which is filled between the pre-filled layer and the electrical component and extends from the bottom of the electrical component to wrap around a portion of the side wall of the electrical component.
  • the packaging structure further includes a second plastic packaging layer, wherein the second plastic packaging layer is formed on the first The surface covers the electrical components and the pre-filled layer; both the pre-filled layer and the second plastic packaging layer have filler particles, and the size of the filler particles in the pre-filled layer is smaller than the size of the filler particles in the second plastic packaging layer.
  • the substrate includes a first chip, a conductor, a first plastic encapsulation layer and a first rewiring layer; the first chip and the conductor are embedded in the first plastic encapsulation layer, and the first plastic encapsulation layer at least covers the side walls of the first chip and the side walls of the conductor; the first rewiring layer is formed on the surface of the first plastic encapsulation layer and is electrically connected to one end of the conductor, and the first rewiring layer includes the multiple pads.
  • the packaging structure further includes a second rewiring layer, which is formed on a surface of the first plastic packaging layer away from the first rewiring layer and is electrically connected to the other end of the conductor and the first chip.
  • the first surface of the substrate has a plurality of solder pads
  • a pre-filled layer is located on the first surface of the substrate
  • the pre-filled layer has a plurality of bump placement openings
  • the plurality of bump placement openings respectively expose the plurality of solder pads
  • an electrical component is mounted on the pre-filled layer
  • each solder bump of the electrical component is embedded in the corresponding bump placement opening and connected to the corresponding solder pad.
  • 1 to 4 are schematic diagrams of the process of a conventional chip packaging method.
  • FIG. 5 is a picture showing the disadvantage of short circuit between adjacent solder bumps of a chip when the chip is packaged using the existing chip packaging method.
  • FIG. 6 is a flow chart of a chip packaging method according to an embodiment of the present disclosure.
  • FIGS. 7 to 26 are schematic diagrams of the step-by-step process of a chip packaging method according to an embodiment of the present disclosure.
  • FIG. 27 is a schematic diagram of a packaging structure according to an embodiment of the present disclosure.
  • FIG. 1 to FIG. 4 100-substrate; 101-pad; 102-solder paste; 103-chip; 103a-solder bump; 104-bottom filler; (FIG. 7 to FIG. 27) 200-substrate; 201-first carrier; 202-first adhesive layer; 203-first chip; 204- Conductor; 204a-conductive structure; 204b-molding material; 205-first plastic layer; 206-first rewiring layer; 206a-first circuit layer; 206b-first dielectric layer; 206c-second circuit layer; 206d-pad; 206e-second dielectric layer; 207-solder paste; 208-passive device; 209-prefilled layer; 209a-bump placement opening; 210-electrical component; 210a-solder bump; 211-second plastic layer; 212-bottom filler; 213-second carrier; 214-second adhesive layer; 215-second rewiring Line layer; 215
  • FIGs 1 to 4 are schematic diagrams of the process of an existing chip packaging method.
  • the existing chip packaging method mainly includes the following steps: as shown in Figure 1, printing solder paste 102 on a pad 101 of a substrate 100; as shown in Figure 2, flipping a chip 103 on the pad 101; as shown in Figure 3, performing reflow soldering, soldering a solder bump 103a (or solder joint) of the chip on the pad 101; as shown in Figure 4, filling a bottom filler 104, and curing the bottom filler 104.
  • the bottom filling of the chip 103 is easily incomplete due to the influence of factors such as the fluidity and viscosity of the bottom filler 104.
  • a void 105 is easily formed between two adjacent solder bumps of the chip 103.
  • the solder bump 103a of the chip will melt again.
  • the molten material will flow through the void 105 and cause the adjacent solder bumps of the chip to be connected, thereby causing a chip short circuit defect, as shown in the circle of FIG5.
  • FIG6 is a flow chart of a chip packaging method according to an embodiment of the present disclosure. As shown in FIG6 , the chip packaging method according to the present embodiment includes:
  • steps in the flowchart of FIG. 6 are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least one of the steps in FIG. 6 A part of the steps may include multiple steps or multiple stages. These steps or stages do not necessarily have to be executed at the same time, but can be executed at different times. The execution order of these steps or stages does not necessarily have to be sequentially, but can be executed in rotation or alternation with other steps or at least part of the steps or stages in other steps.
  • Figures 7 to 26 are schematic diagrams of the step-by-step process of a chip packaging method according to an embodiment of the present disclosure.
  • Figure 27 is a schematic diagram of a packaging structure according to an embodiment of the present disclosure. The chip packaging method according to the present embodiment is described below in conjunction with Figures 6 to 27.
  • a substrate 200 is provided, and a first surface of the substrate 200 has a plurality of pads 206d.
  • the step of providing a substrate may include the following process.
  • a first carrier 201 is provided, and a first chip 203 and a conductor 204 are mounted on the first carrier 201 .
  • a first adhesive layer 202 may be formed on the first carrier 201, and the first adhesive layer 202 is used to adhere the first chip 203 and the conductor 204 to the first carrier 201.
  • the first adhesive layer 202 may be a pyrolytic double-sided adhesive, but is not limited thereto.
  • multiple first chips 203 and multiple conductors 204 may be mounted simultaneously on the first carrier 201.
  • the multiple first chips 203 may be different chips, for example, the structures and/or sizes of the multiple first chips 203 may be different, but not limited thereto.
  • the conductor 204 may include a conductive structure 204a and a plastic encapsulation material 204b that plastic encapsulates the conductive structure 204a, and part of the conductive structure 204a is exposed from the plastic encapsulation material 204b.
  • the conductor 204 is a plastic encapsulated structure and can be made in advance before chip packaging. In this embodiment, the conductor 204 is used as an interconnection channel between upper and lower chips, which helps to reduce the difficulty of packaging process, improve the conductive reliability of the packaging structure, and improve product yield.
  • the conductive structure 204a may include but is not limited to a plurality of copper pillars.
  • the plastic encapsulation material 204b may be an epoxy plastic encapsulation material.
  • the front side of the first chip 203 may have a convex point (not shown in the figure), and the convex point of the first chip 203 may include, for example, a pad and/or a micro-convex structure.
  • the first chip 203 is mounted on the first carrier 201 with the front side facing downward, and the pad and/or the micro-convex structure on the front side of the first chip 203 can be exposed by subsequently separating from the first carrier 201 and the first adhesive layer 202, so that the convex point on the front side of the first chip 203 can be effectively protected, but the present invention is not limited thereto.
  • the first chip 203 may also be mounted on the first carrier 201 with the back side facing downward, and the convex point on the front side of the first chip 203 may be exposed subsequently by laser punching or the like.
  • a first plastic encapsulation layer 205 is formed on the first carrier board 201.
  • the sidewalls of the first chip 203 and the conductor 204 are less covered.
  • the method for forming the first plastic encapsulation layer 205 on the first carrier 201 may include: referring to FIG8 , forming the first plastic encapsulation layer 205 on the first carrier 201, the first plastic encapsulation layer 205 covering the side and back sides of the first chip 203 and the end face of the conductor 204 away from the first carrier 201; removing part of the thickness of the first plastic encapsulation layer 205 by grinding or etching, exposing the end face of the conductor 204 away from the first carrier 201.
  • part of the thickness of the conductor 204 may be simultaneously ground and removed, which helps to improve the applicability of the conductor 204, and thus does not need to design or manufacture a conductor for each product, which helps to reduce packaging costs.
  • the material of the first plastic layer 205 is the same as the material of the plastic material 204b of the conductor 204.
  • the material of the first plastic layer 205 can be epoxy mold compound (EMC).
  • a first rewiring layer 206 is formed on the first plastic packaging layer 205 .
  • the first rewiring layer 206 is electrically connected to one end of the conductor 204 .
  • the first rewiring layer 206 includes the plurality of pads 206 d .
  • the method for forming the first redistribution layer 206 may include: as shown in FIG. 9, forming a first wiring layer 206a on a surface of the first plastic encapsulation layer 205 away from the first carrier 201, the first wiring layer 206a is electrically connected to one end of the conductor 204, and the first wiring layer 206a may include a bump away from the first plastic encapsulation layer 205; as shown in FIG.
  • a first dielectric layer 206b on a surface of the first plastic encapsulation layer 205 away from the first carrier 201, the first dielectric layer 206b covers the first wiring layer 206a, and removing a portion of the thickness of the first dielectric layer 206b by grinding or etching, etc., to expose at least a portion of the first wiring layer 206a away from the first plastic encapsulation layer 205 Surface, for example, the end face of the bump of the first circuit layer 206a is exposed; as shown in FIG11, a second circuit layer 206c is formed on the surface of the first dielectric layer 206b away from the first plastic encapsulation layer 205, the second circuit layer 206c is interconnected with the first circuit layer 206a, and a plurality of pads 206d are formed on the second circuit layer 206c; as shown in FIG12, a second dielectric layer 206e is formed on the surface of the first dielectric layer 206b away from the first plastic encapsulation layer 205, the second di
  • a first rewiring layer 206 having more than three wiring layers can be formed.
  • the substrate 200 may include a first chip 203, a conductor 204, and a first redistribution layer 206, but is not limited thereto.
  • the first surface of the substrate 200 may be a surface of the first redistribution layer 206 away from the first plastic encapsulation layer 205.
  • the substrate 200 may be a printed circuit board (PCB). PCB), and can also be a rewiring layer formed on a carrier board.
  • PCB printed circuit board
  • passive devices 208 may be mounted on a portion of the pads 206 d .
  • the method of installing the passive component 208 on a partial number of pads 206d may include: as shown in FIG. 13, printing solder paste 207 on a partial number of pads 206d; as shown in FIG. 14, mounting the passive component 208 on the pad 206d printed with the solder paste 207, for example, pasting the solder end of the passive component 208 on the solder paste 207; as shown in FIG. 15, performing a reflow soldering process so that the solder end of the passive component 208 is melted and soldered to the corresponding pad 206d.
  • the number of passive components 208 mounted on the substrate 200 may be more than two, but is not limited thereto.
  • a pre-filled layer 209 is formed on the first surface of the substrate 200.
  • the pre-filled layer 209 has a plurality of bump placement openings 209a, and the plurality of bump placement openings 209a respectively expose the plurality of pads 206d.
  • the pre-filled layer 209 can be filled between the passive devices 208.
  • the method of forming the pre-filled layer 209 on the first surface of the substrate 200 may include: forming the pre-filled layer 209 on the first surface of the substrate 200; and forming a plurality of bump placement openings 209a in the pre-filled layer 209 by laser drilling or the like.
  • the thickness of the pre-filled layer 209 can be selected according to the height of the solder bumps of the subsequently mounted electrical component.
  • the width of the bump placement opening 209a in the pre-filled layer 209 can be selected according to the width of the pad 206d and the width of the solder bump of the electrical component.
  • both the pre-filled layer 209 and the encapsulation material (EMC) contain filler particles, which are usually inorganic filler particles. Moreover, the filler particles in the pre-filled layer 209 are smaller than the filler particles in the encapsulation material. Therefore, the probability of voids in the pre-filled layer 209 formed by pre-filling is smaller, which is beneficial to reducing the probability of short circuits between adjacent solder bumps of electrical components.
  • the pre-filled layer 209 may be a non-conductive film, the material of which may be, for example, BPA epoxy resin, BPF epoxy resin, aliphatic epoxy resin, alicyclic epoxy resin, etc. It may also include powders such as silicon carbide, aluminum nitride, etc. as inorganic fillers, but is not limited thereto.
  • the method of forming the pre-filled layer 209 on the first surface of the substrate 200 may include: forming the pre-filled layer 209 having a plurality of bump placement openings 209a on the first surface of the substrate 200 by means of spot coating or printing.
  • spot coating method may also be referred to as “glue dispensing method”.
  • a filler may be injected onto the first surface of the substrate 200 by means of a syringe or a syringe, and the plurality of The positions above the pads 206d are reserved, that is, the positions above the plurality of pads 206d are not coated with filler, so that a pre-filled layer having a plurality of bump placement openings is formed.
  • an electrical component 210 is installed on the pre-filled layer 209, and the electrical component 210 has multiple solder bumps 210a. Each solder bump 210a of the electrical component is embedded in the corresponding bump placement opening 209a and connected to the corresponding pad 206d.
  • the method of installing the electrical component 210 on the pre-filled layer 209 may include: as shown in Figure 17, coating the solder paste 207 on the pad 206d within the multiple bump placement openings 209a; as shown in Figure 19, mounting the electrical component 210 on the substrate 200, each solder bump 210a of the electrical component 210 is embedded in the corresponding bump placement opening 209a and contacts with the coated solder paste 207; as shown in Figure 20, performing a reflow soldering process, and the solder bump 210a of the electrical component is melted and soldered on the corresponding pad 206d.
  • the electrical component 210 may be a chip that has been packaged at the chip level, and the electrical component 210 may include a chip body, a rewiring layer, solder bumps, and a plastic packaging material, but is not limited thereto. As shown in FIG. 18 , the electrical component 210 may be a chip that has solder bumps 210a directly made on the chip. The electrical component 210 may also be an inductor component with solder bumps, etc.
  • the solder bump 210a of the electrical component is, for example, a solder ball connected to a pad, or an outer convex pad including an outer solder layer.
  • the solder bump 210a of the electrical component will melt during the reflow soldering process, and the solder bump 210a can be called a solder joint.
  • the material of the solder bump 210a of the electrical component includes, but is not limited to, tin.
  • a plurality of electrical components 210 may be mounted on the pre-filled layer 209 , and the sizes and/or structures of the plurality of electrical components 210 may be different.
  • a second plastic encapsulation layer 211 may be formed on the first surface of the substrate 200, and the second plastic encapsulation layer 211 covers the electrical component 210, the pre-filled layer 209, the first rewiring layer 206, and the passive device 208.
  • the second plastic encapsulation layer 211 is directly formed to encapsulate the electrical component 210 and the passive device 208 without filling the bottom filler, which helps to simplify the process and save costs.
  • the bottom of the electrical component 210 can be filled with a bottom filler 212, and the bottom filler 212 is at least filled between the electrical component 210 and the pre-filled layer 209, and then the bottom filler 212 is cured.
  • a second plastic encapsulation layer 211 is formed on the first surface of the substrate 200, and the second plastic encapsulation layer 211 covers the electrical component 210, the bottom filler 212, the pre-filled layer 209 and the first rewiring layer 206.
  • the bottom filler 212 is first filled at the bottom of the electrical component 210, and then the second plastic sealing layer 211 is formed to seal the electrical component 210.
  • This can reduce the probability of voids existing at the bottom of the electrical component 210 after plastic sealing, that is, it can be achieved that the electrical component 210 has smaller voids or no voids at the bottom after plastic sealing.
  • the filling effect at the bottom of the electrical component 210 is better, and the risk of short circuit between adjacent solder bumps of the electrical component 210 is further reduced.
  • the material properties of the bottom filler 212 may be the same as those of the pre-filled layer 209.
  • the material of the pre-filled layer 209 is the same as that of the bottom filler 212, so that the pre-filled layer 209 and the bottom filler 212 have the same thermal expansion coefficient, which is beneficial to avoid the problem of cracking between the pre-filled layer 209 and the bottom filler 212 after thermal shock, thereby improving the reliability of the product.
  • a second carrier 213 can be set on the surface of the second plastic encapsulation layer 211 away from the first re-wiring layer 206, and a second adhesive layer 214 is formed between the second carrier 213 and the second plastic encapsulation layer 211.
  • the first carrier 201 and the first adhesive layer 202 are removed to expose the front side of the first chip 203 and the other end of the conductor 204; as shown in Figure 26, a second re-wiring layer 215 is formed on the surface of the first plastic encapsulation layer 205 away from the first re-wiring layer 206, and the second re-wiring layer 215 is electrically connected to the front side of the first chip 203 and the other end of the conductor 204, and the conductor 204 serves as a conductive channel between the first re-wiring layer 206 and the second re-wiring layer 215.
  • a method for forming a second rewiring layer 215 on a surface of the first plastic encapsulation layer 205 away from the first rewiring layer 206 may include: as shown in FIG. 24 , forming a first insulating layer 215a on a surface of the first plastic encapsulation layer 205 away from the first rewiring layer 206, and forming a plurality of blind holes 215b in the first insulating layer by laser drilling or the like, wherein the plurality of blind holes 215b expose the front surface of the first chip 203 and the conductive structure of the conductive body 204; as shown in FIG.
  • a second insulating layer 215e is formed covering the conductive graphic layer 215c and the plurality of bumps 215d, and a portion of the thickness of the second insulating layer 215e is removed by grinding to expose the end surfaces of the plurality of bumps 215d.
  • Both the first insulating layer 215a and the second insulating layer 215e can be a resin film, a build-up film (Ajinomoto Build-up film, ABF) or a PI film (Polyimide Film), etc.
  • the second carrier 213 and the second adhesion layer 214 are removed, and the solder ball 216 is implanted on the bump 215d; a cutting process can be performed to cut the second plastic encapsulation layer 211, the first rewiring layer 206, the first plastic encapsulation layer 205 and the second rewiring layer 215 to obtain multiple packaging particles.
  • the present disclosure also provides a packaging structure, which can be formed using the above chip packaging method.
  • the packaging structure includes a substrate 200, a pre-filled layer 209 and an electrical component 210.
  • the first surface of the substrate 200 has a plurality of pads 206d;
  • the pre-filled layer 209 is located on the first surface of the substrate 200 and has a plurality of bump placement openings 209a corresponding to the plurality of pads 206d;
  • the electrical component 210 has at least a plurality of solder bumps 210a and is mounted on the pre-filled layer 209, and each solder bump 210a of the electrical component 210 is located in a corresponding bump placement opening 209a in the plurality of bump placement openings 209a and is connected to a corresponding pad 206d in the plurality of pads 206d.
  • the surface of the electrical component 210 close to the pre-filled layer 209 has a spacing greater than zero from the pre-filled layer 209; in other words, the upper surface of the pre-filled layer 209 does not exceed the lower surface of the electrical component 210, and the upper surface of the pre-filled layer 209 is opposite to the lower surface of the electrical component 210.
  • the thickness of the pre-filled layer 209 can be less than the thickness of the solder bump 210a.
  • the package structure may further include a second plastic encapsulation layer 211, which is formed on the first surface of the substrate 200 and covers the electrical component 210 and the pre-filled layer 209.
  • Both the pre-filled layer 209 and the second plastic encapsulation layer 211 have filler particles, and the size of the filler particles in the pre-filled layer 209 is smaller than the size of the filler particles in the second plastic encapsulation layer 211, so that the probability of having voids in the pre-filled layer 209 is small, which is beneficial to reducing the probability of short circuits between adjacent solder bumps 210a of the electrical component 210.
  • the packaging structure may further include a bottom filler 212, wherein the bottom filler 212 is filled between the pre-filled layer 209 and the electrical component 210 and extends from the bottom of the electrical component 210 to wrap a portion of the side wall of the electrical component 210, that is, the top surface of the bottom filler 212 is not lower than the lower surface of the electrical component 210; the second plastic layer 211 also covers the bottom filler 212.
  • the bottom filler 212 contains filler particles, and the size of the filler particles in the bottom filler 212 is smaller than the size of the filler particles in the second plastic layer 211.
  • Filling the bottom filler 212 in the second plastic layer 211 and at the bottom of the electrical component 210 can reduce the probability of voids at the bottom of the electrical component 210, improve the filling effect at the bottom of the electrical component 210, and reduce the electrical component 210.
  • the risk of short circuits between adjacent solder bumps is, but is not limited to, this.
  • the material of the bottom filler 212 can be the same as the material of the pre-filled layer 209, so that the thermal expansion coefficients of the pre-filled layer 209 and the bottom filler 212 are the same, which is conducive to avoiding the problem of cracking between the pre-filled layer 209 and the bottom filler 212 after thermal shock, but the present invention is not limited thereto.
  • the material of the bottom filler 212 can be different from the material of the pre-filled layer 209.
  • a bottom filler may not be provided inside the second plastic encapsulation layer 211 and at the bottom of the electrical component 210 . Due to the blocking effect of the pre-filled layer 209 , adjacent solder bumps 210 a of the electrical component will not short-circuit due to re-melting flow during reflow.
  • the substrate 200 may include a first chip 203, a conductor 204, a first plastic encapsulation layer 205 and a first rewiring layer 206; the first chip 203 and the conductor 204 are embedded in the first plastic encapsulation layer 205, and the first plastic encapsulation layer 205 at least covers the side walls of the first chip 203 and the side walls of the conductor 204; the first rewiring layer 206 is formed on the surface of the first plastic encapsulation layer 205, and is electrically connected to one end of the conductor 204, and the first rewiring layer 206 includes the multiple pads 206d; the pre-filled layer 209 is located on the first rewiring layer 206.
  • the packaging structure may further include a second rewiring layer 215 , which is formed on a surface of the first plastic layer 205 away from the first rewiring layer 206 and is electrically connected to the other end of the conductor 204 and the first chip 203 .
  • the first surface of the substrate 200 has a plurality of pads 206d
  • the pre-filled layer 209 is located on the first surface of the substrate 200
  • the pre-filled layer 209 has a plurality of bump placement openings 209a
  • the plurality of bump placement openings 209a respectively expose the plurality of pads 206d
  • the electrical component 210 is mounted on the pre-filled layer 209
  • each solder bump 210a of the electrical component 210 is embedded in the corresponding bump placement opening 209a and connected to the corresponding pad 206d.
  • the pre-filled layer 209 acts as a dam for the solder bumps 210a of the electrical component, so that there are no voids between the adjacent solder bumps 210a of the electrical component, which can prevent the problem of short circuit of the electrical component caused by the solder bumps 210a of the electrical component melting again and flowing through the voids when reflowing again, which is conducive to improving the yield of the product.
  • spatial relationship terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the figure If the device is turned over, elements or features described as “below” or “beneath” or “under” other elements would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “beneath” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

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Abstract

本公开提供一种芯片封装方法。所述芯片封装方法包括：提供基板，基板的第一表面具有多个焊盘；在基板的第一表面形成预填充层，预填充层中具有多个凸点放置开口，多个凸点放置开口分别露出多个焊盘；以及将电气元件安装在预填充层上，电气元件具有多个焊料凸点，电气元件的每个焊料凸点嵌入多个凸点放置开口中对应的凸点放置开口内并与多个焊盘中对应的焊盘连接。如此预填充层对电气元件的焊料凸点起到了挡坝的作用，有利于改善芯片相邻焊料凸点短路不良的问题，提高产品的良率。本公开还提供一种封装结构。所述封装结构中，基板和电气元件之间设置有预填充层。

Description

芯片封装方法及封装结构 技术领域
本公开涉及封装技术领域，特别涉及一种芯片封装方法及一种封装结构。
背景技术
现有的芯片封装方法主要包括以下步骤：将焊膏印刷在基板的焊盘上；将芯片倒装在焊盘上；进行回流焊接，芯片的焊料凸点(或称为焊点)焊接在焊盘上；进行底部填充剂填充，并对底部填充剂进行固化。
在底部填充剂填充作业过程中，受底部填充剂的流动性及粘性等因子的影响，容易造成芯片底部填充不完全的现象，芯片相邻两个焊料凸点之间容易出现空洞。当再次回流时，芯片的焊料凸点会再次熔融，此时，熔融材料会通过空洞流通而导致芯片相邻的焊料凸点连接，进而造成芯片短路不良。
发明内容
本公开提供一种芯片封装方法。本公开还提供一种封装结构。
本公开一方面提供一种芯片封装方法。所述芯片封装方法包括：提供基板，所述基板的第一表面具有多个焊盘；在所述基板的第一表面形成预填充层，所述预填充层中具有多个凸点放置开口，所述多个凸点放置开口分别露出所述多个焊盘；以及将电气元件安装在所述预填充层上，所述电气元件具有多个焊料凸点，所述电气元件的每个焊料凸点嵌入所述多个凸点放置开口中对应的凸点放置开口内并与所述多个焊盘中对应的焊盘连接。
可选的，所述在所述基板的第一表面形成预填充层，包括：在所述基板的第一表面形成预填充层；以及通过镭射打孔的方式在所述预填充层中形成所述多个凸点放置开口。
可选的，所述在所述基板的第一表面形成预填充层，包括：采用点涂或印刷的方式在所述基板的第一表面形成具有所述多个凸点放置开口的预填充层。
可选的，所述将电气元件安装在所述预填充层上，包括：在所述多个凸点放置开口内的所述多个焊盘上涂覆焊膏；将所述电气元件贴装在所述基板上，所述电气元件的每个焊料凸点嵌入所述对应的凸点放置开口内并与涂覆的所述焊膏接触；以及执行回流焊 接工艺，所述电气元件的每个焊料凸点熔融并焊接在所述对应的焊盘上。
可选的，所述提供基板，包括：提供第一载板，将第一芯片和导电体贴装在所述第一载板上，所述导电体包括导电结构以及塑封所述导电结构的塑封材料，且部分所述导电结构从所述塑封材料中露出；在所述第一载板上形成第一塑封层，所述第一塑封层至少包覆所述第一芯片的侧壁和所述导电体的侧壁；以及在所述第一塑封层上形成第一再布线层，所述第一再布线层与所述导电体的一端电连接，所述第一再布线层包括所述多个焊盘。
可选的，所述芯片封装方法包括：所述将电气元件安装在所述预填充层上之后，在所述电气元件的底部填充底部填充剂，所述底部填充剂至少填充在所述电气元件与所述预填充层之间；以及对所述底部填充剂进行固化。
可选的，所述预填充层与所述底部填充剂的材料相同。
可选的，所述芯片封装方法包括：所述对所述底部填充剂进行固化之后，在所述基板的第一表面上形成第二塑封层，所述第二塑封层覆盖所述电气元件、所述底部填充剂、所述预填充层和所述第一再布线层。
可选的，所述将第一芯片和导电体贴装在所述第一载板上的步骤中，所述第一芯片的正面朝向所述第一载板；
所述在所述基板的第一表面上形成第二塑封层之后，所述芯片封装方法包括：去除所述第一载板，露出所述第一芯片的正面和所述导电体的另一端；以及在所述第一塑封层远离所述第一再布线层的表面形成第二再布线层，所述第二再布线层与所述第一芯片的正面和所述导电体的另一端电连接。
本公开还提供一种封装结构。所述封装结构包括基板、预填充层和电气元件。所述基板的第一表面具有多个焊盘；所述预填充层，位于所述基板的第一表面上，具有位置对应于所述多个焊盘的多个凸点放置开口；所述电气元件，具有多个焊料凸点，安装在所述预填充层上，所述电气元件的每个焊料凸点位于所述多个凸点放置开口中对应的凸点放置开口内并与所述多个焊盘中对应的焊盘连接。
可选的，所述电气元件靠近所述预填充层的表面与所述预填充层之间具有大于零的间距；所述封装结构还包括底部填充剂，所述底部填充剂填充在所述预填充层和所述电气元件之间且从所述电气元件的底部延伸包裹所述电气元件的部分侧壁。
可选的，所述封装结构还包括第二塑封层，所述第二塑封层形成在所述基板的第一 表面上，覆盖所述电气元件和所述预填充层；所述预填充层和所述第二塑封层中均具有填料颗粒，且所述预填充层中的填料颗粒的尺寸小于所述第二塑封层中的填料颗粒的尺寸。
可选的，所述基板包括第一芯片、导电体、第一塑封层和第一再布线层；所述第一芯片和所述导电体嵌设在所述第一塑封层中，所述第一塑封层至少包覆所述第一芯片的侧壁和所述导电体的侧壁；所述第一再布线层形成在所述第一塑封层的表面，且与所述导电体的一端电连接，所述第一再布线层包括所述多个焊盘。
可选的，所述封装结构还包括第二再布线层，所述第二再布线层形成在所述第一塑封层远离所述第一再布线层的表面，且与所述导电体的另一端和所述第一芯片电连接。
本公开的芯片封装方法和封装结构中，基板的第一表面具有多个焊盘，预填充层位于基板的第一表面上，所述预填充层中具有多个凸点放置开口，所述多个凸点放置开口分别露出所述多个焊盘，电气元件安装在所述预填充层上，且所述电气元件的每个焊料凸点嵌入对应的所述凸点放置开口内并与对应的所述焊盘连接。
附图说明
图1至图4为现有的芯片封装方法的过程示意图。
图5为利用现有的芯片封装方法封装芯片时芯片相邻焊料凸点短路的缺点图片。
图6为本公开一实施例的芯片封装方法的流程图。
图7至图26为本公开一实施例的芯片封装方法的分步骤过程示意图。
图27为本公开一实施例的封装结构的示意图。
附图标记说明：
(图1至图4)100-基板；101-焊盘；102-焊膏；103-芯片；103a-焊料凸点；104-底
部填充剂；
(图7至图27)200-基板；201-第一载板；202-第一粘连层；203-第一芯片；204-
导电体；204a-导电结构；204b-塑封材料；205-第一塑封层；206-第一再布线层；206a-第一线路层；206b-第一介电层；206c-第二线路层；206d-焊盘；206e-第二介电层；207-焊膏；208-无源器件；209-预填充层；209a-凸点放置开口；210-电气元件；210a-焊料凸点；211-第二塑封层；212-底部填充剂；213-第二载板；214-第二粘连层；215-第二再布 线层；215a-第一绝缘层；215b-盲孔；215c-导电图形层；215d-凸块；215e-第二绝缘层；216-锡球。
具体实施方式
以下结合附图和具体实施例对本公开提出的芯片封装方法和封装结构作进一步详细说明。根据下面说明，本公开的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本公开实施例的目的。
图1至图4为现有的芯片封装方法的过程示意图。现有的芯片封装方法主要包括以下步骤：如图1所示，将焊膏102印刷在基板100的焊盘101上；如图2所示，将芯片103倒装在焊盘101上；如图3所示，进行回流焊接，芯片的焊料凸点103a(或称为焊点)焊接在焊盘101上；如图4所示，进行底部填充剂104填充，并对底部填充剂104进行固化。
在底部填充剂104填充作业过程中，受底部填充剂104的流动性及粘性等因子的影响，容易造成芯片103底部填充不完全的现象，如图4所示，芯片103相邻两个焊料凸点之间容易出现空洞105。当再次回流时，芯片的焊料凸点103a会再次熔融，此时，熔融材料会通过空洞105流通而导致芯片相邻的焊料凸点连接，进而造成芯片短路不良，如图5的圆框内所示。
为了改善封装结构中电气元件短路不良的问题，本实施例提供一种芯片封装方法。图6为本公开一实施例的芯片封装方法的流程图。如图6所示，本实施例的芯片封装方法包括：
S1，提供基板，所述基板的第一表面具有多个焊盘；
S2，在所述基板的第一表面形成预填充层，所述预填充层中具有多个凸点放置开口，所述多个凸点放置开口分别露出所述多个焊盘；
S3，将电气元件安装在所述预填充层上，所述电气元件具有多个焊料凸点，所述电气元件的每个焊料凸点嵌入多个凸点放置开口中对应的凸点放置开口内并与所述多个焊盘中对应的焊盘连接。
应该理解的是，虽然图6的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图6中的至少 一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
图7至图26为本公开一实施例的芯片封装方法的分步骤过程示意图。图27为本公开一实施例的封装结构的示意图。以下结合图6至图27来介绍本实施例的芯片封装方法。
如图12所示，提供基板200，所述基板200的第一表面具有多个焊盘206d。所述提供基板的步骤可以包括以下过程。
如图7所示，提供第一载板201，将第一芯片203和导电体204贴装在所述第一载板201上。
具体的，第一载板201上可以形成有第一粘连层202，第一粘连层202用于将第一芯片203和导电体204粘贴在第一载板201上。第一粘连层202可以为热解双面胶，但不限于此。
为了提高封装效率，可以将多个第一芯片203和多个导电体204同时贴装在第一载板201上。多个第一芯片203可以是不完全相同的芯片，例如多个第一芯片203的结构和/或尺寸可以不完全相同，但不限于此。
所述导电体204可以包括导电结构204a以及塑封所述导电结构204a的塑封材料204b，且部分所述导电结构204a从所述塑封材料204b中露出。所述导电体204为塑封后的结构，可在芯片封装前提前制作，本实施例使用导电体204作为上下层芯片的互联通道，有助于降低封装工艺难度、提高封装结构的导电可靠性、以及提高产品良率。所述导电结构204a可以包括但不限于多个铜柱。所述塑封材料204b可以为环氧塑封料。
所述第一芯片203的正面可以具有凸点(图中未示出)，第一芯片203的凸点例如包括焊盘和/或微凸结构。本实施例中，将第一芯片203正面朝下的贴装在第一载板201上，后续通过脱离第一载板201和第一粘连层202即可露出第一芯片203正面上的焊盘和/或微凸结构，如此可以有效地保护第一芯片203正面的凸点，但不限于此。在其它实施例中，第一芯片203也可以背面朝下的贴装在第一载板201上，后续可以通过镭射打孔等方式露出第一芯片203正面上的凸点。
如图8所示，在所述第一载板201上形成第一塑封层205，所述第一塑封层205至 少包覆所述第一芯片203的侧壁和所述导电体204的侧壁。
在第一载板201上形成第一塑封层205的方法可以包括：参考图8，在第一载板201上形成第一塑封层205，第一塑封层205覆盖第一芯片203的侧面和背面以及覆盖导电体204远离第一载板201的端面；采用研磨或刻蚀等方式去除第一塑封层205的部分厚度，露出导电体204远离第一载板201的端面。在研磨去除第一塑封层205的部分厚度的过程中，可以同时研磨去除导电体204的部分厚度，如此有助于提高导电体204的适用性，进而不需要为每一种产品设计或制作一种导电体，有利于降低封装成本。
为了提高产品的可靠性，避免第一塑封层205与导电体204之间因为热膨胀系数不同而导致的崩裂，第一塑封层205的材料与导电体204的塑封材料204b的材料相同。所述第一塑封层205的材料可以为环氧塑封料(Expoxy Mold Compound，EMC)。
如图12所示，在所述第一塑封层205上形成第一再布线层206，所述第一再布线层206与所述导电体204的一端电连接，所述第一再布线层206包括所述多个焊盘206d。
形成第一再布线层206的方法可以包括：如图9所示，在第一塑封层205远离第一载板201的表面形成第一线路层206a，第一线路层206a与导电体204的一端电连接，第一线路层206a可以包括远离第一塑封层205的凸块；如图10所示，在第一塑封层205远离第一载板201的表面形成第一介电层206b，第一介电层206b覆盖第一线路层206a，通过研磨或刻蚀等方式去除第一介电层206b的部分厚度，至少露出第一线路层206a远离第一塑封层205的部分表面，例如露出第一线路层206a的凸块的端面；如图11所示，在第一介电层206b远离第一塑封层205的表面形成第二线路层206c，第二线路层206c与第一线路层206a互连，并在第二线路层206c上形成多个焊盘206d；如图12所示，在第一介电层206b远离第一塑封层205的表面形成第二介电层206e，第二介电层206e覆盖第二线路层206c和多个焊盘206d，去除第二介电层206e的部分厚度，露出多个焊盘206d远离第一塑封层205的表面。
需要说明的是，形成第二线路层206c之后，通过重复形成介电层以及在介电层上方形成与下层线路层互联的上层线路层的步骤，可以形成具有三层以上的线路层的第一再布线层206。
本实施例中，如图12所示，基板200可以包括第一芯片203、导电体204和第一再布线层206，但不限于此。基板200的第一表面可以为第一再布线层206远离第一塑封层205的表面。在其它实施例中，基板200可以为印刷电路板(Printed Circuit Board， PCB)，还可以在为形成在载板上的再布线层等。
在形成第一再布线层206之后，如图15所示，可以在部分数量的所述焊盘206d上安装无源器件208。
具体的，在部分数量的焊盘206d上安装无源器件208的方法可以包括：如图13所示，在部分数量的焊盘206d上印刷焊膏207；如图14所示，在印刷过焊膏207的焊盘206d上贴装无源器件208，例如将无源器件208的焊端粘贴在焊膏207上；如图15所示，执行回流焊接工艺，使得所述无源器件208的焊端熔融并焊接在对应的焊盘206d上。
在基板200上安装的无源器件208的数量可以为两个以上，但不限于此。
安装无源器件208之后，如图16所示，在所述基板200的第一表面形成预填充层209。所述预填充层209中具有多个凸点放置开口209a，所述多个凸点放置开口209a分别露出所述多个焊盘206d。如图16所示，预填充层209可以填充在无源器件208之间。
一些实施例中，在所述基板200的第一表面形成预填充层209的方法可以包括：在所述基板200的第一表面形成预填充层209；通过镭射打孔等方式在所述预填充层209中形成多个凸点放置开口209a。
所述预填充层209的厚度可以根据后续安装的电气元件的焊料凸点的高度选择。预填充层209中的凸点放置开口209a的宽度可以根据焊盘206d的宽度和电气元件的焊料凸点的宽度选择。
需要说明的是，预填充层209中和塑封料(EMC)中均具有填料颗粒，填料颗粒通常为无机填料颗粒，并且，预填充层209中的填料颗粒比塑封料中的填料颗粒小，从而预填充形成的预填充层209中具有空洞的概率较小，有利于降低电气元件的相邻焊料凸点之间发生短路的概率。
所述预填充层209可以为非导电膜，非导电膜的材料例如为BPA环氧树脂、BPF环氧树脂、脂肪族环氧树脂、脂环族环氧树脂等，还可以包括诸如碳化硅、氮化铝等的粉末作为无机填充剂，但不限于此。
一些实施例中，在基板200的第一表面形成预填充层209的方法可以包括：采用点涂或印刷的方式在所述基板200的第一表面形成具有多个凸点放置开口209a的预填充层209。所谓“点涂的方式”也可以称为“点胶的方式”，在点涂形成预填充层209的过程中，可以通过注射器或针筒等设备将填充剂注射到基板200的第一表面上，且多个 焊盘206d上方的位置预留出来，即多个焊盘206d上方的位置不涂覆填充剂，形成具有多个凸点放置开口的预填充层。
形成预填充层209之后，如图20所示，将电气元件210安装在所述预填充层209上，所述电气元件210具有多个焊料凸点210a，所述电气元件的每个焊料凸点210a嵌入对应的所述凸点放置开口209a内并与对应的所述焊盘206d连接。
具体的，将电气元件210安装在所述预填充层209上的方法可以包括：如图17所示，在所述多个凸点放置开口209a内的所述焊盘206d上涂覆焊膏207；如图19所示，将所述电气元件210贴装在所述基板200上，所述电气元件210的每个焊料凸点210a嵌入对应的所述凸点放置开口209a内并与涂覆的焊膏207接触；如图20所示，执行回流焊接工艺，所述电气元件的焊料凸点210a熔融并焊接在对应的所述焊盘206d上。
参考图19所示，电气元件210可以为进行了芯片级封装的芯片，电气元件210可以包括芯片本体、再布线层、焊料凸点和塑封材料，但不限于此。如图18所示，电气元件210可以是直接在芯片上制作了焊料凸点210a的芯片。电气元件210还可以是具有焊料凸点的电感元件等。
电气元件的焊料凸点210a例如为与焊盘连接的焊球，或者为包括外部焊料层的外凸焊盘。电气元件的焊料凸点210a在回流焊接工艺中会熔融，焊料凸点210a可以称为焊点。作为示例，电气元件的焊料凸点210a的材料包括但不限于锡。
参考图19和图20所示，将电气元件210安装在所述预填充层209上的步骤中，可以将多个电气元件210安装在预填充层209上，多个电气元件210的尺寸和/或结构可以不同。
一些实施例中，如图21所示，将电气元件210安装在所述预填充层209上之后，可以在所述基板200的第一表面上形成第二塑封层211，所述第二塑封层211覆盖所述电气元件210、所述预填充层209、所述第一再布线层206和无源器件208。如此不填充底部填充剂而直接形成第二塑封层211塑封电气元件210和无源器件208，有助于简化工艺和节约成本，且如此即使第二塑封层211塑封电气元件210时电气元件210底部存在空洞，但在预填充层209的阻挡作用下，电气元件的相邻焊料凸点210a在再次回流时也不会由于再次熔融流动而发生短路不良。
塑封料中和底部填充剂中均具有填料颗粒，且塑封料中的填料颗粒较底部填充剂中的填料颗粒大，从而在固化前塑封料的流动性和粘性没有底部填充剂好，用塑封料进行 底部填充时，芯片底部容易有较大的空洞。因此，一些实施例中，将电气元件210安装在所述预填充层209上之后，如图22所示，可以在所述电气元件210的底部填充底部填充剂212，所述底部填充剂212至少填充在所述电气元件210与所述预填充层209之间，然后对所述底部填充剂212进行固化。接着，如图23所示，在所述基板200的第一表面上形成第二塑封层211，所述第二塑封层211覆盖所述电气元件210、所述底部填充剂212、所述预填充层209和所述第一再布线层206。如此首先在电气元件210的底部填充底部填充剂212，再形成第二塑封层211塑封电气元件210，可以减小电气元件210塑封后底部存在空洞的概率，即可以实现电气元件210塑封后底部有较小的空洞或者没有空洞，电气元件210底部的填充效果较好，进一步降低了电气元件210相邻焊料凸点之间短路的风险。
底部填充剂212的材料属性可以与所述预填充层209的材料属性相同。优选的，预填充层209的材料与底部填充剂212的材料相同，如此预填充层209和底部填充剂212的热膨胀系数相同，有利于避免冷热冲击后预填充层209和底部填充剂212之间出现崩裂的问题，提高产品的可靠性。
在所述基板200的第一表面上形成第二塑封层211之后，参考图23和图26所示，可以在第二塑封层211远离第一再布线层206的表面设置第二载板213，第二载板213和第二塑封层211之间形成有第二粘连层214，去除所述第一载板201和第一粘连层202，露出所述第一芯片203的正面和所述导电体204的另一端；如图26所示，在所述第一塑封层205远离所述第一再布线层206的表面形成第二再布线层215，所述第二再布线层215与所述第一芯片203的正面和所述导电体204的另一端电连接，导电体204作为第一再布线层206和第二再布线层215之间的导通通道。
示例性的，在第一塑封层205远离第一再布线层206的表面形成第二再布线层215的方法可以包括：如图24所示，在第一塑封层205远离第一再布线层206的表面形成第一绝缘层215a，并通过镭射打孔等方式在第一绝缘层中形成多个盲孔215b，多个盲孔215b露出第一芯片203的正面和导电体204的导电结构；如图25所示，在第一绝缘层215a上形成导电图形层215c，导电图形层215c填充多个盲孔215b并覆盖多个盲孔215b的内表面，导电图形层215c与第一芯片203的正面和导电体204的另一端电连接；在导电图形层215c上形成多个凸块215d；如图26所示，形成覆盖导电图形层215c和多个凸块215d的第二绝缘层215e，研磨去除第二绝缘层215e的部分厚度，露出多个凸块215d的端面。
第一绝缘层215a和第二绝缘层215e均可以为树脂膜、增层膜(Ajinomoto Build-up film，ABF)或PI膜(Polyimide Film，聚酰亚胺薄膜)等。
参考图26和图27所示，在形成第二再布线层215后，去除第二载板213和第二粘连层214，在凸块215d上植锡球216；可以执行切割工艺，切割第二塑封层211、第一再布线层206、第一塑封层205和第二再布线层215，获得多个封装颗粒。
本公开还提供一种封装结构，所述封装结构可以利用上述的芯片封装方法形成。
如图21和图23所示，所述封装结构包括基板200、预填充层209和电气元件210。具体的，所述基板200的第一表面具有多个焊盘206d；所述预填充层209位于所述基板200的第一表面上，具有位置对应于所述多个焊盘206d的多个凸点放置开口209a；电气元件210具有至少多个焊料凸点210a，且安装在所述预填充层209上，所述电气元件210的每个焊料凸点210a位于多个凸点放置开口209a中对应的凸点放置开口209a内并与多个焊盘206d中对应的焊盘206d连接。
如图21和图23所示，所述电气元件210靠近所述预填充层209的表面与所述预填充层209之间具有大于零的间距；或者说，预填充层209的上表面不超过电气元件210的下表面，预填充层209的上表面与电气元件210的下表面相对。所述预填充层209的厚度可以小于焊料凸点210a的厚度。
如图21和图23所示，所述封装结构还可以包括第二塑封层211，所述第二塑封层211形成在所述基板200的第一表面上，覆盖所述电气元件210和所述预填充层209。所述预填充层209和所述第二塑封层211中均具有填料颗粒，且所述预填充层209中的填料颗粒的尺寸小于所述第二塑封层211中的填料颗粒的尺寸，从而预填充层209中具有空洞的概率较小，有利于降低电气元件210的相邻焊料凸点210a之间发生短路的概率。
一些实施例中，如图23所示，所述封装结构还可以包括底部填充剂212，所述底部填充剂212填充在所述预填充层209和所述电气元件210之间且从所述电气元件210的底部延伸包裹所述电气元件210的部分侧壁，即所述底部填充剂212的顶面不低于所述电气元件210的下表面；第二塑封层211还覆盖所述底部填充剂212。底部填充剂212中具有填料颗粒，底部填充剂212中的填料颗粒尺寸小于第二塑封层211中的填料颗粒尺寸，在第二塑封层211内、电气元件210的底部填充底部填充剂212，可以减小电气元件210底部存在空洞的概率，提高电气元件210底部的填充效果，降低电气元件210 相邻焊料凸点之间短路的风险，但不限于此。
所述底部填充剂212的材料与所述预填充层209的材料可以相同，如此预填充层209和底部填充剂212的热膨胀系数相同，有利于避免冷热冲击后预填充层209和底部填充剂212之间出现崩裂的问题，但不限于此。所述底部填充剂212的材料与所述预填充层209的材料可以不相同。
一些实施例中，如图21所示，第二塑封层211内部、电气元件210的底部可以不设置底部填充剂，由于预填充层209的阻挡作用，电气元件的相邻焊料凸点210a在再次回流时也不会由于再次熔融流动而发生短路不良。
如图27所示，一些实施例中，所述基板200可以包括第一芯片203、导电体204、第一塑封层205和第一再布线层206；所述第一芯片203和所述导电体204嵌设在所述第一塑封层205中，所述第一塑封层205至少包覆所述第一芯片203的侧壁和所述导电体204的侧壁；所述第一再布线层206形成在所述第一塑封层205的表面，与所述导电体204的一端电连接，所述第一再布线层206包括所述多个焊盘206d；所述预填充层209位于所述第一再布线层206上。
所述封装结构还可以包括第二再布线层215，所述第二再布线层215形成在所述第一塑封层205远离所述第一再布线层206的表面，与所述导电体204的另一端和所述第一芯片203电连接。
本实施例的芯片封装方法和封装结构中，基板200的第一表面具有多个焊盘206d，预填充层209位于基板200的第一表面上，所述预填充层209中具有多个凸点放置开口209a，所述多个凸点放置开口209a分别露出所述多个焊盘206d，电气元件210安装在所述预填充层209上，且所述电气元件210的每个焊料凸点210a嵌入对应的凸点放置开口209a内并与对应的焊盘206d连接。如此，预填充层209对电气元件的焊料凸点210a起到了挡坝的作用，使得电气元件相邻的焊料凸点210a之间没有空洞，能够防止再次回流时电气元件的焊料凸点210a再次熔融后通过空洞流动造成电气元件短路不良的问题，有利于提高产品的良率。
需要说明的是，本说明书中空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中 的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
上述描述仅是对本公开较佳实施例的描述，并非对本公开权利范围的任何限定，任何本领域技术人员在不脱离本公开的精神和范围内，都可以利用上述揭示的方法和技术内容对本公开技术方案做出可能的变动和修改，因此，凡是未脱离本公开技术方案的内容，依据本公开的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本公开技术方案的保护范围。

Claims (14)

  1. 一种芯片封装方法，其特征在于，包括：
    提供基板，所述基板的第一表面具有多个焊盘；
    在所述基板的第一表面形成预填充层，所述预填充层中具有多个凸点放置开口，所述多个凸点放置开口分别露出所述多个焊盘；以及
    将电气元件安装在所述预填充层上，所述电气元件具有多个焊料凸点，所述电气元件的每个焊料凸点嵌入所述多个凸点放置开口中对应的凸点放置开口内并与所述多个焊盘中对应的焊盘连接。
  2. 如权利要求1所述的芯片封装方法，其特征在于，所述在所述基板的第一表面形成预填充层，包括：在所述基板的第一表面形成预填充层；以及通过镭射打孔的方式在所述预填充层中形成所述多个凸点放置开口。
  3. 如权利要求1所述的芯片封装方法，其特征在于，所述在所述基板的第一表面形成预填充层，包括：采用点涂或印刷的方式在所述基板的第一表面形成具有所述多个凸点放置开口的预填充层。
  4. 如权利要求1所述的芯片封装方法，其特征在于，所述将电气元件安装在所述预填充层上，包括：
    在所述多个凸点放置开口内的所述多个焊盘上涂覆焊膏；
    将所述电气元件贴装在所述基板上，所述电气元件的每个焊料凸点嵌入所述对应的凸点放置开口内并与涂覆的所述焊膏接触；以及
    执行回流焊接工艺，所述电气元件的每个焊料凸点熔融并焊接在所述对应的焊盘上。
  5. 如权利要求1所述的芯片封装方法，其特征在于，所述提供基板，包括：
    提供第一载板，将第一芯片和导电体贴装在所述第一载板上；所述导电体包括导电结构以及塑封所述导电结构的塑封材料，且部分所述导电结构从所述塑封材料中露出；
    在所述第一载板上形成第一塑封层，所述第一塑封层至少包覆所述第一芯片的侧壁和所述导电体的侧壁；以及
    在所述第一塑封层上形成第一再布线层，所述第一再布线层与所述导电体的一端电连接，所述第一再布线层包括所述多个焊盘。
  6. 如权利要求5所述的芯片封装方法，其特征在于，包括：
    所述将电气元件安装在所述预填充层上之后，在所述电气元件的底部填充底部填充剂，所述底部填充剂至少填充在所述电气元件与所述预填充层之间；以及
    对所述底部填充剂进行固化。
  7. 如权利要求6所述的芯片封装方法，其特征在于，所述预填充层与所述底部填充剂的材料相同。
  8. 如权利要求6所述的芯片封装方法，其特征在于，包括：
    所述对所述底部填充剂进行固化之后，在所述基板的第一表面上形成第二塑封层，所述第二塑封层覆盖所述电气元件、所述底部填充剂、所述预填充层和所述第一再布线层。
  9. 如权利要求8所述的芯片封装方法，其特征在于，所述将第一芯片和导电体贴装在所述第一载板上的步骤中，所述第一芯片的正面朝向所述第一载板；所述在所述基板的第一表面上形成第二塑封层之后，所述芯片封装方法包括：
    去除所述第一载板，露出所述第一芯片的正面和所述导电体的另一端；以及
    在所述第一塑封层远离所述第一再布线层的表面形成第二再布线层，所述第二再布线层与所述第一芯片的正面和所述导电体的另一端电连接。
  10. 一种封装结构，其特征在于，包括：
    基板，所述基板的第一表面具有多个焊盘；
    预填充层，位于所述基板的第一表面上，具有位置对应于所述多个焊盘的多个凸点放置开口；
    电气元件，具有多个焊料凸点，安装在所述预填充层上，所述电气元件的每个焊料凸点位于所述多个凸点放置开口中对应的凸点放置开口内并与所述多个焊盘中对应的焊盘连接。
  11. 如权利要求10所述的封装结构，其特征在于，所述电气元件靠近所述预填充层的表面与所述预填充层之间具有大于零的间距；所述封装结构还包括底部填充剂，所述底部填充剂填充在所述预填充层和所述电气元件之间且从所述电气元件的底部延伸包裹所述电气元件的部分侧壁。
  12. 如权利要求10所述的封装结构，其特征在于，所述封装结构还包括第二塑封层，所述第二塑封层形成在所述基板的第一表面上，覆盖所述电气元件和所述预填充层；所述预填充层和所述第二塑封层中均具有填料颗粒，且所述预填充层中的填料颗粒的尺寸小于所述第二塑封层中的填料颗粒的尺寸。
  13. 如权利要求10所述的封装结构，其特征在于，所述基板包括第一芯片、导电体、第一塑封层和第一再布线层；所述第一芯片和所述导电体嵌设在所述第一塑封层中，所 述第一塑封层至少包覆所述第一芯片的侧壁和所述导电体的侧壁；所述第一再布线层形成在所述第一塑封层的表面，且与所述导电体的一端电连接，所述第一再布线层包括所述多个焊盘。
  14. 如权利要求13所述的封装结构，其特征在于，所述封装结构还包括第二再布线层，所述第二再布线层形成在所述第一塑封层远离所述第一再布线层的表面，且与所述导电体的另一端和所述第一芯片电连接。
PCT/CN2023/129349 2022-11-09 2023-11-02 芯片封装方法及封装结构 WO2024099219A1 (zh)

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CN114499448A (zh) * 2021-12-28 2022-05-13 厦门云天半导体科技有限公司 基于倒装对位键合的扇出型滤波器封装结构及其制作方法

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