TWI415235B - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
TWI415235B
TWI415235B TW098133755A TW98133755A TWI415235B TW I415235 B TWI415235 B TW I415235B TW 098133755 A TW098133755 A TW 098133755A TW 98133755 A TW98133755 A TW 98133755A TW I415235 B TWI415235 B TW I415235B
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Taiwan
Prior art keywords
semiconductor device
substrate
cover
semiconductor wafer
sealing resin
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TW098133755A
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English (en)
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TW201025524A (en
Inventor
Kusano Hidetoshi
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Sony Corp
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Publication of TW201025524A publication Critical patent/TW201025524A/zh
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Publication of TWI415235B publication Critical patent/TWI415235B/zh

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    • H—ELECTRICITY
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    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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    • H01L23/367—Cooling facilitated by shape of device
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Description

半導體裝置及其製造方法
本發明係關於半導體裝置及其製造方法。詳細言之，係關於具備介隔高熱傳導性材料與半導體晶片接合之放熱板之半導體裝置及其製造方法。
近年來，電腦、手機、PDA(Personal Digital Assistance，個人數位助理)等電子機器正朝小型化、高性能化及高速化進展。因此，搭載適於此類電子機器之IC(積體電路)、LSI(大規模積體電路)等之半導體晶片之半導體裝置要求必須更加小型化、高速化及高密度化。而半導體裝置之小型化、高速化及高密度化，會導致消耗電力之增加，而有每單位體積之發熱量亦增加之趨勢。
又，作為半導體晶片之安裝構造，已知的是將半導體晶片之形成有電極之面以面朝下之狀態，利用焊錫凸塊以倒裝晶片安裝之方式安裝於基板之構造。但，倒裝晶片安裝之半導體裝置，由於半導體晶片及基板之熱膨脹係數之差異，會因發熱而使焊錫凸塊之接合部產生應力，亦會產生使連接可靠性下降之問題。
因此，將熱膨脹係數互相不同之半導體晶片及基板，藉由焊錫凸塊等連接構件連接之情形時，為因應於連接部份產生應力之問題，已提案有專利文獻1所記載之技術。
具體言之，專利文獻1中，提案有以熱膨脹係數與基板之熱膨脹係數相同或大致相同之值之構件(罩蓋)封裝之技術。利用該技術，抑制於接合設於基板之複數墊之各者、與設於半導體晶片之複數輸入端之各者的接合構件處產生應力。
以下，參照附圖，就專利文獻1所記載之技術進行說明。
圖15係用以說明先前之半導體裝置之模式圖。此處所示之半導體裝置101，具備配線基板102、半導體晶片103、及設於半導體晶片上面之罩蓋104。
配線基板102具有複數之墊105，該等墊105係與配置於配線基板102之表面或內層之配線連接。
半導體晶片103以表面面朝下之狀態倒裝晶片接合於配線基板102。另，複數之輸入輸入端106係設於半導體晶片之下面(表面)，各個輸入輸出端子配置成格子狀，設於與配線基板102上之各個複數之墊105對應之位置。再者，複數之輸入輸出端子106與複數之墊105相對應者彼此，係藉由焊錫107予以連接。
罩蓋104設有凹部，其斷面呈現凹狀之形狀，且於凹部之底面上，藉由高熱傳導性接著材108而接著半導體晶片103之上面。另，罩蓋104之端緣係藉由接著材料109而接著於配線基板102之上面。從而，藉由罩蓋104、接著材料109及配線基板102，使半導體晶片103構成為完全密封之狀態。
此處，罩蓋係由銅或黃銅所構成，銅之熱膨脹係數為16.5×10-6 /℃，黃銅之熱膨脹係數為17.3×10-6 /℃，係與配線基板102之熱膨脹係數(15~20×10-6 /℃)大致相同之值。
如此，專利文獻1所記載之技術中，藉由以具有與配線基板之熱膨脹係數相同或大致相同之熱膨脹係數之材料構成罩蓋，可抑制應力加諸於焊錫107。
然而，將半導體晶片倒裝晶片安裝於配線基板上之情形時，為保護配線基板與半導體晶片之電性連接部份，一般係藉由底膠材補強。具體言之，其係將以環氧樹脂作為主要成份之液狀底膠材，填充於配線基板與半導體晶片之間隙後，藉由施加熱而使底膠材硬化，而實現配線基板與半導體晶片之電性連接部份之補強。
但，在用以硬化底膠材之加熱之影響下，於配線基板會產生翹曲，使得配線基板與罩蓋之間隔於每個封裝產生差異，另，在封裝內亦會產生偏差。因此，為確實將罩蓋固定於配線基板，必須使配線基板與罩蓋間塗佈之接著材料之分量增多，其結果便會產生接著材料漏出之問題。
即，配線基板與罩蓋之間隔產生偏差之情形時，假設於配線基板與罩蓋間間隔較小之下塗佈接著材料時，會有接著材料之分量不夠充分，以致罩蓋之固定不夠充分之虞。為此，假設配線基板與罩蓋之間間隔較大，而塗佈較多分量之接著材料時，則會產生接著材料漏出，產生封裝不良，或通氣口潰落之各種問題。
因此，為確保罩蓋與配線基板之充分連接，且為使接著材料不從封裝外觀漏出，如圖16所示，乃於罩蓋形成有比罩蓋尺寸更小一圈之接著用凹部120。
即，假設配線基板與罩蓋之間隔較大，而塗佈較多分量之接著材料，以致即使接著材料漏出時，漏出之接著材料亦會積留於接著用凹部120，而據以對應封裝不良與通氣口潰落之各種問題。又，圖16中符號A表示漏出之接著材料。
[專利文獻1]日本特開平11-354677號公報
但，下一代之半導體封裝，係假設利用無芯基板。然而，利用無芯基板之情形時，由於考慮到較先前之基板(具有核材料C之基板)翹曲變形量變得更大，因此即使利用設有接著用凹部之罩蓋，亦有無法充分對應接著材料之漏出之可能。
另，亦可考慮到的是，因翹曲變形量變大，使得無芯基板與罩蓋之接著面積變小，以致罩蓋無法充分固定於無芯基板。
本發明係鑑於以上各點而創作者，其目的為提供一種半導體裝置及其製造方法，可充分確保基板與放熱板之接著面積，且消除因多餘接著材料之漏出所引起之故障。
為達成前述目的，本發明之半導體裝置具備：基板；以表面面朝下之狀態安裝於該基板之半導體晶片；設於前述基板之半導體晶片搭載區域之周邊區域之補強材；及放熱板，其係藉由介隔高熱傳導性材料與前述半導體晶片接合，且介隔接著材料與前述補強材接合，而配置於前述半導體晶片及前述補強材上，且於與前述補強材的接合面設有凹凸部。
此處，藉由設於與放熱板之補強材之接合面之凹凸部，可積留多餘之接著材料，而可消除因多餘接著材料之漏出所引起之故障。另，藉由設於與放熱板之補強材之接合面之凹凸部，使放熱板與接著材料之接觸面積增大，可充分確保基板與放熱板之接著面積。
另，為達成前述目的，本發明之半導體裝置之製造方法具備：將表面面朝下之半導體晶片以倒裝晶片方式安裝於設有配線圖案之基板之步驟；於倒裝晶片安裝之半導體晶片之周邊區域，形成補強材之步驟；及於前述半導體晶片之背面塗佈高熱傳導性材料，且於前述補強材表面塗佈接著材料後，於半導體晶片及補強材上，接合於與前述補強材之接合面設有凹凸部之放熱板之步驟。
此處，藉由接合於與補強材之接合面設有凹凸部之放熱板，可積留多餘之接著材料於凹凸部，消除因多餘材料之漏出所引起之故障。另，放熱板與接著材料之接觸面積增大，可充分確保基板與放熱板之接著面積。
使用本發明之半導體裝置及其製造方法，可充分確保基板與放熱板之接著面積，再者亦可消除因多餘接著材料之漏出所引起之故障。
以下，就本發明之實施形態參照附圖進行說明，以供理解本發明。
圖1係用以說明使用本發明之半導體裝置之一例之模式圖。此處所示之半導體裝置1，具有無芯基板2；以表面面朝下之狀態倒裝晶片安裝於基板2之LSI等之半導體晶片3；密封半導體晶片3之周圍之密封樹脂層4；及配置於半導體晶片3上之罩蓋5。
此處，本實施例所示之半導體裝置1，例舉具有於無芯基板2之背面，將複數之焊錫凸塊6配設成陣列狀之BGA(Ball Grid Array：球格柵陣列)型之半導體封裝構造之情形。再者，所謂「無芯基板2之背面」，意為安裝半導體晶片3之相反側之面。
另，所謂「半導體晶片3之表面」，意為設有與所安裝之無芯基板2電性連接之傳導部之面。而使半導體晶片3以其表面面朝下之狀態安裝於無芯基板，藉此可謀求半導體晶片3與無芯基板2之傳導路線之短縮化，實現半導體裝置之小型化。
再者，半導體晶片3之倒裝晶片安裝，係藉由將無芯基板2與半導體晶片3利用焊錫凸塊之C4(Controlled Collapse Chip Connection：塌陷高度控置晶片連接)技術電性連接。
另，於半導體晶片3與無芯基板2之間隙，填充底膠材(無圖示)。再者，由於填充底膠材，於溫度循環時可藉由無芯基板2與半導體晶片3之熱膨脹係數之差而分散於焊錫接合部分產生之應力，改善相對於溫度變化之動作穩定性。
如此，底膠材以焊錫連接部之保護為目的，具有填充間隙之適度的粘性為較佳。但，充分考慮到底膠材，會恩其粘性、表面張力或製造方法，從無芯基板2與半導體晶片3之間隙溢出於半導體晶片3之側面。因此較佳為，後述之密封樹脂層4介隔溢出於半導體晶片之側面之底膠材進行密封，藉由採用如此構造，因此可保護半導體晶片3避免光、熱及濕度等環境。
另，無芯基板2於其背面設有球焊點(無圖示)，於各個球焊點接合焊錫球6。再者，無芯基板2其背面設有電極墊(無圖示)，於各個電極墊安裝有電容器9。
圖2係用以詳細說明本實施例之無芯基板2之構造之模式剖面圖。此處所示之無芯基板2，具有將層間絕緣膜10與配線層11相互積層之多層配線構造，將複數之配線層11介隔層間絕緣膜10而積層。另，配線層11例如使用銅材料，不同層之配線層11間，藉由設於層間絕緣膜10之通孔插塞12電性連接。再者，於無芯基板2之背面之配線層11a之周圍，形成包含耐熱性佳之樹脂材料之阻焊層13，於無芯基板2進行焊接時，以不焊接於必要部位以外之方式塗佈最下層之層間絕緣膜10a。
另，於無芯基板2之背面，成陣列狀複數配設接合焊錫球6之球焊點7複數配置。再者，於安裝電容器9之電極部分，形成有錫(Sn)、銀(Ag)、銅(Cu)或包含該等之合金之電極墊14。
另一方面，於安裝半導體晶片3側即無芯基板2之表面，成陣列狀複數配設藉由電鍍形成之鎳(Ni)、鉛(Pb)、金(Au)或包含該等之合金之電極墊15。另，於電極墊15之上，設有錫、鉛或包含該等之合金之C4凸塊22。
如此，本實施例中藉由使用無芯基板，例如即使是6層構造亦可薄型化至300μm左右。再者，由於基板較薄故配線電阻低減，因此可望使半導體裝置之動作速度之高速化。
另，電容器9連接於半導體晶片3之正下方之無芯基板2之背面。據此，可縮短半導體晶片3至電容器9之配線路徑，而可謀求配線電阻之低減。再者，電容器9之設置場所，未必限於半導體晶片3之正下方之無芯基板之背面。例如，只要是可使配線路徑充分縮短之範圍內，亦可設於偏離半導體晶片3之正下方之無芯基板2之背面。或者，只要是可使配線路徑充分縮短之範圍內，亦可將電容器9設置於無芯基板2之表面。
另，密封樹脂層4係以與半導體晶片3大致相同厚度之方式所構成。再者，較佳為，密封樹脂層4將無芯基板2覆蓋至比配設成陣列狀之複數之焊錫球6中最外位置之焊錫球6更外側。由於藉由密封樹脂層4使無芯基板2之強度提升，因此可抑制無芯基板2之翹曲，於是可望提升焊錫球6之電氣連接性。
再者，罩蓋5由高熱傳導性材料(例如銅材料)所構成，介隔塗佈於半導體晶片3背面之高熱傳導性材料TIM(Thermal Interface Material：熱界面材料)材料17而與半導體晶片3接合。另，藉由塗佈於密封樹脂層4之表面之接著材料(密封件)18而與密封樹脂層4接合。
此處，本實施例之TIM材料，係於樹脂材料中摻入熱傳導性填充物者，作為樹脂材料，例如可舉出附加硬化型矽氧樹脂組成物。再者，所謂附加硬化型聚矽氧樹脂組成物，是由含有液態聚矽氧作為基礎聚合物之硬化型聚矽氧樹脂組成物所構成之其硬化型聚矽氧樹脂組成物中添加例如熱硬化性之接著賦予成份者。具體言之，已知有含有烷氧矽烷基之有機氫矽氧烷之附加硬化型聚矽氧橡膠組成物(例如參照日本特公昭53-21026號公報)，或含有具有環氧基之有機氫矽氧烷之附加硬化型聚矽氧橡膠組成物(例如參照日本特公昭53-13508號公報)等。
另，熱傳導性填充物係在半導體晶片3與罩蓋5間作為傳遞熱之媒介發揮作用者。具體言之，例如可舉出包含銀(Ag)、鋁(Al)、氧化鋁(Al2 O3 )、二氧化矽(SiO2 )等粒子或粉狀物質之填充材者。惟熱傳導性填充物可以是包含該等填充材之任一種者，也可以是包含粒徑不同之複數之填充材者。
再者，熱傳導性填充物，除了熱傳導之媒介性能外，亦具有作為保持半導體晶片3與罩蓋5之間隔之間隔件之功能。並且，藉由作為該間隔件之功能，而決定摻入熱傳導性填充物之TIM材料、即介於半導體晶片3與罩蓋5間之TIM材料之厚度。
另，於罩蓋5之與密封樹脂層4之接合面，形成有複數個小凹坑(凹部)16a。即，於罩蓋5之與密封樹脂層4之接合面設有凹凸部。
以下，就如上述所構成之半導體裝置之製造方法進行說明。即，就使用本發明之半導體裝置之製造方法之一例進行說明。
圖3係顯示使用本發明之半導體裝置之製造方法之一例之概略之流程圖，首先，形成具有多層配線構造之無芯基板(S10)，於該無芯基板之上安裝半導體晶片(S20)。接著，以密封樹脂密封半導體晶片(S30)，搭載罩蓋(S40)。之後，於無芯基板之背面安裝焊錫球、電容器等(S50)。
以下，就無芯基板之形成方法、半導體晶片之安裝方法及密封樹脂之形成方法，詳細地進行說明。
[無芯基板之形成方法]
首先，如圖4(a)及圖4(b)所示，於銅基板50之上塗佈抗蝕膜52，藉由雷射光之照射將抗蝕膜52圖案化成具有特定開口之形狀。接著，如圖4(c)所示，將抗蝕膜52作為掩模，藉由電鍍使鎳(Ni)、鉛(Pb)、金(Au)或包含該等之合金等之電極墊15形成於銅基板50之上。
接著，如圖5(a)所示，除去抗蝕膜52後，如圖5(b)所示，於銅基板50之上形成層間絕緣膜10。接著，如圖5(c)所示，將層間絕緣膜10之特定的區域藉由雷射光除去，形成導通孔62。又，藉由雷射加工而形成各導通孔62，與鑽孔加工之情形比較，將實現製造成本之低減。
接著，如圖6(a)所示，於層間絕緣膜10之表面上，藉由無電電鍍法於導通孔62之側面及底部形成包含銅之種子層70。種子層70係在後述之銅之電鍍時，成為用於成長銅之核。接著，如圖6(b)所示，於種子層70之上，塗佈抗蝕劑膜72，藉由雷射光之照射圖案化成具有特定開口之形狀。
接著，如圖6(c)所示，將抗蝕膜72作為掩模，於導通孔62中利用電鍍法埋入銅而形成通孔插塞12，且於層間絕緣膜10之上形成配線層11。藉由通孔插塞12，使不同層間之配線層11電性連接。接著，如圖6(d)所示，除去抗蝕膜72後，藉由蝕刻除去存在於抗蝕膜72之下之種子層70，且藉由除去配線層11之最表面，淨化配線層11之表面。
藉由重複以上說明之圖4至圖6所示之程序，可建構如圖7(a)所示之多層配線構造之無芯基板。
接著，如圖7(b)所示，將抗蝕膜(無圖示)作為掩模，以露出最表面之配線層11之方式，於層間絕緣膜10之上形成阻焊層13。接著，如圖7(c)所示，除去銅基板50，且於所要接合BGA球之球焊點7表面，覆蓋有機表面保護塗層材(OSP)21。
接著，如圖8(a)所示，將倒裝晶片安裝用之C4凸塊22焊接於電極墊15之上。另，於安裝電容器之電極部份，藉由焊接，形成錫(Sn)、銀(Ag)、銅(Cu)或包含該等之合金之電極墊14。接著，如圖8(b)所示，將C4凸塊22藉由衝壓平坦化。再者，如圖8(b)所示之C4凸塊平坦化，亦可以機械研磨進行。
藉由以上步驟，形成本實施例所使用之無芯基板2。再者，圖8(b)所示之無芯基板，與圖2所示之無芯基板上下相反。
[半導體晶片之安裝方法]
首先，如圖9(a)所示，將半導體晶片3之設有外部電極端之表面以面朝下之狀態，藉由將各焊錫凸塊32及對應於該等之C4凸塊22焊接，而將半導體晶片3進行倒裝晶片安裝。接著，如圖9(b)所示，於半導體晶片3與無芯基板2之間填充底膠材40。
藉由以上步驟，在將焊錫接合部份所產生之應力由底膠材40予以分散之狀態下，於無芯基板2將半導體晶片3進行倒裝晶片安裝。
[密封樹脂形成方法]
首先，本密封樹脂形成方法所使用之上模200，具備成為熔融的密封樹脂之流通路之流道202。流道202具有當上模200與下模210合模時所形成之朝向腔穴220之開口部。
此處，上模200之成形面，包含樹脂成型時與半導體晶片3之背面相接之晶片接觸面207；及位於晶片接觸面207之周圍，用以成型密封樹脂層4之樹脂成型面206。又，藉由樹脂成型時晶片接觸面207與半導體晶片3之背面相接，則樹脂成型時密封樹脂將不會流入半導體晶片3之背面。再者，於上模200設有與泵等吸引機構連通之吸引穴204。
另一方面，下模210具有使柱塞212可往復運動地形成之料筒214。
利用如此上模200及下模210，如圖10(a)所示，將安裝有半導體晶片3之無芯基板2裝載於下模210。再者，將脫模薄膜230設置於上模200與下模210之間。
接著，如圖10(b)所示，於料筒214中，投入固體密封樹脂之樹脂粒240。藉由使吸引機構動作，排出脫模薄膜230與上模200間之空氣，使脫模薄膜230密著於上模200。接著，如圖10(c)所示，使上模200與下模210合膜，以被推壓狀態夾緊。
接著，如圖11(a)所示，在將樹脂粒240加熱熔融狀態下，藉由將柱塞212壓入料筒214，而將液體狀之密封樹脂241導入腔穴220內。以密封樹脂241填充上模200與無芯基板2間所形成之空間後，加熱一定時間，使密封樹脂241固化。又，本實施例中，雖例舉熱硬化性之密封樹脂進行說明，但亦可藉由冷卻而固化之密封樹脂。
接著，如圖11(b)所示，拉開上模200與下模210，取出形成密封樹脂層4之無芯基板2。
根據以上說明之密封樹脂形成方法，可於半導體晶片3之周圍形成密封半導體晶片3之密封樹脂層4。
另，可使密封樹脂241不與腔穴220之內面等接觸而成型密封樹脂層4。另，由於將密封樹脂層4已成型之無芯基板2藉由脫模薄膜230可容易地脫膜，因此不需於上模200設置頂出銷。因此，可簡化模具構造，因而可使半導體裝置之製造成本下降。另，由於可使用最適於半導體裝置之密封樹脂材料，因此可提高半導體裝置設計之自由度。
[罩蓋之安裝方法]
首先，於半導體晶片3之背面塗佈TIM材17，且於密封樹脂層4之表面塗佈接著材料(密封件)18。接著，藉由將於與密封樹脂層4之接合面設有之小凹坑16a之罩蓋5、與半導體晶片3之背面及密封樹脂層4之表面接合，可得到如圖1所示之半導體裝置1。
使用本發明之半導體裝置1，於罩蓋5之與密封樹脂層4之接合面設有複數之小凹坑16a，使多餘之密封件18可由小凹坑16a吸收。從而，密封件18不會漏出於罩蓋外或無芯基板外，而可消除因密封件18之漏出所引起之故障。
另，藉由設有之小凹坑16a，使罩蓋5與密封件18之接觸面積增大，實現無芯基板2與罩蓋5之堅固的接合。
圖12係用以說明使用本發明之半導體裝置之變形例(1)之模式圖，此處所示之半導體裝置1，於罩蓋5之與密封樹脂層4之接合面設有凹部16b。此處，凹部16b係以其深度從罩蓋5之周邊區域向中央區域變深之方式構成。其他之構造皆與使用本發明之半導體裝置之一例相同。
使用本發明之半導體裝置之變形例(1)中，於罩蓋5之與密封樹脂層4之接合面，設有以其深度從周邊區域向中央區域變深之方式構成之凹部16b，使多餘之密封件18向中央區域側漏出。即，密封樹脂層4與罩蓋5之間之多餘的密封件18會向散逸幅度較大且壓力不集中之中央區域側漏出。從而，密封件18不會漏出於罩蓋外或無芯基板外，可消除因密封件18之漏出所引起之故障。
圖13係用以說明使用本發明之半導體裝置之變形例(2)之模式圖。此處所示之半導體裝置1，於罩蓋之與密封樹脂層4之接合面形成有複數之貫通孔16c。再者，此處之貫通孔16c為凹凸部之一例。其他構造皆與使用本發明之半導體裝置之一例相同。
使用本發明之半導體裝置之變形例(2)中，於罩蓋5之與密封樹脂層4之接合面設有複數之貫通孔16c，使多餘之密封件18可由貫通孔16c吸收。從而，密封件18將不會漏出於罩蓋外或無芯基板外，可消除因密封件18之漏出所引起之故障。另，藉由設有貫通孔16c，使罩蓋5與密封件18之接觸面積增大，實現無芯基板2與罩蓋5間之堅固的接合。
再者，由於貫通孔16c亦可發揮作為通氣口之性能，因此可謀求積留空氣之低減，亦可充分對應吸濕回流處理等時之爆米花現象。但，一般會於罩蓋5表面施行各種標示(印刷)，故亦可想見貫通孔16c可能成為標示(印刷)之障礙。在此情形下，不設置貫通孔16c，而如使用前述之本發明之半導體裝置般設置小凹坑16a較佳。
圖14係用以說明使用本發明之半導體裝置之變形例(3)之模式圖。此處所示之半導體裝置1，於密封樹脂層4設有突起部19。其他之構造皆與使用本發明之半導體裝置之一例相同。
使用本發明之半導體裝置之變形例(3)中，藉由設有突起部，使密封樹脂層4與密封件18之接觸面積增大，實現無芯基板2與罩蓋5之堅固的接合。再者，藉由於上模200與下模210之空間填充密封樹脂241而將密封樹脂層4成型，因此突起部19亦可容易地成型。
再者，本實施例中，雖例舉由樹脂材料所形成之補強材進行說明，但補強材未必由樹脂材料形成，亦可由貼合包含金屬材料之補強材而構成。
1．．．半導體裝置
2．．．無芯基板
3．．．半導體晶片
4．．．密封樹脂層
5．．．罩蓋
6．．．焊錫凸塊
7．．．球焊點
9．．．電容器
10．．．層間絕緣膜
10a．．．最下層之層間絕緣膜
11．．．配線層
11a．．．背面之配線層
12．．．通孔插塞
13．．．阻焊層
14．．．電極墊
15．．．電極墊
16a．．．小凹坑
16b．．．凹部
16c．．．貫通孔
17．．．TIM材料
18．．．密封件
21．．．有機表面保護塗層材料
22．．．C4凸塊
32．．．焊錫凸塊
40．．．底膠材
50．．．銅基板
52．．．抗蝕膜
62．．．導通孔
70．．．種子層
72．．．抗蝕膜
200．．．上模
202．．．流道
204．．．吸引穴
206．．．樹脂成型面
207．．．晶片接觸面
212．．．壓料柱塞
214．．．料筒
220．．．腔穴
230．．．脫模薄膜
240．．．樹脂粒
241．．．密封樹脂
圖1係用以說明使用本發明之半導體裝置之一例之模式圖。
圖2係用以詳細說明無芯基板之構造之模式剖面圖。
圖3係顯示使用本發明之半導體裝置之製造方法之一例之概略之流程圖。
圖4(a)-(c)係用以說明使用本發明之半導體裝置之製造方法之一例之模式圖(2)。
圖5(a)-(c)係用以說明使用本發明之半導體裝置之製造方法之一例之模式圖(2)。
圖6(a)-(d)係用以說明使用本發明之半導體裝置之製造方法之一例之模式圖(3)。
圖7(a)-(c)係用以說明使用本發明之半導體裝置之製造方法之一例之模式圖(4)。
圖8(a)-(b)係用以說明使用本發明之半導體裝置之製造方法之一例之模式圖(5)。
圖9(a)-(b)係用以說明使用本發明之半導體裝置之製造方法之一例之模式圖(6)。
圖10(a)-(c)係用以說明使用本發明之半導體裝置之製造方法之一例之模式圖(7)。
圖11(a)-(b)係用以說明使用本發明之半導體裝置之製造方法之一例之模式圖(8)。
圖12係用以說明使用本發明之半導體裝置之變形例(1)之模式圖。
圖13係用以說明使用本發明之半導體裝置之變形例(2)之模式圖。
圖14係用以說明使用本發明之半導體裝置之變形例(3)之模式圖。
圖15係用以說明先前之半導體裝置之模式圖(1)。
圖16係用以說明先前之半導體裝置之模式圖(2)。
1．．．半導體裝置
2．．．無芯基板
3．．．半導體晶片
4．．．密封樹脂層
5．．．罩蓋
6．．．焊錫凸塊
9．．．電容器
16a．．．小凹坑
17．．．TIM材料
18．．．密封件

Claims (23)

  1. 一種半導體裝置，其包含：熱界面材料，其係與罩蓋之中央區域實體接觸；凹部，其係延伸入上述罩蓋之周圍區域；半導體晶片，其係介於上述熱界面材料及基板之中央區域之間；及密封樹脂層，其係介於密封件及上述基板之周圍區域；其中上述密封件係於上述凹部內，且上述熱界面材料鄰近於上述凹部及上述密封件。
  2. 如請求項1之半導體裝置，其中上述密封樹脂層係與上述基板之周圍區域及上述密封件實體接觸。
  3. 如請求項1之半導體裝置，其中上述基板之中央區域係介於電容器及上述半導體晶片之間。
  4. 如請求項1之半導體裝置，其中上述罩蓋之一表面與上述熱界面材料及上述密封件實體接觸，上述凹部係自上述表面延伸入上述罩蓋之周圍區域。
  5. 如請求項1之半導體裝置，其中上述凹部係部份延伸入上述罩蓋之小凹坑。
  6. 如請求項1之半導體裝置，其中上述凹部係貫穿上述罩蓋之孔。
  7. 如請求項1之半導體裝置，其中上述凹部之深度自上述罩蓋之邊緣向中央區域增加。
  8. 如請求項1之半導體裝置，其中上述密封件係介於上述密 封樹脂層及上述罩蓋之周圍區域。
  9. 如請求項1之半導體裝置，其中上述密封樹脂層係與上述半導體晶片實體接觸。
  10. 如請求項1之半導體裝置，其中上述密封件係接著材料。
  11. 如請求項1之半導體裝置，其中上述密封件與上述罩蓋實體接觸。
  12. 如請求項1之半導體裝置，其中上述罩蓋係高熱傳導性材料。
  13. 如請求項1之半導體裝置，其中上述基板包含：積層之層間絕緣膜、及配線層，且上述配線層遍布於上述積層之層間絕緣膜。
  14. 如請求項1之半導體裝置，其中上述基板之周圍區域係介於上述密封樹脂層及焊錫球之間。
  15. 如請求項1之半導體裝置，其中上述半導體晶片及上述基板之中央區域之間介有底膠材。
  16. 如請求項1之半導體裝置，其中焊錫凸塊係自上述半導體晶片延伸出，連接凸塊係自上述基板之中央區域延伸出，且上述焊錫凸塊係與上述連接凸塊實體並電性接觸。
  17. 如請求項1之半導體裝置，其中上述半導體晶片係與上述基板之中央區域及上述熱界面材料實體接觸。
  18. 如請求項1之半導體裝置，其中上述熱界面材料構成為於上述半導體晶片及上述罩蓋間傳熱。
  19. 如請求項1之半導體裝置，其中上述熱界面材料與上述半 導體晶片及上述罩蓋之中央區域實體接觸。
  20. 如請求項1之半導體裝置，其中上述熱界面材料係熱傳導性填充物及樹脂材料之混合物。
  21. 如請求項20之半導體裝置，其中上述混合物包含硬化型矽氧樹脂組合物。
  22. 如請求項20之半導體裝置，其中上述熱傳導性填充物為銀、鋁、氧化鋁、及二氧化矽所組成之物質群中之任一種。
  23. 一種用來製造如請求項1之半導體裝置之方法，該方法包含：將上模與下模夾緊以形成腔穴，並將上述半導體晶片及上述基板包圍於上述上模與上述下模之間；將液態密封樹脂導入至上述腔穴，使上述液態密封樹脂固化而形成上述密封樹脂層。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI797482B (zh) * 2020-06-29 2023-04-01 大陸商珠海越亞半導體股份有限公司 積體被動裝置封裝結構製作方法

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011111112A1 (ja) * 2010-03-12 2011-09-15 富士通株式会社 放熱構造体およびその製造方法
US20120104591A1 (en) * 2010-10-29 2012-05-03 Conexant Systems, Inc. Systems and methods for improved heat dissipation in semiconductor packages
US20130049188A1 (en) * 2011-08-25 2013-02-28 Stats Chippac, Ltd. Semiconductor Device and Method of Forming TIM Within Recesses of MUF Material
US9287191B2 (en) * 2011-10-12 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device package and method
US9412717B2 (en) * 2011-11-04 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for molded underfills in flip chip packaging
US9006889B2 (en) 2011-11-11 2015-04-14 Skyworks Solutions, Inc. Flip chip packages with improved thermal performance
JP6008582B2 (ja) * 2012-05-28 2016-10-19 新光電気工業株式会社 半導体パッケージ、放熱板及びその製造方法
KR101368719B1 (ko) * 2012-07-31 2014-03-03 주식회사 영일프레시젼 반도체 패키지용 방열판
JP2014063844A (ja) * 2012-09-20 2014-04-10 Sony Corp 半導体装置、半導体装置の製造方法及び電子機器
KR102005234B1 (ko) 2012-09-25 2019-07-30 삼성전자주식회사 가이드 벽을 갖는 반도체 패키지
US9552977B2 (en) * 2012-12-10 2017-01-24 Intel Corporation Landside stiffening capacitors to enable ultrathin and other low-Z products
CN103021887B (zh) * 2012-12-31 2015-04-22 无锡中微高科电子有限公司 有散热要求fc电路的气密性封帽方法
US8901732B2 (en) * 2013-03-12 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device package and method
US9831190B2 (en) 2014-01-09 2017-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device package with warpage control structure
JP6421432B2 (ja) * 2014-03-31 2018-11-14 日本電気株式会社 半導体装置およびその製造方法
JP6312527B2 (ja) * 2014-05-23 2018-04-18 新日本無線株式会社 放熱板を備えた電子部品の実装構造
JP6379815B2 (ja) * 2014-07-31 2018-08-29 富士電機株式会社 半導体装置およびその製造方法
KR102392202B1 (ko) * 2015-04-09 2022-05-02 삼성전자주식회사 방열막을 구비한 반도체 패키지 및 그 제조방법
US10692797B2 (en) 2015-06-30 2020-06-23 Laird Technologies, Inc. Thermal interface materials with low secant modulus of elasticity and high thermal conductivity
US9828539B2 (en) 2015-06-30 2017-11-28 Laird Technologies, Inc. Thermal interface materials with low secant modulus of elasticity and high thermal conductivity
US10155896B2 (en) 2015-06-30 2018-12-18 Laird Technologies, Inc. Thermal interface materials with low secant modulus of elasticity and high thermal conductivity
US10109547B2 (en) * 2016-01-29 2018-10-23 Taiwan Semiconductor Manufacturing Company, Llc Semiconductor device and method of manufacture
US10420255B2 (en) * 2016-09-14 2019-09-17 Jtekt Corporation Electronic control device
DE102016117841A1 (de) * 2016-09-21 2018-03-22 HYUNDAI Motor Company 231 Packung mit aufgerauter verkapselter Oberfläche zur Förderung einer Haftung
WO2018067150A1 (en) 2016-10-06 2018-04-12 Hewlett-Packard Development Company, L.P. Adhesive sealing of thermal interface materials
US10177060B2 (en) * 2016-10-21 2019-01-08 Powertech Technology Inc. Chip package structure and manufacturing method thereof
CN110476245B (zh) * 2017-03-31 2023-08-01 株式会社村田制作所 模块
US10529645B2 (en) * 2017-06-08 2020-01-07 Xilinx, Inc. Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal management
KR102442622B1 (ko) * 2017-08-03 2022-09-13 삼성전자주식회사 반도체 소자 패키지
JP2019057546A (ja) * 2017-09-19 2019-04-11 東芝メモリ株式会社 半導体記憶装置
JP7000129B2 (ja) * 2017-11-15 2022-01-19 芝浦メカトロニクス株式会社 成膜装置
CN108520866A (zh) * 2018-04-27 2018-09-11 宁波江丰电子材料股份有限公司 焊接结构及半导体零件
JP2019200240A (ja) * 2018-05-14 2019-11-21 キヤノン株式会社 光プリントヘッドを備える画像形成装置
US11581240B2 (en) * 2018-12-21 2023-02-14 Intel Corporation Liquid thermal interface material in electronic packaging
US10643924B1 (en) * 2019-05-01 2020-05-05 Yuci Shen Heat-dissipating lid with reservoir structure and associated lidded flip chip package allowing for liquid thermal interfacing materials
US11621211B2 (en) * 2019-06-14 2023-04-04 Mediatek Inc. Semiconductor package structure
US11948855B1 (en) 2019-09-27 2024-04-02 Rockwell Collins, Inc. Integrated circuit (IC) package with cantilever multi-chip module (MCM) heat spreader
US11749631B2 (en) * 2020-05-20 2023-09-05 Apple Inc. Electronic package including a hybrid thermal interface material and low temperature solder patterns to improve package warpage and reliability
CN112599653B (zh) * 2020-12-04 2023-03-10 杭州大和热磁电子有限公司 一种适于冷热交变的热电模块及其制作方法
CN115116985A (zh) * 2021-03-19 2022-09-27 华为技术有限公司 用于抑制电磁辐射的芯片封装散热组件
US20220406681A1 (en) * 2021-06-18 2022-12-22 Taiwan Semiconductor Manufacturing Company Limited Package assembly including liquid alloy thermal interface material and methods of forming the same
CN114823573B (zh) * 2022-06-24 2022-09-09 威海市泓淋电力技术股份有限公司 一种散热型封装结构及其形成方法
TWI830448B (zh) * 2022-10-19 2024-01-21 同欣電子工業股份有限公司 晶片封裝結構及其製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200418157A (en) * 2003-03-04 2004-09-16 Siliconware Precision Industries Co Ltd Semiconductor package with heatsink

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5760465A (en) * 1996-02-01 1998-06-02 International Business Machines Corporation Electronic package with strain relief means
JP2814985B2 (ja) * 1996-04-25 1998-10-27 日本電気株式会社 固体電解コンデンサの製造方法
JPH10242355A (ja) * 1997-02-25 1998-09-11 Hitachi Ltd 半導体集積回路装置
JPH11345905A (ja) * 1998-06-02 1999-12-14 Mitsubishi Electric Corp 半導体装置
JP3070579B2 (ja) 1998-06-10 2000-07-31 日本電気株式会社 半導体装置の実装構造および実装方法
JP2000012744A (ja) * 1998-06-19 2000-01-14 Fujitsu Ltd 半導体装置及びその製造方法
JP3519285B2 (ja) * 1998-09-28 2004-04-12 松下電器産業株式会社 半導体装置
JP3395164B2 (ja) * 1998-11-05 2003-04-07 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体装置
JP3277996B2 (ja) * 1999-06-07 2002-04-22 日本電気株式会社 回路装置、その製造方法
US6233960B1 (en) * 1999-10-12 2001-05-22 International Business Machines Corporation Spot cooling evaporator cooling system for integrated circuit chip modules
JP2002151613A (ja) * 2000-11-09 2002-05-24 Kyocera Corp 半導体素子収納用パッケージ
TW574750B (en) * 2001-06-04 2004-02-01 Siliconware Precision Industries Co Ltd Semiconductor packaging member having heat dissipation plate
KR100446290B1 (ko) * 2001-11-03 2004-09-01 삼성전자주식회사 댐을 포함하는 반도체 패키지 및 그 제조방법
JP4568472B2 (ja) * 2002-11-29 2010-10-27 東レ・ダウコーニング株式会社 銀粉末の製造方法および硬化性シリコーン組成物
JP4255842B2 (ja) * 2004-01-09 2009-04-15 パナソニック株式会社 半導体装置
JP4986435B2 (ja) * 2005-10-12 2012-07-25 株式会社ソニー・コンピュータエンタテインメント 半導体装置、半導体装置の作成方法
JP4155999B2 (ja) * 2006-06-02 2008-09-24 株式会社ソニー・コンピュータエンタテインメント 半導体装置および半導体装置の製造方法
CN101114624A (zh) * 2006-07-27 2008-01-30 矽品精密工业股份有限公司 散热型半导体封装件及其散热结构

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200418157A (en) * 2003-03-04 2004-09-16 Siliconware Precision Industries Co Ltd Semiconductor package with heatsink

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI797482B (zh) * 2020-06-29 2023-04-01 大陸商珠海越亞半導體股份有限公司 積體被動裝置封裝結構製作方法

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