JP4321269B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4321269B2 JP4321269B2 JP2004006670A JP2004006670A JP4321269B2 JP 4321269 B2 JP4321269 B2 JP 4321269B2 JP 2004006670 A JP2004006670 A JP 2004006670A JP 2004006670 A JP2004006670 A JP 2004006670A JP 4321269 B2 JP4321269 B2 JP 4321269B2
- Authority
- JP
- Japan
- Prior art keywords
- underfill material
- interposer substrate
- solder resist
- wiring
- intermediate layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Description
図1は、本発明の第1実施形態に係る半導体装置S1としてのBGA(ボールグリッドアレイ)の概略断面構成を示す図である。
ここで、本実施形態の変形例を述べておく。
図6は、本発明の第2実施形態に係る半導体装置S2としてのBGA(ボールグリッドアレイ)の概略断面構成を示す図である。
なお、本発明は上記したBGA以外にも、少なくとも一面側に配線部を有し、配線部の表面の一部がソルダーレジストにて被覆されたインターポーザ基板と、インターポーザ基板の一面側にフリップチップバンプを介して搭載された半導体チップと、半導体チップとインターポーザ基板との隙間を埋めるように充填されたアンダーフィル材とを備える半導体装置について適用可能であることは上述の説明から明らかである。
14…スルーホール、15…ソルダーレジスト、16…中間層、
17…アンダーフィル材、18…半導体チップ、19…フリップチップバンプ。
Claims (2)
- 少なくとも一面側に配線部(11、12)を有し、前記配線部(11、12)の表面の一部がソルダーレジスト(15)にて被覆されたインターポーザ基板(10)と、
前記インターポーザ基板(10)の一面側にフリップチップバンプ(19)を介して搭載された半導体チップ(18)と、
前記半導体チップ(18)と前記インターポーザ基板(10)との隙間を埋めるように充填されたアンダーフィル材(17)とを備える半導体装置において、
前記ソルダーレジスト(15)と前記アンダーフィル材(17)との間に、前記ソルダーレジスト(15)と前記アンダーフィル材(17)との間に発生する応力を緩和するための中間層(16)が介在しており、
前記中間層(16)は、熱膨張係数が前記アンダーフィル材(17)よりも大きく且つヤング率が前記ソルダーレジスト(15)と前記アンダーフィル材(17)との中間の大きさであり、
前記中間層(16)は、前記アンダーフィル材(15)のフィレット部の端部の直下に設けられていることを特徴とする半導体装置。 - 前記インターポーザ基板(10)は、スルーホール(14)を有するものであり、
前記インターポーザ基板(10)の一面側に設けられた前記配線部(11)は、前記アンダーフィル材(17)のフィレット部の端部の直下では、前記スルーホール(14)を介して前記インターポーザ基板(10)の一面側から厚み方向の内部に向かって引き出されていることを特徴とする請求項1に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004006670A JP4321269B2 (ja) | 2004-01-14 | 2004-01-14 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004006670A JP4321269B2 (ja) | 2004-01-14 | 2004-01-14 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005203488A JP2005203488A (ja) | 2005-07-28 |
JP4321269B2 true JP4321269B2 (ja) | 2009-08-26 |
Family
ID=34820566
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004006670A Expired - Fee Related JP4321269B2 (ja) | 2004-01-14 | 2004-01-14 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4321269B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006100385A (ja) | 2004-09-28 | 2006-04-13 | Rohm Co Ltd | 半導体装置 |
US11842972B2 (en) | 2004-09-28 | 2023-12-12 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
JP2008210827A (ja) * | 2007-02-23 | 2008-09-11 | Nec Electronics Corp | 半導体装置および配線基板、ならびにそれらの製造方法 |
US7763965B2 (en) * | 2007-09-25 | 2010-07-27 | International Business Machines Corporation | Stress relief structures for silicon interposers |
JP6464762B2 (ja) * | 2015-01-16 | 2019-02-06 | 凸版印刷株式会社 | 半導体パッケージ基板、および半導体パッケージと、半導体パッケージ基板の製造方法、および半導体パッケージの製造方法 |
-
2004
- 2004-01-14 JP JP2004006670A patent/JP4321269B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005203488A (ja) | 2005-07-28 |
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