JP5515744B2 - 配線基板及び半導体装置 - Google Patents
配線基板及び半導体装置 Download PDFInfo
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- JP5515744B2 JP5515744B2 JP2009554362A JP2009554362A JP5515744B2 JP 5515744 B2 JP5515744 B2 JP 5515744B2 JP 2009554362 A JP2009554362 A JP 2009554362A JP 2009554362 A JP2009554362 A JP 2009554362A JP 5515744 B2 JP5515744 B2 JP 5515744B2
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
- H01L2224/02125—Reinforcing structures
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
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- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
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- H05K2201/0133—Elastomeric or compliant polymer
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- H—ELECTRICITY
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
本発明は、日本国特許出願:特願2008−040335号(2008年2月21日出願)の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
本発明は、半導体パッケージ又は半導体チップを実装するための配線基板及び半導体装置に関し、特に、フリップチップ接続、CSP(Chip Scale Package)接続等に適した配線基板及び半導体装置に関する。
バンプを用いた従来技術において、LSIチップ−配線基板間がはんだバンプを介してフリップチップ接続される場合、弾性率が高いはんだバンプは、LSIチップ−配線基板間の熱膨張差により高い応力が発生し、はんだバンプ自身又ははんだバンプ近傍のLSIチップにおけるLSI回路を破壊するおそれがある。特に、ハイエンド向け大型ASIC(Application Specific Integrated Circuit)を中心にLSIチップにおける絶縁層のLow−k(低誘電率)化によるLSI回路の脆弱化が進行しており、特に、応力によるLSI回路の破壊が顕著になっている。
11 低弾性樹脂
12、112 実装パッド(パッド)
12a、112a 配線
12b 外周部
12c 結線部
13、113 絶縁層(基板)
13a 穴
14 金属層
20、120 半導体チップ(LSIチップ)
21、121 電極
30、130 バンプ(金属層)
131 樹脂コア
140 アンダーフィル樹脂
さらに、以下の形態も可能である。
前記絶縁層中に配設されるとともに、少なくとも前記凹部の底面に配された金属層を備えることが好ましい。
前記絶縁層上に形成されるとともに、前記外周部と接続された配線を備えることが好ましい。
前記結線部は、直線状、曲線状、斜線状、又はこれらの組合せで形成されていることが好ましい。
前記配線基板と、前記配線基板のパッドと対応する位置に電極を有する半導体チップ又は半導体パッケージと、前記パッドと前記電極の間に配設されるとともに、前記パッドと前記電極を電気的に接続するバンプと、を備える半導体装置とすることが好ましい。
Claims (5)
- 所定の位置に凹部を有する絶縁層と、
前記凹部内に埋め込まれるとともに、前記絶縁層よりも低弾性な低弾性樹脂と、
前記低弾性樹脂上に配設されるとともに、前記低弾性樹脂の領域よりも小さい領域のパッドと、
を備え、
前記低弾性樹脂の領域の外周の前記絶縁層上に配設されるとともに、前記パッドと同一材料よりなる外周部と、
前記低弾性樹脂の領域内であって前記実装パッドと前記外周部の間の領域の一部に配設されるとともに、前記パッドと同一材料よりなり、かつ、前記実装パッドと前記外周部を結線する1又は複数の結線部と、
を備えることを特徴とする配線基板。 - 前記絶縁層中に配設されるとともに、少なくとも前記凹部の底面に配された金属層を備えることを特徴とする請求項1記載の配線基板。
- 前記絶縁層上に形成されるとともに、前記外周部と接続された配線を備えることを特徴とする請求項1又は2記載の配線基板。
- 前記結線部は、直線状、曲線状、斜線状、又はこれらの組合せで形成されていることを特徴とする請求項1乃至3のいずれか一に記載の配線基板。
- 請求項1乃至4のいずれか一に記載の配線基板と、
前記配線基板のパッドと対応する位置に電極を有する半導体チップ又は半導体パッケージと、
前記パッドと前記電極の間に配設されるとともに、前記パッドと前記電極を電気的に接続するバンプと、
を備えることを特徴とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009554362A JP5515744B2 (ja) | 2008-02-21 | 2009-02-19 | 配線基板及び半導体装置 |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008040335 | 2008-02-21 | ||
| JP2008040335 | 2008-02-21 | ||
| JP2009554362A JP5515744B2 (ja) | 2008-02-21 | 2009-02-19 | 配線基板及び半導体装置 |
| PCT/JP2009/052862 WO2009104668A1 (ja) | 2008-02-21 | 2009-02-19 | 配線基板及び半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPWO2009104668A1 JPWO2009104668A1 (ja) | 2011-06-23 |
| JP5515744B2 true JP5515744B2 (ja) | 2014-06-11 |
Family
ID=40985546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009554362A Expired - Fee Related JP5515744B2 (ja) | 2008-02-21 | 2009-02-19 | 配線基板及び半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP5515744B2 (ja) |
| WO (1) | WO2009104668A1 (ja) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
| JP5584474B2 (ja) | 2007-03-05 | 2014-09-03 | インヴェンサス・コーポレイション | 貫通ビアによって前面接点に接続された後面接点を有するチップ |
| US8193615B2 (en) | 2007-07-31 | 2012-06-05 | DigitalOptics Corporation Europe Limited | Semiconductor packaging process using through silicon vias |
| US8791575B2 (en) | 2010-07-23 | 2014-07-29 | Tessera, Inc. | Microelectronic elements having metallic pads overlying vias |
| US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
| US8796135B2 (en) | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
| US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
| US8610259B2 (en) | 2010-09-17 | 2013-12-17 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
| US8637968B2 (en) | 2010-12-02 | 2014-01-28 | Tessera, Inc. | Stacked microelectronic assembly having interposer connecting active chips |
| US8587126B2 (en) | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
| US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
| US8610264B2 (en) * | 2010-12-08 | 2013-12-17 | Tessera, Inc. | Compliant interconnects in wafers |
| DE102011014584A1 (de) * | 2011-03-21 | 2012-09-27 | Osram Opto Semiconductors Gmbh | Anschlussträger für Halbleiterchips und Halbleiterbauelement |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000277923A (ja) * | 1999-03-29 | 2000-10-06 | Nec Corp | マザーボードプリント配線板およびその製造方法 |
| JP2001094227A (ja) * | 1999-09-20 | 2001-04-06 | Shinko Electric Ind Co Ltd | 半導体チップ実装用の配線基板と該基板を用いた半導体チップの実装方法 |
| JP2003198068A (ja) * | 2001-12-27 | 2003-07-11 | Nec Corp | プリント基板、半導体装置、およびプリント基板と部品との電気的接続構造 |
| JP2004247549A (ja) * | 2003-02-14 | 2004-09-02 | Fujitsu Ltd | 配線基板の作製方法および多層配線基板の作製方法 |
-
2009
- 2009-02-19 WO PCT/JP2009/052862 patent/WO2009104668A1/ja not_active Ceased
- 2009-02-19 JP JP2009554362A patent/JP5515744B2/ja not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000277923A (ja) * | 1999-03-29 | 2000-10-06 | Nec Corp | マザーボードプリント配線板およびその製造方法 |
| JP2001094227A (ja) * | 1999-09-20 | 2001-04-06 | Shinko Electric Ind Co Ltd | 半導体チップ実装用の配線基板と該基板を用いた半導体チップの実装方法 |
| JP2003198068A (ja) * | 2001-12-27 | 2003-07-11 | Nec Corp | プリント基板、半導体装置、およびプリント基板と部品との電気的接続構造 |
| JP2004247549A (ja) * | 2003-02-14 | 2004-09-02 | Fujitsu Ltd | 配線基板の作製方法および多層配線基板の作製方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2009104668A1 (ja) | 2009-08-27 |
| JPWO2009104668A1 (ja) | 2011-06-23 |
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