JP5515744B2 - 配線基板及び半導体装置 - Google Patents
配線基板及び半導体装置 Download PDFInfo
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Description
本発明は、日本国特許出願:特願2008−040335号(2008年2月21日出願)の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
本発明は、半導体パッケージ又は半導体チップを実装するための配線基板及び半導体装置に関し、特に、フリップチップ接続、CSP(Chip Scale Package)接続等に適した配線基板及び半導体装置に関する。
バンプを用いた従来技術において、LSIチップ−配線基板間がはんだバンプを介してフリップチップ接続される場合、弾性率が高いはんだバンプは、LSIチップ−配線基板間の熱膨張差により高い応力が発生し、はんだバンプ自身又ははんだバンプ近傍のLSIチップにおけるLSI回路を破壊するおそれがある。特に、ハイエンド向け大型ASIC(Application Specific Integrated Circuit)を中心にLSIチップにおける絶縁層のLow−k(低誘電率)化によるLSI回路の脆弱化が進行しており、特に、応力によるLSI回路の破壊が顕著になっている。
11 低弾性樹脂
12、112 実装パッド(パッド)
12a、112a 配線
12b 外周部
12c 結線部
13、113 絶縁層(基板)
13a 穴
14 金属層
20、120 半導体チップ(LSIチップ)
21、121 電極
30、130 バンプ(金属層)
131 樹脂コア
140 アンダーフィル樹脂
さらに、以下の形態も可能である。
前記絶縁層中に配設されるとともに、少なくとも前記凹部の底面に配された金属層を備えることが好ましい。
前記絶縁層上に形成されるとともに、前記外周部と接続された配線を備えることが好ましい。
前記結線部は、直線状、曲線状、斜線状、又はこれらの組合せで形成されていることが好ましい。
前記配線基板と、前記配線基板のパッドと対応する位置に電極を有する半導体チップ又は半導体パッケージと、前記パッドと前記電極の間に配設されるとともに、前記パッドと前記電極を電気的に接続するバンプと、を備える半導体装置とすることが好ましい。
Claims (5)
- 所定の位置に凹部を有する絶縁層と、
前記凹部内に埋め込まれるとともに、前記絶縁層よりも低弾性な低弾性樹脂と、
前記低弾性樹脂上に配設されるとともに、前記低弾性樹脂の領域よりも小さい領域のパッドと、
を備え、
前記低弾性樹脂の領域の外周の前記絶縁層上に配設されるとともに、前記パッドと同一材料よりなる外周部と、
前記低弾性樹脂の領域内であって前記実装パッドと前記外周部の間の領域の一部に配設されるとともに、前記パッドと同一材料よりなり、かつ、前記実装パッドと前記外周部を結線する1又は複数の結線部と、
を備えることを特徴とする配線基板。 - 前記絶縁層中に配設されるとともに、少なくとも前記凹部の底面に配された金属層を備えることを特徴とする請求項1記載の配線基板。
- 前記絶縁層上に形成されるとともに、前記外周部と接続された配線を備えることを特徴とする請求項1又は2記載の配線基板。
- 前記結線部は、直線状、曲線状、斜線状、又はこれらの組合せで形成されていることを特徴とする請求項1乃至3のいずれか一に記載の配線基板。
- 請求項1乃至4のいずれか一に記載の配線基板と、
前記配線基板のパッドと対応する位置に電極を有する半導体チップ又は半導体パッケージと、
前記パッドと前記電極の間に配設されるとともに、前記パッドと前記電極を電気的に接続するバンプと、
を備えることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2009554362A JP5515744B2 (ja) | 2008-02-21 | 2009-02-19 | 配線基板及び半導体装置 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP2008040335 | 2008-02-21 | ||
JP2008040335 | 2008-02-21 | ||
JP2009554362A JP5515744B2 (ja) | 2008-02-21 | 2009-02-19 | 配線基板及び半導体装置 |
PCT/JP2009/052862 WO2009104668A1 (ja) | 2008-02-21 | 2009-02-19 | 配線基板及び半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JPWO2009104668A1 JPWO2009104668A1 (ja) | 2011-06-23 |
JP5515744B2 true JP5515744B2 (ja) | 2014-06-11 |
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JP2009554362A Expired - Fee Related JP5515744B2 (ja) | 2008-02-21 | 2009-02-19 | 配線基板及び半導体装置 |
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WO (1) | WO2009104668A1 (ja) |
Families Citing this family (13)
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US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
CN101675516B (zh) | 2007-03-05 | 2012-06-20 | 数字光学欧洲有限公司 | 具有通过过孔连接到前侧触头的后侧触头的芯片 |
KR101538648B1 (ko) | 2007-07-31 | 2015-07-22 | 인벤사스 코포레이션 | 실리콘 쓰루 비아를 사용하는 반도체 패키지 공정 |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
US8796135B2 (en) | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
US8791575B2 (en) | 2010-07-23 | 2014-07-29 | Tessera, Inc. | Microelectronic elements having metallic pads overlying vias |
US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
US8610259B2 (en) | 2010-09-17 | 2013-12-17 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
US8637968B2 (en) | 2010-12-02 | 2014-01-28 | Tessera, Inc. | Stacked microelectronic assembly having interposer connecting active chips |
US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
US8587126B2 (en) | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US8610264B2 (en) * | 2010-12-08 | 2013-12-17 | Tessera, Inc. | Compliant interconnects in wafers |
DE102011014584A1 (de) * | 2011-03-21 | 2012-09-27 | Osram Opto Semiconductors Gmbh | Anschlussträger für Halbleiterchips und Halbleiterbauelement |
Citations (4)
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JP2000277923A (ja) * | 1999-03-29 | 2000-10-06 | Nec Corp | マザーボードプリント配線板およびその製造方法 |
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JP2004247549A (ja) * | 2003-02-14 | 2004-09-02 | Fujitsu Ltd | 配線基板の作製方法および多層配線基板の作製方法 |
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