JP4971243B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP4971243B2 JP4971243B2 JP2008128194A JP2008128194A JP4971243B2 JP 4971243 B2 JP4971243 B2 JP 4971243B2 JP 2008128194 A JP2008128194 A JP 2008128194A JP 2008128194 A JP2008128194 A JP 2008128194A JP 4971243 B2 JP4971243 B2 JP 4971243B2
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- opening
- wiring board
- chip
- resin
- corner
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
11…樹脂基板(配線基板本体)、
12,13…配線層、
12P,13P…パッド部(導体部)、
14,15…ソルダレジスト層(保護膜/絶縁層)、
18,18a,18b,18c…開口部、
20…半導体チップ(被実装体)、
23…バンプ(電極端子)、
30…アンダーフィル樹脂、
MA…チップの実装エリア、
EP,EP1,EP2,EP3…(開口部の)エッジ部、
P1〜P8、Q1〜Q8…(開口部の)コーナー部。
Claims (6)
- 平面的に見て多角形状で、かつ実装面側にバンプ状の電極端子を有する被実装体を実装したときに当該被実装体との間に樹脂が充填される配線基板であって、
前記被実装体の電極端子と接続される導体部が形成された配線基板本体と、
前記配線基板本体上に形成され、前記被実装体の外形に対応した実装エリアにおいて少なくとも前記導体部を露出させて形成された開口部を有する絶縁性の保護膜とを備え、
前記開口部は、少なくとも1箇所のコーナー部を除いて前記開口部のエッジ部が前記被実装体の実装エリアに沿ってその外側に位置し、かつ、前記少なくとも1箇所のコーナー部において前記開口部のエッジ部が当該被実装体の実装エリアの辺上もしくはその内側に位置するよう形成されるとともに、前記少なくとも1箇所のコーナー部を除いた他のコーナー部において局所的に広く開口されていることを特徴とする配線基板。 - 前記開口部は、前記少なくとも1箇所のコーナー部において前記開口部のエッジ部が当該被実装体の実装エリアの辺上もしくはその内側に位置するよう形成される代わりに、前記開口部のエッジ部が当該被実装体の実装エリアの角の位置を通るよう曲線状に形成されていることを特徴とする請求項1に記載の配線基板。
- 前記被実装体として平面的に見て方形状のものを実装する場合に、前記開口部は、最大2箇所のコーナー部において、前記開口部のエッジ部が当該被実装体の実装エリアの辺上もしくはその内側に位置するよう、あるいは当該被実装体の実装エリアの角の位置を通るよう曲線状に形成されていることを特徴とする請求項1又は2に記載の配線基板。
- 前記開口部は、前記被実装体の実装エリアに沿って環状に形成されていることを特徴とする請求項1に記載の配線基板。
- 前記開口部は、前記被実装体の実装エリアの全域にわたり開口されるよう形成されていることを特徴とする請求項1に記載の配線基板。
- 前記被実装体として半導体チップ、別の配線基板もしくは半導体装置を実装するよう適応されていることを特徴とする請求項1に記載の配線基板。
Priority Applications (3)
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JP2008128194A JP4971243B2 (ja) | 2008-05-15 | 2008-05-15 | 配線基板 |
CN2009101371949A CN101582395B (zh) | 2008-05-15 | 2009-05-14 | 布线基板 |
US12/465,964 US8378482B2 (en) | 2008-05-15 | 2009-05-14 | Wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2008128194A JP4971243B2 (ja) | 2008-05-15 | 2008-05-15 | 配線基板 |
Publications (2)
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JP2009277915A JP2009277915A (ja) | 2009-11-26 |
JP4971243B2 true JP4971243B2 (ja) | 2012-07-11 |
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JP2008128194A Active JP4971243B2 (ja) | 2008-05-15 | 2008-05-15 | 配線基板 |
Country Status (3)
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US (1) | US8378482B2 (ja) |
JP (1) | JP4971243B2 (ja) |
CN (1) | CN101582395B (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5378707B2 (ja) * | 2008-05-29 | 2013-12-25 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
KR102214512B1 (ko) * | 2014-07-04 | 2021-02-09 | 삼성전자 주식회사 | 인쇄회로기판 및 이를 이용한 반도체 패키지 |
JP6467797B2 (ja) * | 2014-07-14 | 2019-02-13 | 凸版印刷株式会社 | 配線基板、配線基板を用いた半導体装置およびこれらの製造方法 |
JP6557481B2 (ja) * | 2015-02-26 | 2019-08-07 | ローム株式会社 | 電子装置 |
US10672625B2 (en) | 2016-04-01 | 2020-06-02 | Intel Corporation | Electronic device package with recessed substrate for underfill containment |
US9899305B1 (en) * | 2017-04-28 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package structure |
US11282717B2 (en) | 2018-03-30 | 2022-03-22 | Intel Corporation | Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap |
EP3618586A1 (de) * | 2018-08-31 | 2020-03-04 | Siemens Aktiengesellschaft | Schaltungsträger mit einem einbauplatz für elektronische bauelemente, elektronische schaltung und herstellungsverfahren |
US11626336B2 (en) * | 2019-10-01 | 2023-04-11 | Qualcomm Incorporated | Package comprising a solder resist layer configured as a seating plane for a device |
TWI713166B (zh) * | 2020-02-17 | 2020-12-11 | 頎邦科技股份有限公司 | 晶片封裝構造及其電路板 |
FR3109466B1 (fr) * | 2020-04-16 | 2024-05-17 | St Microelectronics Grenoble 2 | Dispositif de support d’une puce électronique et procédé de fabrication correspondant |
Family Cites Families (11)
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JP2730004B2 (ja) | 1989-09-29 | 1998-03-25 | ウシオ電機株式会社 | 光源装置 |
JPH03115828U (ja) * | 1990-03-14 | 1991-12-02 | ||
US6048656A (en) * | 1999-05-11 | 2000-04-11 | Micron Technology, Inc. | Void-free underfill of surface mounted chips |
US6291264B1 (en) * | 2000-07-31 | 2001-09-18 | Siliconware Precision Industries Co., Ltd. | Flip-chip package structure and method of fabricating the same |
JP3773855B2 (ja) * | 2001-11-12 | 2006-05-10 | 三洋電機株式会社 | リードフレーム |
JP2005175113A (ja) * | 2003-12-10 | 2005-06-30 | Fdk Corp | フリップチップ実装用プリント配線基板 |
JP4536603B2 (ja) * | 2005-06-09 | 2010-09-01 | 新光電気工業株式会社 | 半導体装置の製造方法及び半導体装置用実装基板及び半導体装置 |
JP3115828U (ja) * | 2005-08-16 | 2005-11-17 | ハリマ化成株式会社 | 配線基板 |
JP4535969B2 (ja) * | 2005-08-24 | 2010-09-01 | 新光電気工業株式会社 | 半導体装置 |
JP4180622B2 (ja) * | 2005-11-16 | 2008-11-12 | アルプス電気株式会社 | 電子部品の実装構造、及びその実装方法 |
JP4366611B2 (ja) * | 2006-09-13 | 2009-11-18 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
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2009
- 2009-05-14 US US12/465,964 patent/US8378482B2/en active Active
- 2009-05-14 CN CN2009101371949A patent/CN101582395B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
US20090283317A1 (en) | 2009-11-19 |
US8378482B2 (en) | 2013-02-19 |
CN101582395A (zh) | 2009-11-18 |
CN101582395B (zh) | 2013-07-31 |
JP2009277915A (ja) | 2009-11-26 |
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