201003864 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶片封裝結構，且特別是有關於一種 具有散熱蓋的晶片封裝結構。 【先前技術】 圖1A至圖1B是習知一種晶片封裝結構的製造方法的流 程圖’圖2是習知另一種晶片封裝結構的示意圖。請先參照圖 1A’習知晶片封裝結構的製造方法是先將一晶片u〇組裝於 ί 一印刷電路板（printed circuit board，PCB) 120 上’且晶片 ι10 是透過多個凸塊112而電性連接至印刷電路板120。接著，於 晶片110之上表面114上塗佈一導熱膠材π〇。然後，進行回 焊（reflow)以使印刷電路板120的連接墊122上的焊料15〇 融溶’並使用治具將金屬蓋140組合於印刷電路板120的連接 墊122上，以藉由焊料150將金屬蓋140固著於連接墊122上 (如圖1B所示）。此金屬蓋140可用以防止電磁干擾 (electromagnetic interference, EMI)，並提供散熱功能。 〔 承上述，在將金屬蓋140組合於印刷電路板120時，需施 加壓力F1，以使金屬蓋140能下沈至連接墊122上，並提高 金屬盖140與導熱膠材130的接觸效果。然而，因將金屬蓋 140組合於印刷電路板120時需進行回焊，此會導致晶片11〇 的凸塊112融熔。若使用的導熱膠材130具有高流動性，則金 屬蓋140下壓時導熱膠材130所產生的應力較小，晶片11()的 凸塊112不易崩塌，但容易導致溢膠的情形（如圖1B所示）。 此外，如圖2所示，若使用的導熱膠材130具有低流動性，則 不易產生溢膠的情形’但由於金屬蓋140下壓時導熱膠材13〇 所產生的應力較大，其容易導致晶片110的凸塊112塌陷，進 6 201003864 而造成短路。因此，習知晶片封裝結構的生產良率較差。 【發明内容】 本么明&供一種晶片封裝結構，其具有較高的生產良率。 為達上述優點，本發明提出一種晶片封裝結構，其包括一 基板、一第一晶片、一第一導熱膠材、—第二導熱膠材以及一 散熱蓋’其中第一導熱膠材的流動性低於第二導熱膠材的流動 生基板具有一承載面’而第一晶片是配置於基板之承载面 上，且與基板電性連接。第一導熱膠材是配置於第一晶片之一 上表面上，且第一導熱膠材包括一第一封閉圖案。第二導熱膠 材疋配置於第一晶片之上表面上，且位於第一封閉圖案所圍出 的一第一封閉區域内。散熱蓋是配置於基板之承載面上，並覆 盍第一晶片、第一導熱膠材及第二導熱膠材，且散熱蓋與第一 導熱膠材及第二導熱膠材接觸。 在本發明之一實施例中，上述之第一導熱膠材更包括一第 二封閉圖案，位於第一封閉區域内。 在本發明之一實施例中，上述之第一導熱膠材更包括多個 柱體’位於第一封閉區域内。 在本發明之一實施例中，上述之第一晶片具有電性連接至 基板的多個凸塊。 在本發明之一實施例中，上述之基板之承載面的邊緣設有 一連接墊，而散熱蓋是配置於連接墊上，且散熱蓋是透過一焊 料而固著於基板上。 在本發明之一實施例中，上述之第一導熱膠材的黏滯係數 (viscosity coefficient)高於第二導熱膠材的黏滯係數。 在本發明之一實施例中’上述之晶片封裝結構，更包括一 第二晶片、一第三導熱膠材以及一第四導熱膠材，其中第二導 7 201003864 熱膠材的流動性低於第四導熱膠材的流動性。第二晶片是配置 於基板上’且與基板電性連接。第三導熱膠材是配置於第二晶 片之一上表面上，且第三導熱膠材包括一第三封閉圖案。第四 導熱膠材是配置於第二晶片之上表面上，且位於第三封閉圖案 f圍出的一第三封閉區域内。此外，散熱蓋更覆蓋第二晶片、 第二導熱膠材及第四導熱膠材，並與第三導熱膠材及第四導熱 膠材接觸。 在本發明之一實施例中，上述之第一晶片之上表面至承载 面的距離不同於第二晶片之上表面至承載面的距離。 在本發明之一實施例中，上述之第三導熱膠材的黏滯係數 高於第四導熱膠材的黏滯係數。 在本發明之一實施例中，上述之散熱蓋的材質包括金屬。 在本發明晶片封裝結構中，因流動性較高的第二導熱膝材 是位於流動性較低的第一封閉圖案内，所以在製造時能避免產 生溢膠的情形。此外，由於使用低流動性的第二導熱膠材，所 以能減少散熱蓋下壓時的應力，如此可防止晶片封裝結構中的 元件受損。因此，本發明之晶片封裝結構能提高生產良率。 為讓本發明之上述和其他目的、特徵和優點能更明顯易 懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 圖3是本發明一實施例之一種晶片封裝結構的剖面示意 圖，圖4是圖3之晶片封裝結構未組裝散熱蓋時的立體示意 圖。請參照圖3與圖4 ’本實施例之晶片封裝結構200包括一 基板210、一第一晶片220、一第一導熱膠材230、一第二導 熱膠材240以及一散熱蓋250，其中第一導熱膠材230的流動 性低於第二導熱膠材240的流動性。基板21〇具有一承載面 8 201003864 212，而第一晶片220是配置於基板210之承載面212上，且 與基板210電性連接。第一導熱膠材230是配置於第一晶片 220之一上表面222上，且第一導熱膠材230例如是於第一晶 片220之上表面222上形成一第一封閉圖案。第二導熱膠材 240是配置於第一晶片220之上表面222上，且位於第一封閉 圖案（即第一導熱膠材230)所圍出的一第一封閉區域232内。 散熱蓋250是配置於基板210之承載面212上，並覆蓋第一晶 片220、第一導熱膠材230及第二導熱膠材240,且散熱蓋250 與第一導熱膠材230及第二導熱膠材240接觸。 上述之晶片封裝結構200中，基板210例如是印刷電路 板。第一晶片220例如具有多個凸塊224，以使第一晶片220 透過凸塊224而電性連接至基板210。當然，本發明並不限定 第一晶片220電性連接至基板210的方式。此外，基板210之 承載面212的邊緣設有一連接墊214，且連接墊214上設有焊 料260。散熱蓋250是配置於連接墊214上，並透過焊料260 而固著於基板210上。散熱蓋250的材質可包括金屬，如此可 用以防止電磁干擾。另外，第二導熱膠材240例如是填滿第一 封閉區域232。第一導熱勝材230與第二導熱膠材240可為導 熱膠或導熱膏。第一導熱膠材230的黏滯係數例如是高於第二 導熱膠材240的黏滯係數。 由於第一導熱膠材230與第二導熱膠材240是配置於第一 晶片220上，且散熱蓋250與第一導熱膠材230及第二導熱膠 材240接觸，所以第一晶片220所產生的熱能可經由第一導熱 膠材230與第二導熱膠材240而傳遞至散熱蓋250，如此可藉 由散熱蓋250將熱能散逸至外界。 以下將介紹本實施例之晶片封裝結構200的製造方法，而 9 201003864 圖5A至圖5C是圖3之晶片封裝結構的製造方法的流程圖。 請先參照圖5A，本實施例之晶片封裝結構的製造方法是先將 第一晶片220組裝於基板210上，並進行回焊。接著，如圖 5B所示，將第一導熱膠材230塗佈於第一晶片220的上表面 222，以圍出第一封閉區域232。之後，如圖5C所示，將第二 導熱膠材240塗佈於第一封閉區域232内，接著進行回焊使焊 料260融炫’並使用治具將散熱蓋250組合於基板210的連接 墊214上。散熱蓋250組合於基板210後的結構如圖3所示。 承上述，在將散熱蓋250組合於基板210的過程中，雖然 需施加壓力F2 ’以使散熱蓋250能下沈至連接墊214上，並 提高散熱蓋250與第一導熱膠材230及第二導熱膠材240的接 觸效果。然而，由於第一導熱膠材230的流動性較低，所以第 一導熱膠材230不容易產生溢流的情形。此外，雖然第二導熱 膠材240的流動性較高，但可藉由第一導熱膠材230來防止第 二導熱膠材240溢流。另外，在本實施例中，由於同時使用流 動性較低的第一導熱膠材230以及流動性較高的第二導熱膠 材240,所以可減少散熱蓋250下壓時的應力，以防止凸塊224 塌陷。因此，本實施例之晶片封裝結構200在製造時能有效防 止膠材溢流及凸塊224塌陷，進而提高生產良率。 在本發明中第一導熱膠材230除了包括第一封閉圖案 外’還可更包括其他圖案。圖6A與圖6B是本發明另二實施 例中塗佈於第一晶片上之第一導熱膠材與第二導熱膠材的俯 視圖。請先參照圖6A，本實施例之晶片封裝結構的第一導熱 膠材230’包括第一封閉圖案234以及第二封閉圖案236 ’且第 二封閉圖案236是位於第一封閉圖案234所圍出的第一封閉區 域232内。請參照圖6B，本實施例之晶片封裝結構的第—導 201003864 熱膠材230”包括第一封閉圖案234以及位於第一封閉區域232 内的多個柱體238。 由於流動性較低的導熱膠材其導熱性較佳，因此在第一封 閉圖案234内增設第二封閉圖案236或柱體238，可提高導熱 效果’進而提升晶片封裝結構的散熱效果。 圖7是本發明另一實施例之晶片封裝結構的剖面示意 圖。請參照圖7 ’本實施例之晶片封裝結構2〇〇,與圖3之晶片 封裝結構200相似，不同處在於晶片封裴結構200,更包括一第 二晶片270、一第三導熱膠材280以及一第四導熱勝材290， 其中第三導熱膠材280的流動性低於第四導熱膠材290的流動 性。第二晶片270是配置於基板210上，且與基板210電性連 接。第三導熱膠材280是配置於第二晶片270之一上表面272 上，且第三導熱膠材280例如是於第二晶片270之上表面272 上形成一第三封閉圖案。第四導熱膠材290是配置於第二晶片 270之上表面272上，且位於第三封閉圖案（即第三導熱膠材 280)所圍出的一第三封閉區域282内。此外，散熱蓋250更 覆蓋第二晶片270、第三導熱膠材280及第四導熱膠材290， 並與第三導熱膠材280及第四導熱膠材290接觸。 上述之晶片封裝結構200’中，第二晶片270例如具有多 個凸塊274，以使第二晶片270透過凸塊274而電性連接至基 板210。當然，本發明並不限定第二晶片270電性連接至基板 210的方式。此外，第四導熱膠材290例如是填滿第三封閉區 域282。第三導熱膠材280與第四導熱膠材290可為導熱膠或 導熱膏。第三導熱膠材280的黏滯係數例如是高於第四導熱膠 材290的黏滞係數。 本實施例之晶片封裝結構200’的優點與圖3之晶片封裝 11 201003864 結構200的優點相似。此外，由於第一導熱膠材23〇與第三導 熱膠材280的流動性較低，其厚度較容易控制，因此/第一晶片 220之上表面222至基板210的承載面212的距離D1可不同 於第二晶片270之上表面272至基板210的承載面212的距離 =2。換言之，第一晶片22〇相對於基板21〇的高度可不同於 第二晶片270相對於基板210的高度。 綜上所述，本發明之晶片封裝結構至少具有下列優點： 1. 因流動性較高的第二導熱膠材是位於流動性較低的第 —封閉圖案内，所以本發明晶片封裝結構在製造時能避免產生 溢膠的情形。此外，由於使用低流動性的第二導熱膠材，所以 月b減少散熱蓋下壓時的應力，如此可防止晶片封裝結構中的部 件X損。因此，本發明之晶片封裝結構具有較高的生產良率。 2. 在一實施例中，由於第一導熱膠材與第三導熱膠材的流 動性較低，其厚度較容易控制，因此第一晶片相對於基板的高 度可不同於第二晶片相對於基板的高度。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定 本發明’本發明所屬技術領域中具有通常知識者，在不脫離本 發明之精神和範圍内，當可作些許之更動與潤飾，因此本發明 之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A至圖1B是習知一種晶片封裝結構的製造方法的流 程圖。 圖2是習知另一種晶片封裝結構的示意圖。 圖3是本發明一實施例之一種晶片封裝結構的剖面示意 圖。 圖4是圖3之晶片封裝結構未組裝散熱蓋時的立體示意 201003864 圖。 圖5A至圖5C是圖3 之晶片封裝結構的201003864 IX. Description of the Invention: [Technical Field] The present invention relates to a chip package structure, and more particularly to a chip package structure having a heat dissipation cover. 1A to 1B are flow diagrams of a conventional method of fabricating a chip package structure. FIG. 2 is a schematic view of another conventional chip package structure. Referring to FIG. 1A, a conventional method for fabricating a chip package structure is to first mount a wafer u on a printed circuit board (PCB) 120 and the wafer ι10 is electrically transmitted through a plurality of bumps 112. Connected to the printed circuit board 120. Next, a thermal conductive adhesive π 涂布 is applied on the upper surface 114 of the wafer 110. Then, reflow is performed to melt the solder 15 on the connection pads 122 of the printed circuit board 120 and the metal cover 140 is combined on the connection pads 122 of the printed circuit board 120 by soldering to solder 150 attaches the metal cover 140 to the connection pad 122 (as shown in FIG. 1B). This metal cover 140 can be used to prevent electromagnetic interference (EMI) and provide a heat dissipation function. [In the above, when the metal cover 140 is assembled to the printed circuit board 120, a pressure F1 is applied to enable the metal cover 140 to sink onto the connection pad 122, and the contact effect of the metal cover 140 with the thermal conductive material 130 is improved. However, re-soldering is required when the metal cover 140 is assembled to the printed circuit board 120, which causes the bumps 112 of the wafer 11 to be melted. If the thermal conductive adhesive 130 used has high fluidity, the stress generated by the thermal conductive adhesive 130 when the metal cover 140 is pressed down is small, and the bumps 112 of the wafer 11 are not easily collapsed, but the overflowing is likely to occur (eg, Figure 1B)). In addition, as shown in FIG. 2, if the heat conductive adhesive 130 used has low fluidity, it is not easy to generate a spillage condition. However, since the stress generated by the thermal conductive adhesive 13 is large when the metal cover 140 is pressed, it is easy. This causes the bumps 112 of the wafer 110 to collapse, entering 6 201003864 and causing a short circuit. Therefore, the production yield of the conventional chip package structure is poor. SUMMARY OF THE INVENTION The present invention provides a wafer package structure having a high production yield. In order to achieve the above advantages, the present invention provides a chip package structure including a substrate, a first wafer, a first thermal conductive adhesive material, a second thermal conductive adhesive material, and a heat dissipating cover, wherein the first thermal conductive adhesive material has fluidity. The flow-generating substrate below the second thermal conductive material has a bearing surface ′, and the first wafer is disposed on the bearing surface of the substrate and electrically connected to the substrate. The first thermal conductive adhesive material is disposed on an upper surface of the first wafer, and the first thermal conductive adhesive material includes a first closed pattern. The second thermal conductive material is disposed on the upper surface of the first wafer and located in a first enclosed area surrounded by the first closed pattern. The heat dissipating cover is disposed on the bearing surface of the substrate, and covers the first wafer, the first thermal conductive adhesive material and the second thermal conductive adhesive material, and the heat dissipating cover is in contact with the first thermal conductive adhesive material and the second thermal conductive adhesive material. In an embodiment of the invention, the first thermal conductive adhesive material further includes a second closed pattern located in the first enclosed region. In an embodiment of the invention, the first thermally conductive rubber material further comprises a plurality of cylinders ' located in the first enclosed region. In an embodiment of the invention, the first wafer has a plurality of bumps electrically connected to the substrate. In an embodiment of the invention, the edge of the bearing surface of the substrate is provided with a connection pad, and the heat dissipation cover is disposed on the connection pad, and the heat dissipation cover is fixed on the substrate through a solder. In an embodiment of the invention, the viscosity coefficient of the first thermal conductive material is higher than the viscosity coefficient of the second thermal conductive rubber. In one embodiment of the present invention, the above-mentioned chip package structure further includes a second wafer, a third thermal conductive adhesive material and a fourth thermal conductive adhesive material, wherein the second conductive material of the second guide 7 201003864 is lower than the fluidity of the second adhesive material The fluidity of the fourth thermal conductive adhesive. The second wafer is disposed on the substrate and electrically connected to the substrate. The third thermal conductive adhesive material is disposed on an upper surface of the second crystal wafer, and the third thermal conductive adhesive material includes a third closed pattern. The fourth thermal conductive adhesive material is disposed on the upper surface of the second wafer and located in a third closed region surrounded by the third closed pattern f. In addition, the heat dissipation cover further covers the second wafer, the second thermal conductive adhesive material and the fourth thermal conductive adhesive material, and is in contact with the third thermal conductive adhesive material and the fourth thermal conductive adhesive material. In an embodiment of the invention, the distance from the upper surface of the first wafer to the carrying surface is different from the distance from the upper surface of the second wafer to the bearing surface. In an embodiment of the invention, the viscous coefficient of the third thermal conductive adhesive material is higher than the viscous coefficient of the fourth thermal conductive adhesive. In an embodiment of the invention, the material of the heat dissipation cover comprises metal. In the wafer package structure of the present invention, since the second heat-conductive knee material having a high fluidity is located in the first closed pattern having a low fluidity, it is possible to avoid the occurrence of overflow during manufacture. In addition, since the second heat-conductive adhesive material having a low fluidity is used, the stress at the time of pressing down the heat-dissipating cover can be reduced, thereby preventing damage of components in the chip package structure. Therefore, the chip package structure of the present invention can improve the production yield. The above and other objects, features and advantages of the present invention will become more <RTIgt; 3 is a schematic cross-sectional view showing a chip package structure according to an embodiment of the present invention, and FIG. 4 is a perspective view showing a state in which the chip package structure of FIG. 3 is not assembled with a heat dissipation cover. Referring to FIG. 3 and FIG. 4, the chip package structure 200 of the present embodiment includes a substrate 210, a first wafer 220, a first thermal conductive adhesive 230, a second thermal conductive adhesive 240, and a heat dissipation cover 250. The fluidity of the thermal conductive rubber 230 is lower than the fluidity of the second thermal conductive rubber 240. The substrate 21 has a bearing surface 8 201003864 212, and the first wafer 220 is disposed on the bearing surface 212 of the substrate 210 and electrically connected to the substrate 210. The first thermal conductive adhesive 230 is disposed on an upper surface 222 of the first wafer 220, and the first thermal conductive adhesive 230 forms a first closed pattern on the upper surface 222 of the first wafer 220, for example. The second thermal conductive paste 240 is disposed on the upper surface 222 of the first wafer 220 and is disposed in a first enclosed region 232 surrounded by the first closed pattern (ie, the first thermal conductive paste 230). The heat dissipation cover 250 is disposed on the bearing surface 212 of the substrate 210 and covers the first wafer 220, the first thermal conductive adhesive 230 and the second thermal conductive adhesive 240, and the heat dissipation cover 250 and the first thermal conductive adhesive 230 and the second thermal conduction. The glue 240 is in contact. In the above wafer package structure 200, the substrate 210 is, for example, a printed circuit board. The first wafer 220 has a plurality of bumps 224 , for example, to electrically connect the first wafer 220 to the substrate 210 through the bumps 224 . Of course, the present invention does not limit the manner in which the first wafer 220 is electrically connected to the substrate 210. In addition, a connecting pad 214 is disposed on the edge of the bearing surface 212 of the substrate 210, and a solder 260 is disposed on the connecting pad 214. The heat dissipation cover 250 is disposed on the connection pad 214 and is fixed to the substrate 210 by the solder 260. The material of the heat dissipation cover 250 may include metal so as to prevent electromagnetic interference. Additionally, the second thermally conductive adhesive 240 fills, for example, the first enclosed region 232. The first thermal conductive material 230 and the second thermal conductive adhesive 240 may be a thermal conductive paste or a thermal conductive paste. The viscous coefficient of the first thermally conductive adhesive 230 is, for example, higher than the viscous coefficient of the second thermally conductive adhesive 240. Since the first thermal conductive adhesive 230 and the second thermal conductive adhesive 240 are disposed on the first wafer 220, and the heat dissipation cover 250 is in contact with the first thermal conductive adhesive 230 and the second thermal conductive adhesive 240, the first wafer 220 is generated. The thermal energy can be transmitted to the heat dissipation cover 250 via the first thermal conductive adhesive 230 and the second thermal conductive adhesive 240, so that the thermal energy can be dissipated to the outside by the heat dissipation cover 250. A method of fabricating the chip package structure 200 of the present embodiment will be described below, and 9 201003864 FIGS. 5A to 5C are flowcharts showing a method of fabricating the chip package structure of FIG. 3. Referring to FIG. 5A, in the method of fabricating the chip package structure of the present embodiment, the first wafer 220 is first assembled on the substrate 210 and reflowed. Next, as shown in FIG. 5B, the first thermal conductive paste 230 is applied to the upper surface 222 of the first wafer 220 to enclose the first enclosed region 232. Thereafter, as shown in FIG. 5C, the second thermal conductive adhesive 240 is applied to the first closed region 232, followed by reflow soldering to melt the solder 260' and the heat dissipating cover 250 is assembled to the connection pad of the substrate 210 using the jig. 214. The structure in which the heat dissipation cover 250 is combined with the substrate 210 is as shown in FIG. In the above, in the process of assembling the heat dissipation cover 250 to the substrate 210, the pressure F2′ is required to enable the heat dissipation cover 250 to sink onto the connection pad 214, and the heat dissipation cover 250 and the first thermal conductive adhesive 230 and the first The contact effect of the two thermal conductive adhesives 240. However, since the fluidity of the first thermally conductive rubber 230 is low, the first thermally conductive rubber 230 is less prone to overflow. Further, although the fluidity of the second thermal conductive paste 240 is high, the second thermal conductive adhesive 240 can be prevented from overflowing by the first thermal conductive adhesive 230. In addition, in the present embodiment, since the first thermal conductive adhesive 230 having lower fluidity and the second thermal conductive adhesive 240 having higher fluidity are simultaneously used, the stress when the heat dissipating cover 250 is pressed can be reduced to prevent the convexity. Block 224 collapses. Therefore, the chip package structure 200 of the present embodiment can effectively prevent the glue overflow and the bump 224 from collapsing during manufacture, thereby improving the production yield. In the present invention, the first thermal conductive paste 230 may further include other patterns in addition to the first closed pattern. 6A and 6B are top views of a first thermally conductive adhesive and a second thermally conductive adhesive applied to a first wafer in another embodiment of the present invention. Referring to FIG. 6A , the first thermal conductive adhesive 230 ′ of the chip package structure of the embodiment includes a first closed pattern 234 and a second closed pattern 236 ′ and the second closed pattern 236 is located outside the first closed pattern 234 . Within the first enclosed area 232. Referring to FIG. 6B, the first guide 201003864 of the wafer package structure of the present embodiment includes a first closed pattern 234 and a plurality of pillars 238 located in the first closed region 232. The heat conduction is low due to low fluidity. The rubber material has better thermal conductivity. Therefore, the second sealing pattern 236 or the pillar 238 is added to the first sealing pattern 234, which can improve the heat conduction effect and thereby improve the heat dissipation effect of the chip package structure. FIG. 7 is another embodiment of the present invention. FIG. 7 is a schematic view similar to the chip package structure 200 of FIG. 3, except that the chip package structure 200 further includes a second wafer 270. a third thermal conductive material 280 and a fourth thermal conductive material 290, wherein the third thermal conductive adhesive 280 has a lower fluidity than the fourth thermal conductive adhesive 290. The second wafer 270 is disposed on the substrate 210. The third thermal conductive adhesive 280 is disposed on the upper surface 272 of the second wafer 270, and the third thermal conductive adhesive 280 is formed on the upper surface 272 of the second wafer 270, for example. Three closed The fourth thermal conductive adhesive 290 is disposed on the upper surface 272 of the second wafer 270 and located in a third enclosed region 282 surrounded by the third closed pattern (ie, the third thermal conductive adhesive 280). The heat dissipation cover 250 further covers the second wafer 270, the third thermal conductive adhesive 280 and the fourth thermal conductive adhesive 290, and is in contact with the third thermal conductive adhesive 280 and the fourth thermal conductive adhesive 290. In the above wafer package structure 200', The second wafer 270 has, for example, a plurality of bumps 274 to electrically connect the second wafer 270 to the substrate 210 through the bumps 274. Of course, the present invention does not limit the manner in which the second wafer 270 is electrically connected to the substrate 210. In addition, the fourth thermal conductive adhesive 290 is filled, for example, to fill the third closed region 282. The third thermal conductive adhesive 280 and the fourth thermal conductive adhesive 290 may be a thermal conductive adhesive or a thermal conductive paste. The viscous coefficient of the third thermal conductive adhesive 280 is, for example, It is higher than the viscosity coefficient of the fourth thermal conductive adhesive 290. The advantages of the wafer package structure 200' of the present embodiment are similar to those of the wafer package 11 201003864 structure 200 of Fig. 3. In addition, since the first thermal conductive adhesive 23 is The third thermal conductive adhesive 280 has low fluidity The thickness thereof is relatively easy to control, so the distance D1 from the upper surface 222 of the first wafer 220 to the bearing surface 212 of the substrate 210 may be different from the distance from the upper surface 272 of the second wafer 270 to the bearing surface 212 of the substrate 210 = 2. In other words The height of the first wafer 22〇 relative to the substrate 21〇 may be different from the height of the second wafer 270 relative to the substrate 210. In summary, the chip package structure of the present invention has at least the following advantages: 1. High fluidity The second thermal conductive adhesive material is located in the first closed pattern of fluidity, so that the chip package structure of the present invention can avoid the occurrence of overflow during manufacture. Further, since the low-flow second heat-conductive adhesive material is used, the month b reduces the stress at the time of the heat-dissipation cover pressing, so that the X loss of the member in the chip package structure can be prevented. Therefore, the wafer package structure of the present invention has a high production yield. 2. In an embodiment, since the fluidity of the first thermal conductive rubber and the third thermal conductive rubber is relatively low, the thickness thereof is relatively easy to control, and thus the height of the first wafer relative to the substrate may be different from the second wafer relative to the substrate. the height of. Although the present invention has been disclosed in the above preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A to 1B are flowcharts showing a conventional method of fabricating a chip package structure. 2 is a schematic view of another conventional chip package structure. Figure 3 is a cross-sectional view showing a chip package structure in accordance with an embodiment of the present invention. 4 is a perspective view of the semiconductor package of FIG. 3 when the heat dissipating cover is not assembled, 201003864. 5A to 5C are the wafer package structure of FIG.
圖。 圖6A與圖6B是本發明另二實施例中塗佈於第一 晶片上 之第一導熱膠材與第二導熱膠材的俯視圖。 圖7是本發明另-實施例之晶片封t結構的剖面示意圖。 【主要元件符號說明】 110 .晶片 112、224、274 :凸塊 114、222、272 :上表面 120 :印刷電路板 122、214 :連接墊 130 :導熱膠材 140 :金屬蓋 150、260 :焊料 200、200” ：晶片封裝結構 210 :基板 212 :承載面 220 :第一晶片 230、230,、230” ：第一導熱膠材 232 :第一封閉區域 234 :第一封閉圖案 236 :第二封閉圖案 238 :柱體 240 :第二導熱膠材 250 ·‘散熱蓋 13 201003864 270 :第二晶片 280 :第三導熱膠材 282 :第三封閉區域 290 :第四導熱膠材 Dl、D2 :距離 FI、F2 :壓力Figure. 6A and 6B are plan views of a first thermal conductive adhesive and a second thermal conductive adhesive coated on a first wafer in another embodiment of the present invention. Figure 7 is a cross-sectional view showing the structure of a wafer package t according to another embodiment of the present invention. [Main component symbol description] 110. Wafers 112, 224, 274: bumps 114, 222, 272: upper surface 120: printed circuit board 122, 214: connection pad 130: thermal conductive adhesive 140: metal cover 150, 260: solder 200, 200": chip package structure 210: substrate 212: bearing surface 220: first wafer 230, 230, 230": first thermal conductive adhesive 232: first closed area 234: first closed pattern 236: second closed Pattern 238: cylinder 240: second thermal conductive material 250 · 'heat dissipation cover 13 201003864 270 : second wafer 280 : third thermal conductive adhesive 282 : third closed region 290 : fourth thermal conductive adhesive Dl, D2 : distance FI , F2: pressure