CN105374783B - 半导体边界保护密封剂 - Google Patents

半导体边界保护密封剂 Download PDF

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Publication number
CN105374783B
CN105374783B CN201510197236.3A CN201510197236A CN105374783B CN 105374783 B CN105374783 B CN 105374783B CN 201510197236 A CN201510197236 A CN 201510197236A CN 105374783 B CN105374783 B CN 105374783B
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semiconductor
wafer
groove
active circuit
protective
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CN105374783A (zh
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赵子群
加伦·柯克帕特里克
罗立德
雷佐尔·拉赫曼·卡恩
施明煌
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Avago Technologies International Sales Pte Ltd
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Avago Technologies General IP Singapore Pte Ltd
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Abstract

本发明涉及半导体边界保护密封剂，其中，半导体封装包括包含有源电路层的半导体单元。半导体封装还包括有源电路层上的多个接合焊盘，多个接合焊盘被配置为连接至相应的外部导电连接器。半导体封装还包括填充有源电路层的凹槽边缘的保护密封涂层。保护密封涂层包含外部晶圆分离表面。

Description

半导体边界保护密封剂
相关申请
本申请要求于2014年10月20日提交的美国申请第14/518,947号和2014年8月15日提交的美国临时申请第62/037,899号的优先权，其全部内容通过引用结合于此。
技术领域
本发明涉及半导体封装。
背景技术
半导体封装可以是包含一个或多个半导体电子组件的金属壳、塑料壳、玻璃壳、或者陶瓷壳，也称为裸片或者集成电路(IC)。封装提供对冲击和腐蚀、以及环境因素(诸如湿气、氧化、高温、及污染物)的保护措施。电接触或者导线从封装伸出并被连接到其他装置和/或至中间的基板，或者直接至电路板。封装可以仅有两个导线或者接触用于诸如二极管的装置，或者在微处理器的情况下具有几百个导线或者接触。
半导体封装可以是专用的独立装置，可以装配至最终产品的印刷电路板(PCB)或者印刷线路板(PWB)。IC可以连接至各种布置的基板，以及堆叠多层。另外，封装可以装配在其他封装之上以形成封装堆叠装置。半导体封装也可以装配至柔性电路，诸如胶带。
具有几个特征与功能的用户产品变得更加复杂。另外，许多用户产品变得更小。因此，制造商利用封装替代作为在更小的区域或者体积中达到更多特征与功能的方法。
半导体封装可以完全以晶圆级制造，包括以栅阵列配置制作单个IC、多级金属喷镀、封装、及焊球的粘接(或者其他传导性互连)。完成的晶圆然后被分离，即，分为单个的封装的IC。
分离的通用方法是沿着IC之间的划片街区(saw street)锯切晶圆。晶圆划片完全切割穿过单个封装的IC。然而，锯切可能损伤接近切口的区域，尤其介质层与金属喷镀层。另外，由于在分离过程中的密封圈的损伤，裸片涂层可能变得与金属喷镀层分层。因此，分层可能穿透裸片的密封圈内部并且导致IC的最终失败。附加过程也可能导致分层继续传播。其他类型的分离包括隐形切片和等离子体切片。
发明内容
在实施方式中，半导体封装包括包含有源电路层的半导体单元。半导体封装还包括有源电路层上的多个接合焊盘，多个接合焊盘被配置为连接至相应的外部导电连接器。半导体封装还包括填充有源电路层的所有凹槽边缘的保护密封涂层。保护密封涂层包含外部晶圆分离表面(exterior wafer-singulated surface，外部被单一化晶圆表面)。
优选地，所述外部晶圆切割表面(exterior wafer-cut surface，外部被切割晶圆表面)包括锯切、蚀刻或者激光改变的边缘的一个或多个。
优选地，所述保护密封涂层至少部分地覆盖所述半导体单元的裸片(die)的周边。
优选地，所述半导体封装进一步包括：焊球外部导电连接器。
优选地，所述半导体封装进一步包括：接合线外部导电连接器。
优选地，所述半导体封装进一步包括：附加保护密封涂层，围绕所述有源电路层上的所述外部导电连接器。
优选地，所述半导体封装进一步包括：附加保护密封涂层，在所述半导体单元的非活性表面上。
优选地，所述保护密封涂层减小或者消除围绕每个所述半导体单元的密封圈。
在另一种实施方式中，半导体封装包括具有有源电路表面和非活性表面的半导体单元。半导体封装还包括沿着有源电路表面的所有暴露的边缘形成并且部分地沿着半导体单元的裸片边缘延伸的凹槽。半导体封装还包括填充在凹槽内并具有切割的、锯切的、蚀刻的、或者激光修改的外部表面的保护密封涂层。
优选地，所述裸片边缘的剩余部分包含晶圆切割边缘。
优选地，所述凹槽沿着所述半导体单元的所述裸片边缘延伸。
优选地，所述保护密封涂层的所述切割的、锯切的、蚀刻的、或者激光改变的外表面沿着所述半导体单元的所述裸片边缘延伸。
优选地，所述半导体封装进一步包括保护密封涂层，在所述半导体单元的所述非活性表面上。
优选地，所述半导体封装进一步包括多个焊球，以球栅阵列在所述有源电路表面上。
优选地，所述半导体封装包括焊线接合的半导体封装(wire-bondedsemiconductor package)。
优选地，所述保护密封涂层取代围绕每个所述半导体单元的密封圈。
在另一种实施方式中，制造半导体封装的方法包括将载带(carry tape)粘附至半导体晶圆的非活性表面。方法还包括在所述半导体晶圆的半导体单元之间切割或者蚀刻凹槽。凹槽通过半导体晶圆的有源电路层切割或者蚀刻。方法还包括将保护密封涂层材料施加到半导体单元之间的凹槽中，并通过保护密封涂层材料分离(singulate，单一化)半导体单元。
优选地，所述方法进一步包括：将膜粘附至所述半导体晶圆的外部导电连接器；以及围绕所述外部导电连接器施加所述保护密封涂层材料。
优选地，所述方法进一步包括穿过所述半导体单元之间的所述半导体晶圆切割或者蚀刻所述凹槽。
优选地，所述凹槽通过切割与蚀刻步骤的组合来形成。
优选地，所述施加发生在外部导电连接器连接至所述半导体单元之前。
优选地，所述方法进一步包括照射并去除通过掩模中的开口暴露的所述保护密封涂层材料，所述开口对应于所述有源电路层的下面的接合焊盘。
优选地，所述方法进一步包括：在仍以晶圆形式的封装之后或者作为分离的所述半导体单元的最后测试，利用裸片探测器测试所述半导体单元。
在另一种实施方式中，制造半导体封装的方法包括将多个半导体器件以板条格式或阵列格式粘附至粘性载体。格式包含相邻的每对半导体器件之间的间隙。方法还包括在间隙内施加塑封料(mold compound)，其中，塑封料围绕所有暴露的有源电路边缘。方法还包括通过施加的塑封料分离多个半导体器件。
优选地，所述方法进一步包括：将外部焊球连接至有源电路层的相应的接触焊盘；以及在所述有源电路层上施加所述塑封料以包围连接的所述外部焊球。
优选地，所述方法进一步包括在所述有源电路层与施加至所述外部焊球的底表面的膜之间的所述有源电路层上施加所述塑封料。
优选地，所述方法进一步包括：激光烧蚀施加至所述外部焊球的底表面的所述塑封料。
优选地，所述方法进一步包括：通过暴露的裸片模套(exposed die chase)或者压模(compression mold)之一在所述间隙内和所述有源电路层上施加所述塑封料。
优选地，所述方法进一步包括：在施加至所述多个半导体器件的背表面的所述塑封料上标记所述多个半导体器件。
优选地，所述多个半导体器件包括重构的半导体器件。
优选地，所述方法进一步包括：在以面板形式的裸片重构和铸模成型之后、在成型的面板被分成条状之后、或者作为分离的所述半导体器件的最后测试，测试所述多个半导体器件。
已经通过总体介绍的方式提供了前述段落，但不旨在限制以下权利要求的范围。通过参照以下结合附图所做的详细描述，可更好地理解所描述的实施方式和另外的优点。
附图说明
本公开内容的更完整的评价和其许多附带的优点将容易地被获得，如同通过结合附图所考虑的以下详细描述而变得更好理解那样，其中：
图1A至图1B分别是根据一种实施方式的IC晶圆与单个分离的(singulated)IC的示意图；
图2A至图2B是根据一种实施方式的IC的活性表面上的接合焊盘图案的示意图；
图3A至图3D分别是根据一种实施方式的具有外部连接器的晶圆的截面图；
图4A是根据一种实施方式的具有划片街区槽(saw street groove)的晶圆级球栅阵列(WLBGA)的截面图；
图4B是根据一种实施方式的具有保护涂层填充的划片街区槽的WLBGA的截面图；
图4C是根据一种实施方式的具有密封圈的晶圆级IC的顶视图；
图4D是根据一种实施方式的没有密封圈的晶圆级IC的顶视图；
图5A至图5B分别是根据一种实施方式的分离的半导体单元的截面图与3D底视图；
图6是根据一种实施方式的切割为半导体单元的全部晶圆的截面图；
图7是根据一种实施方式的半导体单元之间填充的保护涂层的截面图；
图8A至图8B分别是根据一种实施方式的分离半导体单元的截面图与3D底视图；
图9是根据一种实施方式的在半导体单元之间并且在半导体单元的顶部填充的保护涂层的截面图；
图10A至图10B分别是根据一种实施方式的分离的半导体单元的截面图与3D底视图与顶视图；
图11A是根据一种实施方式的将要连接至基板的BGA半导体单元的截面图；
图11B是根据一种实施方式的连接至基板的焊线接合的半导体单元的截面图；
图12A是根据一种实施方式的晶圆的截面图；
图12B是根据一种实施方式的具有划片街区槽的晶圆的截面图；
图13A是根据一种实施方式的具有划片街区槽和粘接的掩模带(mask tape)的晶圆的截面图；
图13B至图13C分别是根据一种实施方式的晶圆的图案化掩模带与保护填充的凹槽的截面图；
图14A至图14B分别是根据一种实施方式的分离的半导体单元的截面图与3D底视图；
图15是根据一种实施方式的具有两个划片街区槽的晶圆的截面图；
图16是根据一种实施方式的具有施加的载带(carry tape)和掩模带的晶圆的截面图；
图17A至图17B示出根据一种实施方式的具有保护填充的划片街区的晶圆的截面图；
图18A至图18B分别是根据一种实施方式的分离半导体单元的截面图与3D底视图；
图18C至图18D分别是根据一种实施方式的分离的半导体单元的截面图与3D底视与顶视图；
图19是根据一种实施方式的用于制造半导体封装的方法的流程图；
图20A示出根据一种实施方式的重构半导体器件的阵列；
图20B示出根据一种实施方式的在重构半导体器件阵列上的塑封料；
图20C示出根据一种实施方式的在激光烧蚀之后的重构半导体器件阵列；
图20D示出根据一种实施方式的激光烧蚀的重构半导体器件阵列的分离；
图20E示出根据一种实施方式的单独封装的重构半导体器件；
图20F示出根据一种实施方式的单独封装的重构半导体器件的保护密封涂层的特写示图；
图21示出根据一种实施方式的具有粘附至粘性载体的焊球的重构半导体器件的模制工序；
图22A至图22B示出根据一种实施方式的晶圆或者重构的半导体器件的塑封模套与柔性焊盘铸模成型过程；并且
图23是根据一种实施方式的用于制造半导体封装的方法的流程图。
具体实施方式
IC可以以晶圆级形式制造，其中，10个、100个、或者1000个IC形成在单个半导体晶圆内。晶圆材料可以是硅、砷化镓、或者其他半导体材料。现在参考附图，其中，贯穿几个视图，相同参考标号指代相同的或者对应的部分，图1A示出包含多个IC 110的晶圆100。IC110在形状上可以是正方形或者矩形，以及适于具体制造过程的其他形状。
图1B示出IC 110的截面区域。IC 110具有非活性表面120和活性表面130。活性表面130具有多个导电接触区域或者接触焊盘140，该多个导电接触区域或者接触焊盘140设计成能使IC 110与其他装置或者基板互连。IC接触焊盘140可以具有多层，称为凸点下金属喷镀(UBM，under-bump metallization)。基导电层可以包含铝。因为焊料没有很好地粘附至铝，所以另一个金属层或者导电层可以在铝垫片上图案化。示例UBM包括铝、镍钒、及铜的组合。然而，本文中描述的实施方式考虑几个其他UBM材料。本文中之后所指的接触焊盘可以包括UBM层。
接触焊盘140可以布置成各种配置，取决于其将连接至另一个装置或者基板的介质。图2A示出IC 110的顶视图，顶视图示出主要布置在IC 110的活性表面130的中心的多个接触焊盘140。该配置可以用于倒装芯片类型的装置，其中，装置可以具有连接至接触焊盘140的焊料凸块或者铜柱。倒装芯片装置和连接的焊料凸块被“翻转”并连接至另一个装置或者基板的接触焊盘。图2B示出IC 110的顶视图，顶视图示出主要围绕IC 110的活性表面130的周边布置的多个接触焊盘140。该配置可以用于焊线接合类型的装置。例如，焊线接合装置作为堆叠的装置或者并排的焊线接合装置粘接。接合线将焊线接合装置的接触焊盘140连接至另一个装置或者基板的接触焊盘。
图3A是晶圆级球栅阵列(WLBGA)310的截面图，包含晶圆315和多个半导体单元320。WLBGA 310也可以称为晶圆级芯片尺寸封装(WLCSP)，封装的尺寸与芯片的尺寸相同或者仅稍微大于芯片的尺寸。每个半导体单元320包含IC和晶圆315的活性表面335上的多个焊球330。图3A是简化的示图，其中，仅示出四个半导体单元320。足尺的晶圆315可以在截面图中具有更多的半导体单元320，诸如在图1A中的晶圆100。
图3B是晶圆级柱栅阵列340的截面图，包含晶圆345和多个半导体单元350。支柱360位于晶圆345的活性表面365上。支柱360是导电支柱，包含例如，具有焊料表面涂层的铜芯。
图3C示出具有焊料盖360的铜柱的外部连接。图3D示出线370外部连接。
图4A是WLBGA 400的截面图，包含晶圆410和多个半导体单元420。焊球430粘接至球栅阵列(BGA)中的晶圆410的活性表面435。其他配置包括，但不限于，细间距球栅阵列(FBGA)、针栅阵列(PGA)、柱栅阵列(CGA)、脊栅阵列(LGA)、Z互连阵列、以及其他。载带440粘附至晶圆410背面的非活性表面以在整个制造过程中使半导体单元420保持在适当的空间布局中。图4A还示出每个半导体单元420之间的凹槽或者切口450。在实施方式中，激光束在每个半导体单元420之间的划片街区穿行。第一切口450穿透活性表面435以去除划片街区内的介电材料与金属喷镀。激光束还部分地切割穿过晶圆410。在其他实施方式中，等离子腐蚀或者机械锯切可以用于第一切口450。
图4B是WLBGA 400的截面图，其中，图4A的载带440已经去除。诸如载带440的粘带可以通过机械去胶带或者施加紫外线光至载带440以使胶带的粘性无效。胶带460已经粘附至焊球430的底表面。胶带460的上表面具有厚的粘合层，其中，该粘合层围绕每个焊球430。当在随后步骤中施加真空时，粘合材料向上流动以部分地围绕每个焊球430，使得在每个焊球430的底表面上的胶带460中形成凹槽。然而，非粘带也可以用于胶带460。在其后的步骤，保护材料470填充在形成在晶圆410的活性表面435与胶带460的顶表面之间的间隙内以包围焊球430的暴露部分。保护材料470还填充通过第一切口450形成的划片街区凹槽。施加真空以提高保护材料470的毛细流动以到达并填充晶圆410与胶带460之间的所有的开放空间并且填充通过第一切口450形成的凹槽内。
保护材料470在划片街区凹槽内并且沿着活性表面435提供保护密封涂层。保护材料470由热固胶粘剂、使用膜辅助铸模成型的塑封料、或者环氧树脂制成。本文中描述的实施方式也考虑沿着半导体裸片的表面提供密封和保护涂层的其他材料。
在一种实施方式中，焊料凸块430在高度上约200微米。胶带460的粘合材料围绕焊球430约100微米的高度。这留下约100微米的差距，其中，保护材料470存在于活性表面435与胶带460之间。本文中描述的实施方式考虑其他大小的保护材料470，并且将基于半导体器件的类型、材料、及大小不同。
图4C示出晶圆级形式的一些IC的顶视图。图4C仅示出晶圆的部分示图，因为在晶圆上可能存在更多的IC。IC区域475位于结构的中心，被密封圈480包围。密封圈480被用于保护IC。在实施方式中，密封圈480可以由两个金属围栏制成，其中，每个金属层上的金属平面具有在金属平面之间的金属通孔。作为一个例子，两个金属围栏的宽度可以是几微米，诸如2至5微米的宽度并且在金属围栏中间分开几微米。划线街区485存在于每个IC区域475与它的密封圈480之间。
本文中描述的用于保护性边缘密封剂的实施方式提供减小或者完全去除密封圈，如在图4D中示出的。这在IC之间提供更大的区域。因此，IC可以一起更接近以利用更多的晶圆空间并且产生每个晶圆的更多数量的总裸片。
在图5A中，已经去除图4B的胶带460，并且晶圆510在半导体单元530之间的第二切口520中分离。划片切割穿过半导体单元530之间的保护材料535，并且还切割穿过其余的晶圆510以使半导体单元530远离彼此完全分离。因为保护材料535存在于活性表面上以及凹槽内，所以晶圆划片在执行第二切口520时破坏介电层或者金属喷镀层。产生的分离封装540具有在裸片的所有四个侧边缘并部分向上形成并且在围绕每个焊球的活性表面上的保护材料。图5B是分离的封装540的底部三维示图。
图6是另一实施方式的截面图600，示出具有活性表面620的晶圆610、和连接至活性表面620的焊球630。晶圆610的非活性表面粘附至载带640以保持分离后的半导体单元650的空间布局。制成第一切口660，在第一切口660中，晶圆610被部分地切割，诸如在图4A中示出的。例如，第一切口660可以通过激光刻槽制成。第一切口的示例是宽度为50微米至70微米。然而，本文中描述的实施方式考虑其他大小以适应半导体单元650的不同类型、材料、及尺寸。第二切口在划片街区槽内制成以完全切穿晶圆610。第二切口延伸到载带640中，但是没有完全切穿载带640。第二切口可以通过机械锯切制成。替代地，代替两个单独的切口，可以通过等离子腐蚀或者机械锯切制成单个切口。
载带640保持半导体单元650的空间布局，并且粘附至晶圆边缘(未示出)以提供刚性框架。另一实施方式包括使载带640延伸，即，拉长载带640，这可以通过对晶圆边缘内的载带640的背面按压执行。这提供半导体单元650之间的更大的间隙(是宽度的两倍)，即，100微米至140微米，如在图6的底部附图中示出的。这使得提供更大的间隙而无需实际上锯切那样大的切口。在该示例中，制成50微米至70微米的切口，但实现100微米至140微米的宽度。
图7是示出缺少图6的载带640的截面图。另一个胶带720粘附至半导体单元710的焊球的底表面。附贴至胶带720的半导体单元710可以是与图6相同的半导体单元和相同的布局，或者半导体单元710可以是粘附至胶带720用于进一步处理的几个选择单元。胶带720可以是围绕焊球的粘带或者非粘带。保护涂层730从半导体单元710的上位置填充到划片街区槽中，并且在半导体单元710与胶带720之间的活性表面上。替代地，保护涂层730在上表面仍粘附至图6中示出的载带640的同时从半导体单元710的下表面填充。
在图8A中，在每个相邻的裸片之间切割保护涂层，但是没有切穿半导体单元的任何有源电路。分离的半导体单元800除了具有活性表面上围绕焊球的保护涂层，还具有在所有的四个侧边缘的整个表面上的保护涂层。图8B是分离的半导体单元800的底部三维示图。
图9是在与上述实施方式类似的处理之后的粘附至四个半导体单元920的粘带910的截面图。胶带910也可以是胶带围绕焊球的非粘带。保护材料930填充在半导体单元920之间及顶部上。保护材料930也填充在每个半导体单元920与粘带910之间的间隙。
图10A是示出四个半导体单元的分离的截面图。充满保护材料的划片街区被切割，但是半导体单元的有源电路未被切割。除了焊球的下表面，最终封装的半导体单元1000完全被保护材料包围。图10B是封装的半导体单元1000的底部与顶部三维示图。
参考图3A至图10描述的实施方式针对倒装芯片类型的装置，在该装置中，焊球、支柱、或者圆柱连接至半导体单元的有源表面。图11A是示出在IC 1110的有源表面上具有焊料凸块1130的IC 1110的框图。IC 1110“翻转”使得有源表面在下边缘上。这允许焊料凸块1130直接连接至另一个装置或者基板，诸如基板1120。虽然未示出，基板1120在其上表面上具有与IC 1110上的焊料凸块1130的图案匹配的接触焊盘。焊料凸块1130被带入与基板1120的接触焊盘接触并上升至焊料凸块1130开始回流或者液化的温度。当温度降低时，回流的焊料凸块1130凝固，并且变得电并机械地连接至基板1120上的接触焊盘。
以上参考图3A至图5描述的实施方式在形成并且填充划片街区之前并在半导体单元的分离之前处理为在过程早期使焊球连接至有源电路层。替代地，可以首先执行划片街区的形成与填充，并且焊球或者其他导电性结构可以在处理的末尾连接至半导体单元。
现在将参考回到图3A至图5描述替代实施方式。在该替代实施方式中，图3A至图3B的晶圆315与晶圆345不具有此时连接至晶圆的焊球330或者导体支柱360。在图4A中，载带440粘附至晶圆410的后表面，并且在晶圆410的活性表面中的划片街区中制成第一切口450。在该替代实施方式中未使用图4B中的胶带460。替代地，保护涂层470填充在划片街区450内，并且还完全覆盖晶圆410的活性表面。焊接掩模或者焊料模板在使半导体单元分离之前施加在覆盖有源电路层的保护涂层上。焊接掩模可以由在暴露于紫外线(UV)光时可以图案化的聚合物或者感光成像材料制成。包含与半导体单元的活性表面上的接触焊盘匹配的多个开口的焊接掩模放置在晶圆上的保护涂层上。紫外线光穿过焊接掩模中的开口暴露保护涂层。随后去除焊接掩模，并且去除保护涂层的暴露区域。焊球放置在接触焊盘上的保护涂层的开口内，在图5中示出的分离之前或分离之后。焊球回流连接至半导体单元的接触焊盘。
图11B是示出另一种类型的装置，称为焊线接合装置的方框图。IC1110相对于胶粘剂连接的基板1120直立放置。上活性表面包含接合焊盘1135，接合焊盘1135通过接合线1150连接至基板1120的接合焊盘1145。图11B仅示出焊线接合装置的一种实施方式。本文中描述的实施方式考虑用于焊线接合至其他装置和/或其他类型的基板的几个其他配置。
现在将描述用于随后期望焊线接合的IC的实施方式。图12A示出半导体晶圆1210，半导体晶圆1210包含有源电路层1220。如在图12B中示出的，为了准备用于晶圆切割的晶圆，载带1230附贴至晶圆1210的非活性表面。晶圆切口或者凹槽1240通过晶圆1210的划片街区形成。晶圆切口或者凹槽1240可以通过激光刻槽、等离子腐蚀、或者机械锯切形成。在一种实施方式中，晶圆切口或者凹槽1240从划片街区去除任何钝化层、金属喷镀层、及层间介电材料，并且部分地切穿硅基板。
图13A示出掩模带1310施加至晶圆1330的活性表面1320，以为填充划片街区1340作准备。载带1350仍粘附至晶圆1330的非活性表面。图13B示出直接在划片街区1340上的掩模带1310内的开口1360的形成。开口1360可以通过激光图案化形成，诸如激光直写或者蚀刻。开口1360可以部分暴露划片街区1340，如在图13B中示出的，或者开口1360可以完全暴露划片街区1340。
图13C示出利用保护密封剂填充材料1370填充划片街区1340。保护密封剂填充材料1370包括，但不限于塑封料、热固性环氧树脂、树脂、或者胶粘剂。填充过程包括，但不限于铸模成型、真空铸模成型、沉浸涂层、喷涂、及旋转涂层。
图14A示出图13C的掩模带1310已经去除并且半导体单元1410分离以形成单独的封装的半导体单元1420。在一种实施方式中，晶圆划片穿透保护材料1430并且切割通过剩余的晶圆1440。晶圆分离的其他方法包括，但不限于蚀刻切割、激光烧蚀、隐形切片、及等离子体切片。封装的半导体单元1420包含完全围绕封装的半导体单元1420的下外围的保护材料1430，使得有源电路层1450的所有的边缘被保护材料1430保护。图14B是封装的半导体单元1420的底部三维示图。
图15示出用于期望随后的焊线接合的IC的晶圆级处理的另一种实施方式。包含多个IC的晶圆1510具有有源电路层1520。载带1530粘附至晶圆1510的非活性表面。在晶圆1510与有源电路层1520内的划片街区中制成多个第一切口或者凹槽1540。例如，晶圆切口或者晶圆凹槽1540可以通过激光刻槽、等离子腐蚀、或者机械锯切形成。在一种实施方式中，晶圆切口或者晶圆凹槽1540从划片街区去除任何钝化层、金属喷镀层、及层间介电材料，并且部分地通过硅基板切割。第二切口或者第二凹槽1550完全通过晶圆1510制成并且部分地到载带1530中。在实施方式中，第二切口或者第二凹槽1550通过晶圆锯切制成。图15示出第一切口或者第一凹槽1540在宽度上比第二切口或者第二凹槽1550大。在一种实施方式中，较大的第一凹槽1540通过激光刻槽或者等离子腐蚀形成，而第二凹槽1550通过晶圆锯切形成。大部分的载带1530仍然具有粘性，因此，继续将分离的半导体单元相对于彼此保持在原位。
在另一种实施方式中，代替上述的第二切口或者第二凹槽，晶圆的背表面可以后磨削至第一凹槽的顶部。粘性载体或者使晶圆稳定的其他手段可用于在后磨削过程中将晶圆保持在原位。该方法在较小的最后裸片方面占优势。
图16示出粘附至晶圆1630的有源电路层1620的掩模带1610。图17A示出图15的载带1530已经去除。保护密封材料1710从晶圆1720的背面填充在划片街区中。掩模带1730为保护密封材料1710提供备用。图17B示出另一种实施方式，其中，保护密封材料1710施加至晶圆的后非活性表面，以及划片街区内。保护密封材料1710包括，但不限于塑封料、热固性环氧树脂、树脂、或者胶粘剂。保护密封材料1710可以通过铸模成型、真空辅助铸模成型、浸没施加、喷涂层、及旋转涂层施加。本文中描述的实施方式考虑其他施加方法。
图18A是图17A的实施方式的截面图，其中，利用保护密封材料填充划片街区。半导体单元在划片街区内的保护密封材料之间分离1810，其中，在分离1810过程中电路未被切割。最后封装的半导体单元1820示出保护密封材料1830完全围绕IC1840的外围以覆盖IC的侧边缘与有源电路层1850的边缘。图18B是封装的半导体单元1820的底部三维示图。
图18C是图17B的实施方式的截面图，其中，利用保护密封材料填充划片街区并覆盖晶圆的后非活性表面。半导体单元在划片街区内的保护密封材料之间分离1810，其中，在分离1810过程中电路未被切割。最后封装的半导体单元1820示出保护密封材料1830完全围绕外围与IC1840的后非活性表面。除了有源电路层1850的底表面，最后封装的半导体单元1820完全被保护密封材料1830覆盖。图18D是封装的半导体单元1820的底部与顶部三维示图。
现在将参考回到图12A至图14描述替代实施方式。图12A的晶圆1210包含有源电路层1220。图12B示出晶圆1210的背面上的载带1230。第一切口或者第一凹槽1240通过有源电路层1240制成并且部分地通过半导体单元之间的硅晶圆。在图13A中示出的掩模带1310未施加至该替代实施方式。替代地，图13C的保护密封填充材料1370填充在第一切口或者第一凹槽1240内，并且还覆盖有源电路层1320。这在整个晶圆1330的活性表面上产生保护密封填充材料1370的连续层。
包含与半导体晶圆的活性表面上的接触焊盘匹配的多个开口的焊接掩模放置在晶圆上的保护密封填充材料1370上。焊接掩模可以由聚合物或者感光成像材料制成，聚合物或者感光成像材料在暴露于紫外线(UV)光时可以图案化。紫外线光通过焊接掩模中的开口暴露保护密封填充材料1370。随后去除焊接掩模，并且去除保护密封填充材料1370的暴露区域。接合线可以连接至保护密封填充材料1370的开口内有源电路层上的接触焊盘。
参考图19，将描述制造半导体封装的方法1900。在步骤S1910，载带粘附至半导体晶圆的非活性表面。在步骤S1920，在半导体晶圆的半导体单元之间切割或者蚀刻凹槽。凹槽切穿或者蚀刻穿过半导体晶圆的有源电路层。在一种实施方式中，凹槽利用切割与蚀刻步骤的组合形成。在步骤S1930，保护密封涂层材料施加到半导体单元之间的凹槽里。在一种实施方式中，施加步骤出现在连接外部导电连接器至半导体单元之前。在步骤S1940，半导体单元通过保护密封涂层材料分离。在一种实施方式中，方法1900还包括将膜粘附至半导体晶圆的外部导电连接器，并围绕外部导电连接器施加保护密封涂层材料。在另一种实施方式中，方法还包括穿过半导体单元之间的半导体晶圆完全切割或者蚀刻凹槽。在另一种实施方式中，方法还包括照射并去除通过掩模中的开口暴露的保护密封涂层材料，其中，开口与有源电路层的下面的接合焊盘对应。
本文中描述的方法与装置可以施加至晶圆级装置，如上所述，或者方法和装置可以施加至重构装置，如下所述。重构装置与晶圆形成分离并且经受多个测试。丢弃在一个或多个测试中失败的装置，重装通过测试的装置用于进一步制造。这仅提供继续处理好装置的优势，而不是完全通过处理携载不好的装置并在处理结束时丢弃它们。
图20A示出粘附至粘性载体2020的重构半导体器件2010的3×8阵列。图20A示出重构的半导体器件2010的矩形阵列。然而，本文中描述的实施方式考虑其他阵列，诸如装置板条、装置的四方阵列、或者装置的重构圆形晶圆阵列。图20A还示出在装置的活性表面上具有以球栅阵列(BGA)的多个焊球2030的重构半导体器件2010。然而，本文中描述的实施方式考虑其他外部互连，诸如引脚栅格阵列、圆柱栅格阵列、或者配置用于随后的焊线接合的多个接触焊盘。
图20B示出覆盖焊球2030与有源电路层，以及在重构半导体器件2010中间的保护涂层材料2040，诸如塑封料或者环氧树脂。图20C示出暴露焊球2030的下部分。在一种实施方式中，激光烧蚀被用于暴露焊球2030。近似焊球高度的一半通过塑封料暴露。然而，可以根据期望的最终产品使用其他暴露大小。在另一种实施方式中，膜放置在焊球2030的底表面上。塑封料2040填充在重构的半导体器件2010的膜与有源表面之间，并围绕单个焊球2030。
图20D示出将重构半导体器件2010分离为单个单元2050。单个单元2050的示例包括，但不限于球栅阵列(BGA)或者芯片级封装(CSP)。分离可以通过锯切、切割、或者蚀刻的一种或多种发生。分离仅通过塑封料发生，无需切割重构的半导体器件2010。如在图20E中示出的，单个单元2050从粘性载体2020去除。
图20F示出单个单元2050的截面示图。塑封料2040沿着单个单元2050的侧面保留并且继续围绕拐角表面且向内朝向单个单元2050的周边焊球2030。这提供密封有源电路层的边缘以防止分层的优势，还提供结构支撑至周边焊球2030。
侧壁塑封料的厚度可以依据最后的封装产品改变。在一种实施方式中，塑封料的侧壁厚度在从10μm至90μm的范围内。在一种实施方式中，模注半导体器件(在去除任何塑封料之前)从装置的背面至塑封料的顶表面可以近似560μm。通过激光烧蚀或者其他方法去除的塑封料的量可以是190μm。该量的塑封料去除暴露近似焊球的一半。上述大小仅出于示例性目的给出，本文中描述的实施方式考虑设计用于具体的最终产品的其他大小。
图21示出重构半导体器件的焊球粘附至粘性载体的一种实施方式。塑封料填充在重构半导体器件之间，以及每个装置的活性层与粘性载体之间的间隙。图21示出塑封料也驻留在重构半导体器件的后非活性表面上。另一种实施方式包括利用膜或者胶带覆盖后表面，因此后表面上没有施加塑封料。图21进一步示出粘性载体去除，并且重构半导体器件分离为单个单元。
在其他实施方式中，塑封料可以以暴露的裸片模套或者通过压缩模塑施加。图22A示出背表面粘附至载体的多个半导体器件。焊料凸块嵌入柔性焊盘，因此焊料凸块的上半部被覆盖并且焊料凸块的紧挨着裸片的下半部被暴露用于接收塑封料。在塑封料渗透开放空间并且设定之后，去除裸片模套与柔性焊盘。半导体器件被分离为单个单元。
图22B示出与图22A的过程类似的过程，除了在施加裸片模套与柔性焊盘之前施加塑封料接近多个装置的中心。图22A与图22B的过程可以施加至晶圆级半导体器件或者施加至重构半导体器件。
本文中描述的实施方式的多用性允许在几个可能的处理阶段进行测试。可以在以晶圆形式的划片街区封装之后，在以面板形式的裸片重构与铸模成型之后，在铸模成型的面板被分成板条形式，或者作为分离的IC单元的最后测试之后，使用裸片探测器进行测试。由于不同的供应商可以利用不同的测试平台，所以测试灵活度提供成本节约。
图23是制造半导体封装的方法2300的流程图。在步骤S2310，多个半导体器件以板条格式或阵列格式粘附至粘性载体。格式包含相邻的每对半导体器件之间的间隙。在步骤S2320，塑封料被施加至间隙。塑封料围绕所有暴露的有源电路边缘。在步骤S2330，多个半导体器件通过施加的塑封料分离。
方法2300还可以包括将外部焊球连接至有源电路层的相应的接触焊盘，并且在有源电路层上施加塑封料以包围连接的外部焊球。方法2300还可以包括在有源电路层与施加至外部焊球的底表面的膜之间的有源电路层上施加塑封料，激光烧蚀施加至外部焊球的底表面的塑封料，通过暴露的裸片模套或者压模之一将塑封料施加在间隙内并且在有源电路层上，或者在施加至多个半导体器件的背表面的塑封料上标记多个半导体器件的步骤的一个或多个。在一种实施方式中，多个半导体器件包括重构半导体器件。
半导体器件被处理多次并且经受几个处理及测试程序。传统的装置趋向于在接近有源电路层的边缘形成缺口(chipped-out)区域，尤其当装置受到撞击时。该缺口区域趋向于导致电路层与裸片的随后分层，引起装置的最终失败。
本文中描述的实施方式提供更坚固的半导体器件。保护边缘密封剂密封全部在裸片的所有四个侧面的周围的有源电路层的边缘。保护边缘密封剂在有源电路层上延伸以包围外部连接器，诸如焊球。这提供焊球支撑并且保护位于装置的外围的焊球的额外益处，增加装置的可靠性。作为减小分层与增加的可靠性的结果，半导体封装可以容纳更大的裸片。作为一个例子，仅出于示例性目的给出，传统的半导体封装可以具有近似5mm x5mm的裸片。较大尺寸的传统裸片存在在处理与测试的过程中出现缺口与分层的较高频率的风险。通过使用本文中描述的实施方式，可以使用8mm x 8mm或者10mm x 10mm的裸片尺寸并且仍然保持最小的分层与缺口，并具有增加的可靠性。使用本文中描述的实施方式的更大裸片也进行要求连接至基板以提供稳定性或者保护，引起成本节约。
本文中描述的方法与装置是示例性的并给出以示出某些实施方式的特征和过程。实施方式不局限于任何具体顺序或者本文中描述的示例性顺序。
本文中描述的用于半导体封装的实施方式可被用于许多施加，包括但不限于网络、移动、无线、可佩带的电子设备、及宽带。在网络施加中，本文中描述的半导体封装可被用于多核处理器、知识型处理器、服务器消息块(SMB)处理器、加密协同处理器、及安全处理器。在移动、无线施加、及可佩带施加中，本文中描述的半导体封装可被用于3G基带处理器、LTE基带处理器、移动视频处理器、移动图形处理器、施加处理器、触摸控制器、无线功率、物联网(IoT)及可佩带的系统芯片(SoC)、无线视频、及天线。在宽带施加中，本文中描述的半导体封装可被用于电缆机顶盒(STB)、卫星STB、网络协议(IP)STB、地面STB、超高清(HD)处理器、STB图形处理器、及STB安全处理器。这些装置和系统可被用于包括但不限于路由器、智能手机、平板电脑、个人计算机、及诸如手表、鞋子、衣服、及眼镜的可佩带设备的产品。在一些实施方式中，本文中描述的装置与系统可被用于WiFi组合芯片、施加处理器、功率管理芯片、及蓝牙芯片。
上述讨论仅公开并描述示例性实施方式。本领域的技术人员会理解的是，在不背离其精神或基本特性的情况下，本公开内容可体现为其他具体的形式。因此，本实施方式的本公开内容旨在进行说明，而非限制实施方式的范围以及权利要求。在此包括教导的可容易辨别的任何变体的公开内容部分限定上述权利要求书的术语的范围，从而任何主题都不公开使用。

Claims (9)

1.一种倒装半导体封装，包括：
晶圆，其包含有源电路层且包括多个半导体单元；
在所述有源电路层上的多个接合焊盘，所述多个接合焊盘被配置为连接至多个焊球中相应的焊球；以及
保护密封涂层，其至少填充所述晶圆的第一凹槽和第二凹槽，所述第一凹槽至少穿过所述有源电路层，所述第二凹槽与所述第一凹槽衔接且共同穿过所述晶圆，所述第一凹槽的宽度大于所述第二凹槽的宽度，其中，所述保护密封涂层包含外部晶圆分离表面，经由所述外部晶圆分离表面分离所述多个半导体单元；
其中所述多个焊球具有第一高度并被胶带的粘合材料围绕第二高度，所述第二高度小于所述第一高度，由此形成在所述有源电路层和所述胶带之间的间隙，所述保护密封涂层填充于所述间隙内并包围所述多个焊球的暴露部分。
2.根据权利要求1所述的倒装半导体封装，其中，所述外部晶圆分离表面包括锯切边缘、蚀刻边缘或者激光改变的边缘中的一个或多个。
3.根据权利要求1所述的倒装半导体封装，其中，所述保护密封涂层至少部分地覆盖所述半导体单元的裸片的周边。
4.根据权利要求1所述的倒装半导体封装，进一步包括：
附加保护密封涂层，在所述半导体单元的非活性表面上。
5.根据权利要求1所述的倒装半导体封装，其中，所述保护密封涂层减小或者去除围绕每个所述半导体单元的密封圈。
6.一种倒装半导体封装，包括：
晶圆，其具有有源电路表面和非活性表面且包括多个半导体单元；
多个焊球，其连接至所述有源电路表面；
第一凹槽，沿着所述有源电路表面的暴露边缘形成并部分地沿着所述半导体单元的裸片边缘延伸；
第二凹槽，其与所述第一凹槽衔接且共同穿过所述晶圆，所述第一凹槽的宽度大于所述第二凹槽的宽度；以及
保护密封涂层，填充在所述第一凹槽和所述第二凹槽内，其中所述保护密封涂层包含外部晶圆分离表面，经由所述外部晶圆分离表面分离所述多个半导体单元，
其中所述多个焊球具有第一高度并被胶带的粘合材料围绕第二高度，所述第二高度小于所述第一高度，由此形成在所述有源电路表面和所述胶带之间的间隙，所述保护密封涂层填充于所述间隙内并包围所述多个焊球的暴露部分。
7.一种制造倒装半导体封装的方法，包括：
将多个焊球安置于半导体晶圆的有源电路层上，其中所述半导体晶圆包括多个半导体单元；
在所述半导体晶圆的各半导体单元之间切割或者蚀刻第一凹槽和第二凹槽，其中，所述第一凹槽切割穿过或者蚀刻穿过所述半导体晶圆的所述有源电路层，所述第二凹槽与所述第一凹槽衔接且共同穿过所述半导体晶圆，所述第一凹槽的宽度大于所述第二凹槽的宽度；
将胶带粘附至所述多个焊球；以及
将保护密封涂层施加到所述半导体单元之间的所述第一凹槽和所述第二凹槽中，其中所述保护密封涂层包含外部晶圆分离表面，经由所述外部晶圆分离表面分离所述多个半导体单元；
其中所述多个焊球具有第一高度并被所述胶带的粘合材料围绕第二高度，所述第二高度小于所述第一高度，由此形成在所述有源电路层和所述胶带之间的间隙，所述保护密封涂层填充于所述间隙内并包围所述多个焊球的暴露部分。
8.根据权利要求7所述的方法，其进一步包括：
由所述多个半导体单元形成多个半导体器件；
将所述多个半导体器件以条格式或阵列格式粘附至粘性载体，其中，所述格式包含相邻的每对半导体器件之间的间隔；
在所述间隔内施加塑封料，其中，所述塑封料围绕暴露的有源电路边缘；并且
经由施加的所述塑封料分离所述多个半导体器件。
9.根据权利要求7所述的方法，其中所述第一凹槽和所述第二凹槽是通过切割和蚀刻步骤的组合而形成的。
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