CN101589464A - 晶片级csp封装设计 - Google Patents

晶片级csp封装设计 Download PDF

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CN101589464A
CN101589464A CNA2008800032151A CN200880003215A CN101589464A CN 101589464 A CN101589464 A CN 101589464A CN A2008800032151 A CNA2008800032151 A CN A2008800032151A CN 200880003215 A CN200880003215 A CN 200880003215A CN 101589464 A CN101589464 A CN 101589464A
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substrate
protective layer
top surface
wafer die
circuit
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阿兰·奥唐奈
奥利弗·基尔斯
托马斯·M·戈伊达
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Analog Devices Inc
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Abstract

本发明提供了一种电子封装，该电子封装包括晶片裸片衬底，该晶片裸片衬底包含电子电路并且具有顶表面和底表面。顶部保护层比衬底大体上薄并且覆盖顶表面。底部保护层比衬底大体上薄并且覆盖底表面。电路接触分布在底部保护层的各处，用于将衬底电子电路电耦合到外部电子电路。

Description

晶片级CSP封装设计
本申请要求于2007年1月25日提交的美国专利申请11/627,041的优先权，其内容通过引用结合于此。
技术领域
本发明涉及用于电子电路的封装，具体而言，涉及密封的晶片级芯片尺寸封装。
背景技术
对于发展新型电子产品的一个限制是所需电路的组装和封装。封装提供多重功能，包括用于保护被封入的电路裸片表面和用于提供裸片和印刷电路板之间的应力释放机构。另外，封装需要符合小尺寸、高密度和低成本的应用需求。
过去，在晶片被切片成电路裸片后，器件封装被组装为单个的单元。这种封装是被封入电路裸片的尺寸的几倍。最近，在切片之前以晶片级来密封电路裸片，以制造小得多的封装。当封装具有的面积不大于被封入裸片的1.2倍时，将其称作芯片尺寸封装(CSP)。晶片级CSP将晶片制造扩展为包括器件互连工艺和器件保护工艺，从而制造出的封装仅略大于被封入的裸片。
图1示出根据现有技术的典型WLCSP 10的底部立体正视图。晶片裸片11包含器件电路12，其通过可以存在于芯片表面上的透明聚合物保护涂层是可见的。WLCSP 10的底表面上的焊料球电接触13(也被称作“凸块”)的阵列将芯片内的器件电路12连接到诸如电路板的外部电路。
如上所述，WLCSP 10的透明聚合物涂层使下面的器件电路12可用眼观察进行检查，这是不期望发生的。例如，穿过透明聚合物涂层的光会对内部的器件电路12的操作产生不利影响。另外，焊料球电接触13相对易碎，并且在运输和操作期间会受到损坏。类似地，WLCSP10的未密封的背面也容易受碎屑的影响。
发明内容
本发明的实施例涉及一种电子封装，该电子封装具有晶片裸片衬底，该晶片裸片衬底包含电子电路并且具有顶表面和底表面。顶部保护层比晶片裸片衬底大体上薄并且覆盖顶表面。底部保护层比衬底大体上薄并且覆盖底表面。电路接触分布在底部保护层的各处，用于将衬底电子电路电耦合到外部电子电路。
在另外的实施例中，顶部保护层和/或底部保护层可以是不透明的。晶片裸片衬底还可以包括在顶表面和底表面之间的侧表面，并且顶部保护层和底部保护层中的至少一个可以在侧表面处更厚，使得衬底在侧表面处的暴露表面比衬底的剩余部分大体上薄。或者，在相关实施例中，可以在侧表面处没有暴露衬底的表面。
在一些实施例中，电路接触可以是基于嵌入到底部保护层中的导电凸块阵列。一些特定的实施例还可以包括在晶片裸片表面之一中的锁定部件，用于提高所述晶片表面和与其关联的保护层之间的粘附性。
本发明的实施例还包括一种制造电子电路封装的方法。在这种方法中，在具有顶表面和底表面的晶片裸片衬底中制造电子电路。用比衬底大体上薄的顶部保护层来覆盖顶表面，并且用比衬底大体上薄的底部保护层来覆盖底表面。在底部保护层各处分布电路接触，用于将衬底电子电路电耦合到外部电子电路。
在另外的这类实施例中，顶部保护层和/或底部保护层可以是不透明的。晶片裸片衬底还可以包括在顶表面和底表面之间的侧表面，并且覆盖顶表面和覆盖底表面中的至少一个可以在侧表面处产生更厚的保护层，使得衬底在侧表面处的暴露表面比衬底的剩余部分大体上薄。或者，在相关实施例中，可以不在侧表面处暴露衬底的表面。
在一些实施例中，形成多个电路接触的步骤可以包括：将导电凸块的阵列嵌入在底部保护层中。在一些特定实施例中，在晶片裸片衬底的顶表面和底表面中的至少一个中可以制造多个锁定部件，用于提高顶表面和底表面中的至少一个和与其关联的保护层之间的粘附性。
附图说明
图1示出根据现有技术的晶片级芯片尺寸封装的底部立体正视图。
图2示出根据本发明实施例的晶片级芯片尺寸封装的底部立体正视图。
图3是示出制造根据实施例的晶片级芯片尺寸封装的工艺中各种逻辑步骤的流程图。
图4A-B示出对裸片晶片上的电路应用电接触。
图5A-B示出部分锯切裸片晶片的过程。
图6A-B示出裸片晶片的密封。
图7A-B示出研磨底部密封层以暴露电路接触。
图8A-B示出将晶片分成单个裸片芯片。
图9A至图9D示出根据本发明的不同具体实施例的WLCSP的示例。
图10A至图10B示出对晶片背面和/或部分锯切的切口狭槽进行微蚀刻以使其具有密封锁定部件的实施例。
具体实施方式
本发明的实施例涉及用于完全或几乎完全密封晶片级芯片尺寸封装(CSP)的平坦表面的技术。这与目前至少一个平坦表面没有被密封的WLCSP大不相同。另外，尽管在现有技术中电路侧的平坦表面可以具有透明密封层，但是在本发明的实施例中，尤其在电路侧，密封层可以基本上是不透明的。
在一个特定实施例中，通过成型(molding)工艺来密封电路裸片的整个未经切割的晶片，该成型工艺包括密封与结合焊盘附着的金属互连。一旦被密封，成型后的晶片随后就被研磨或蚀刻以暴露互连，并且随后通过例如锯切将晶片分成单个WLCSP组件。
图2示出根据本发明的一个特定实施例的晶片级芯片尺寸封装(WLCSP)20的底部立体正视图。WLCSP 20包括晶片裸片衬底21，所述晶片裸片衬底21包含器件的电子电路。覆盖衬底21的底表面的是比衬底大体上薄的密封材料的底部保护层23。覆盖衬底21顶表面的是比衬底大体上薄的密封材料的类似顶部保护层24。电路接触22(例如，由焊料、金、铜等制成)分布在底部保护层23的各处(about)，用于将衬底的电子电路电耦合到外部电子电路。
图3是示出制造根据实施例的晶片级芯片尺寸封装(WLCSP)的工艺中的各种逻辑步骤的流程图。如图4中所示，一旦在晶片42上已经制造了电子电路，在步骤301中，以电路接触41阵列形式施加器件互连，将所述电路接触41阵列附着到电路内的结合焊盘。电路接触41可以是用于物理连接的具有足够强度的导电材料，包括但不限于焊料、金、银、铜等，并且电路接触41可以具有诸如球形、圆柱形等的各种特定形式，并且可以通过诸如焊料印刷、镀敷、引线结合等公知技术中的任意一种来连接。
在一些特定实施例中，如图5中所示，下一步骤302是用于部分锯切裸片晶片42，以在晶片材料42中产生切口狭槽51，切口狭槽51初步地分离单个裸片电路。在步骤302中，除了机械锯切之外，还可以使用其他特定工艺来进行部分锯切，这些其他特定工艺包括但不限于基于激光锯切、化学蚀刻等的方法。
如图6所示，在切口狭槽51的部分锯切之后，在步骤303中，密封材料61在晶片42的顶表面和底表面上方成型。密封剂可以是各种电绝缘材料中的任意一种，例如，诸如聚酰亚胺的不透明可成型的聚合物。在密封之后，切口狭槽51包含的密封材料61层比晶片材料42的每个器件的电子电路位于其中的剩余部分的密封材料层大体上厚。
在图6中所示的实施例中，密封材料61的底部保护层62完全覆盖电路接触41。在这种情况下，如图7所示，下一步骤304是例如通过研磨或蚀刻将底部保护层62减薄，以便暴露电路接触41的一部分来进行外部连接。在其他实施例中，密封材料61的底部保护层62最初没有完全覆盖电路接触41，而是使得电路接触的一部分暴露。在任一情况下，在步骤305中，在电路连接器41的暴露部分上方添加另一层电路连接器71是有用的。
然后，在步骤306中，将晶片分割成单个WLCSP。如从图8可以看到的，用于分割的切口比之前部分锯切步骤中使用的切口更窄。结果，在单个裸片82的侧边缘81处，密封材料61比整个的晶片衬底材料大体上厚。因而，在单个裸片82的侧边缘81仅暴露厚度减小的晶片材料。减少在器件侧边缘81处暴露的晶片材料的这一方面减小了光对内部电子电路的影响并且增大了单个裸片82的物理完整性。
图9A至图9D示出根据本发明的各种特定实施例的WLCSP的示例。图9A示出单个WLCSP，在该WLCSP中，部分锯切切口和较厚的密封材料层位于器件的有源(连接器)面。图9B示出单个WLCSP，在该WLCSP中，部分锯切切口和较厚的密封材料层位于器件的背(非连接器)面。图9C示出单个WLCSP，在该WLCSP中，晶片有源面和背面具有的部分锯切切口和较厚的密封材料层都位于器件的两个面上，以最小程度暴露晶片衬底。并且图9D示出单个WLCSP，在该WLCSP中，晶片的有源面和背面都具有基本汇合的部分锯切切口(使最初的晶片穿孔，例如，只在裸片角落处连接)，使得当在晶片上方成型密封材料时，单个裸片的侧边缘处的密封材料流动到一起从而汇合，使得在单个裸片的侧边缘处暴露非常少的晶片材料或者不暴露晶片材料。
在另外的具体实施例中，例如，可以使用各种附加的制造步骤，以提高密封材料与器件的粘附性。图10A至图10B示出对晶片背面进行微蚀刻以使其具有密封锁定部件1001的实施例的部件。锁定部件1001可以是一系列的凹槽、狭槽或其他表面部件，这些表面部件可以通过诸如微蚀刻、激光蚀刻、成型等各种手段在晶片背面上形成(develop)。如图10B中所示，部分锯切出的切口狭缝也可以或者可替选地具有类似的狭缝锁定部件1002。在这样的实施例中，当在部分锯切的晶片上方施加密封材料时，密封材料流入锁定部件1001和/或1002。一旦密封材料固化，通过密封材料与锁定部件1001和1002之间的交互作用，使得晶片材料和密封材料之间的物理连接增强。
虽然已经公开了本发明的各种示例性实施例，但是本领域的技术人员应该清楚的是，在不脱离本发明的真实保护范围的情况下，可以进行实现本发明的一些优点的各种变化和修改。

Claims (21)

1.一种电子封装，包括：
晶片裸片衬底，所述晶片裸片衬底包括电子电路并且具有顶表面和底表面；
顶部保护层，比所述衬底大体上薄，并且覆盖所述顶表面；
底部保护层，比所述衬底大体上薄，并且覆盖所述底表面；以及
多个电路接触，分布在所述底部保护层的各处，用于将所述衬底的电子电路电耦合到外部电子电路。
2.根据权利要求1所述的电子封装，其中，
所述顶部保护层是不透明的。
3.根据权利要求1所述的电子封装，其中，
所述底部保护层是不透明的。
4.根据权利要求1所述的电子封装，其中，
所述晶片裸片衬底还包括在所述顶表面和所述底表面之间的侧表面，以及
其中，所述顶部保护层和所述底部保护层中的至少一个在所述侧表面处更厚，使得所述衬底在所述侧表面处的暴露表面比所述衬底的剩余部分大体上薄。
5.根据权利要求1所述的电子封装，其中，
所述晶片裸片衬底还包括所述顶表面和所述底表面之间的侧表面，以及
其中，所述顶部保护层和所述底部保护层中的至少一个在所述侧表面处更厚，使得在所述侧表面处没有所述衬底的表面暴露。
6.根据权利要求1所述的电子封装，其中，
所述电路接触是基于嵌入在所述底部保护层中的导电凸块的阵列。
7.根据权利要求1所述的电子封装，还包括：
多个锁定部件，被制造在所述晶片裸片衬底的顶表面和底表面中的至少一个中，用于提高所述顶表面和所述底表面中的至少一个和与其关联的保护层之间的粘附性。
8.一种制造电子电路封装的方法，所述方法包括：
在具有顶表面和底表面的晶片裸片衬底中制造电子电路；
用比所述衬底大体上薄的顶部保护层来覆盖所述顶表面；
用比所述衬底大体上薄的底部保护层来覆盖所述底表面；以及
形成多个电路接触，所述多个电路接触分布在所述底部保护层的各处，用于将所述衬底电子电路电耦合到外部电子电路。
9.根据权利要求8所述的方法，其中，
所述顶部保护层是不透明的。
10.根据权利要求8所述的方法，其中，
所述底部保护层是不透明的。
11.根据权利要求8所述的方法，其中，
所述晶片裸片衬底还包括在所述顶表面和所述底表面之间的侧表面，以及
其中，覆盖所述顶表面和覆盖所述底表面中的至少一个在所述侧表面处产生更厚的保护层，使得所述衬底在所述侧表面的暴露表面比所述衬底的剩余部分大体上薄。
12.根据权利要求8所述的方法，其中，
所述晶片裸片衬底还包括在所述顶表面和所述底表面之间的侧表面，以及
其中，覆盖所述顶表面和覆盖所述底表面中的至少一个在所述侧表面处产生更厚的保护层，使得在所述侧表面处没有所述衬底的表面暴露。
13.根据权利要求8所述的方法，其中，
所述形成多个电路接触的步骤包括：在所述底部保护层中嵌入导电凸块的阵列。
14.根据权利要求8所述的方法，其中，
在晶片裸片衬底中制造电子电路的步骤包括：在所述晶片裸片衬底的顶表面和底表面中的至少一个中制造多个锁定部件，用于提高所述顶表面和所述底表面中的至少一个和与其关联的保护层之间的粘附性。
15.一种电子封装，包括：
晶片裸片衬底，包括电子电路并且具有顶表面和底表面；
顶部保护装置，比所述衬底大体上薄，并且覆盖所述顶表面；
底部保护装置，比所述衬底大体上薄，并且覆盖所述底表面；以及
多个电路接触装置，分布在所述底部保护层的各处，用于将所述衬底电子电路电耦合到外部电子电路。
16.根据权利要求15所述的电子封装，其中，
所述顶部保护装置是不透明的。
17.根据权利要求15所述的电子封装，其中，
所述底部保护装置是不透明的。
18.根据权利要求15所述的电子封装，其中，
所述晶片裸片衬底还包括在所述顶表面和所述底表面之间的侧表面，以及
其中，所述顶部保护装置和所述底部保护装置中的至少一个在所述侧表面处更厚，使得所述衬底在所述侧表面处的暴露表面比所述衬底的剩余部分大体上薄。
19.根据权利要求15所述的电子封装，其中，
所述晶片裸片衬底还包括在所述顶表面和所述底表面之间的侧表面，以及
其中，所述顶部保护装置和所述底部保护装置中的至少一个在所述侧表面处更厚，使得在所述侧表面处没有所述衬底的表面暴露。
20.根据权利要求15所述的电子封装，其中，
所述多个电路接触装置包括在所述底部保护装置中的导电凸块的阵列。
21.根据权利要求15所述的电子封装，其中，
所述晶片裸片衬底还包括在所述晶片裸片衬底的顶表面和底表面中的至少一个中的锁定部件装置，用于提高所述顶表面和所述底表面中的至少一个和与其关联的保护装置之间的粘附性。
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