JP7075791B2 - 半導体パッケージの製造方法 - Google Patents
半導体パッケージの製造方法 Download PDFInfo
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- JP7075791B2 JP7075791B2 JP2018052128A JP2018052128A JP7075791B2 JP 7075791 B2 JP7075791 B2 JP 7075791B2 JP 2018052128 A JP2018052128 A JP 2018052128A JP 2018052128 A JP2018052128 A JP 2018052128A JP 7075791 B2 JP7075791 B2 JP 7075791B2
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- 239000004065 semiconductor Substances 0.000 title claims description 218
- 238000004519 manufacturing process Methods 0.000 title claims description 43
- 239000000758 substrate Substances 0.000 claims description 94
- 238000007789 sealing Methods 0.000 claims description 86
- 238000000034 method Methods 0.000 claims description 37
- 239000003795 chemical substances by application Substances 0.000 claims description 19
- 239000008393 encapsulating agent Substances 0.000 claims description 18
- 239000000565 sealant Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 13
- 238000005520 cutting process Methods 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 109
- 229920005989 resin Polymers 0.000 description 57
- 239000011347 resin Substances 0.000 description 57
- 230000017525 heat dissipation Effects 0.000 description 25
- 238000010586 diagram Methods 0.000 description 15
- 238000005538 encapsulation Methods 0.000 description 11
- 238000012545 processing Methods 0.000 description 10
- 238000002347 injection Methods 0.000 description 9
- 239000007924 injection Substances 0.000 description 9
- 239000006061 abrasive grain Substances 0.000 description 7
- 229910003460 diamond Inorganic materials 0.000 description 6
- 239000010432 diamond Substances 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- 238000009832 plasma treatment Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 4
- 229920002803 thermoplastic polyurethane Polymers 0.000 description 4
- 208000032365 Electromagnetic interference Diseases 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000002679 ablation Methods 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000001747 exhibiting effect Effects 0.000 description 2
- 238000007733 ion plating Methods 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000010295 mobile communication Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 229920006337 unsaturated polyester resin Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010330 laser marking Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 230000005389 magnetism Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 1
- -1 polyethylene naphthalate Polymers 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Grinding Of Cylindrical And Plane Surfaces (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Dicing (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Control And Other Processes For Unpacking Of Materials (AREA)
Description
(1)
step coverage=(t2/t1)×100
11 :配線基板(配線基材)
12 :半導体チップ
13 :樹脂層
15 :封止基板
22、109 :樹脂層上面(封止剤表面)
34 :封止剤
36 :保持テープ
41、51、81:総型砥石
42、54、86:加工面
53、83 :突起
61 :金型
62 :天井面
Claims (3)
- 封止剤により封止された半導体パッケージを作成する半導体パッケージの製造方法であって、
交差する分割予定ラインによって区画された配線基材表面上に複数の半導体チップをボンディングし該配線基材の表面側に該封止剤を供給して封止された封止基板の該配線基材裏面側を保持治具又は保持テープで保持する保持ステップと、
該保持ステップを実施した後に、凹凸形状の加工面を有する総型砥石で該半導体チップに到達しない深さで該封止剤に切り込み、該封止剤表面に四角錐形状の多数の凹凸を形成して表面積を増加させる凹凸形成ステップと、
該分割予定ラインに沿って個々の半導体パッケージに個片化する個片化ステップと、
個片化後の該半導体パッケージの外面に導電性材料でシールド層を形成するシールド層形成ステップと、
を備える半導体パッケージの製造方法。 - 封止剤により封止された半導体パッケージを作成する半導体パッケージの製造方法であって、
交差する分割予定ラインによって区画された配線基材表面上に複数の半導体チップをボンディングし該配線基材の表面側に封止剤を供給して封止された封止基板を該封止基板の該配線基材裏面側を保持治具又は保持テープで保持する保持ステップと、
該保持ステップを実施した後に、総型砥石で該分割予定ラインに沿って該保持テープ途中まで又は該保持治具内まで切り込み、個々の半導体パッケージに個片化する個片化ステップと、
個片化後の該半導体パッケージの外面に導電性材料でシールド層を形成するシールド層形成ステップと、
を備え、
該総型砥石は、該分割予定ラインに対応して少なくとも2つの突起が形成され、該2つの突起間は凹凸形状の加工面を有し、
該個片化ステップにおいて、該突起を該分割予定ラインに沿って切り込み個々の半導体パッケージに個片化すると共に、個片化された半導体パッケージの該半導体チップに到達しない深さに該封止剤表面に四角錐形状の多数の凹凸を形成して表面積を増加させる半導体パッケージの製造方法。 - 該個片化ステップを実施した後に、個片化後の半導体パッケージの側面にIDマークを形成するIDマーク形成ステップを含む、
請求項1又は請求項2に記載の半導体パッケージの製造方法。
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CN201910186529.XA CN110310934B (zh) | 2018-03-20 | 2019-03-12 | 半导体封装的制造方法 |
US16/353,629 US10937668B2 (en) | 2018-03-20 | 2019-03-14 | Semiconductor package manufacturing method |
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