CN110310934B - 半导体封装的制造方法 - Google Patents
半导体封装的制造方法 Download PDFInfo
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- CN110310934B CN110310934B CN201910186529.XA CN201910186529A CN110310934B CN 110310934 B CN110310934 B CN 110310934B CN 201910186529 A CN201910186529 A CN 201910186529A CN 110310934 B CN110310934 B CN 110310934B
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Abstract
本发明提供半导体封装的制造方法,提高利用密封剂进行了密封的半导体封装的放热性。半导体封装的制造方法采用如下的构成:制作将接合在布线基板上的半导体芯片用树脂层进行了密封的密封基板,用保持带进行保持,用成型磨具切入树脂层而在树脂层上表面形成凹凸形状以使表面积增加,将密封基板沿着分割预定线单片化成各个半导体封装。
Description
技术领域
本发明涉及将半导体芯片用密封剂进行了密封的半导体封装的制造方法。
背景技术
作为半导体封装,制造出了将半导体芯片用密封剂进行了密封的半导体封装(例如,参见专利文献1)。在专利文献1所述的半导体封装的制造方法中,在布线基板上搭载多个半导体芯片,利用模制树脂等密封剂将多个半导体芯片统一密封,形成密封基板。之后将密封基板沿着分割预定线进行切割,由此将半导体芯片按照进行了封装的每1封装分别进行分割,制造出半导体封装。
现有技术文献
专利文献
专利文献1:日本特开2001-23936号公报
发明内容
发明所要解决的课题
另外,在半导体封装中,除了要求保护半导体芯片免受冲击或异物等外部环境的影响以外,还要求将半导体芯片中产生的热散逸到外部的放热性。但是,在仅用密封剂密封半导体芯片的构成中,放热性存在限制,要求进一步改善半导体封装的放热性。
本发明是鉴于这一点而完成的,其目的之一在于提供一种半导体封装的制造方法,其能够提高利用密封剂进行了密封的半导体封装的放热性。
用于解决课题的手段
本发明的一个方式的半导体封装的制造方法是制作利用密封剂进行了密封的半导体封装的方法,其中,该制造方法具备下述步骤:保持步骤,利用保持治具或保持带对密封基板的布线基材背面侧进行保持,该密封基板是在由交叉的分割预定线划分的布线基材表面上接合多个半导体芯片并对该布线基材的表面侧供给密封剂进行密封而成的;凹凸形成步骤,在实施了该保持步骤后,利用具有凹凸形状的加工面的成型磨具以未到达该半导体芯片的深度切入到该密封剂中,在该密封剂表面形成凹凸,使表面积增加;以及单片化步骤,沿着该分割预定线将该密封基板单片化成各个半导体封装。
根据该构成,通过利用成型磨具的凹凸形状的加工面以未到达半导体芯片的深度切入到密封剂中,能够在不损伤半导体芯片的情况下增加密封剂表面的表面积。因此,由半导体芯片产生的热传递至密封剂表面,利用密封剂表面的凹凸面有效地散热,提高半导体封装的放热性。
本发明的另一方式的半导体封装的制造方法是制作利用密封剂进行了密封的半导体封装的方法,其中,该制造方法具备下述步骤:
保持步骤,利用保持治具或保持带对密封基板的布线基材背面侧进行保持,该密封基板是在由交叉的分割预定线划分的布线基材表面上接合多个半导体芯片并对该布线基材的表面侧供给密封剂进行密封而成的;以及单片化步骤,在实施了该保持步骤后,用成型磨具沿着该分割预定线切入到该保持带的中途或该保持治具内,将该密封基板单片化成各个半导体封装,该成型磨具与该分割预定线对应地形成至少2个突起,该2个突起间具有凹凸形状的加工面,在单片化步骤中,使该突起沿着该分割预定线切入而单片化成各个半导体封装,并且以未到达进行了单片化的半导体封装的该半导体芯片的深度在该密封剂表面形成凹凸,使表面积增加。
根据该构成,在成型磨具形成有2个突起,因而利用2个突起沿着分割预定线切入密封基板而单片化成各个半导体封装。另外,通过利用成型磨具的凹凸形状的加工面以未到达半导体芯片的深度切入密封剂,能够在不会损伤进行了单片化的半导体芯片的情况下在密封剂表面形成凹凸,使表面积增加。因此,由半导体芯片产生的热传递至密封剂表面,利用密封剂表面的凹凸面有效地散热。如此,在对密封基板进行分割的同时在密封剂表面形成凹凸,因而能够降低作业工时、并且提高半导体封装的放热性。
本发明的另一方式的半导体封装的制造方法是制作利用密封剂进行了密封的半导体封装的方法,其中,该制造方法具备下述步骤:芯片接合步骤,在由交叉的分割预定线划分的布线基材表面上接合多个半导体芯片;密封基板制作步骤,将在顶面形成有凹凸形状的模具按照与该半导体芯片的表面之间形成空间的方式配置在布线基材表面侧,向该模具与该半导体芯片的表面之间的该空间内供给密封剂来进行密封,制作在该密封剂表面形成有凹凸形状的密封基板;以及单片化步骤,在实施了该密封基板制作步骤后,沿着该分割预定线对该布线基材进行分割,沿着该分割预定线单片化成各个半导体封装。
根据该构成,通过使用在顶面形成有凹凸形状的模具将半导体芯片用密封剂密封,可形成密封剂表面为凹凸面、表面积增加了的密封基板。因此,由半导体芯片产生的热传递至密封剂表面,利用密封剂表面的凹凸面有效地散热。另外,在不实施加工的情况下增加密封剂表面的表面积,因而在密封剂表面形成凹凸时不会增加操作者的负担。如此,通过使用模具形成凹凸,能够在不会增加作业工时的情况下提高半导体封装的放热性。
本发明的一个方式和其他方式的半导体封装的制造方法中可以包括ID标记形成步骤,在实施了该单片化步骤之后,在单片化后的半导体封装的侧面形成ID标记。
发明效果
根据本发明,通过使密封剂表面形成凹凸来增大表面积,由半导体芯片产生的热传递至密封剂表面,利用密封剂表面的凹凸面有效地散热,提高半导体封装的放热性。
附图说明
图1是本实施方式的半导体封装的截面示意图。
图2是通常的半导体封装的放热性的说明图。
图3的(A)是示出第1实施方式的芯片接合步骤的一例的图,图3的(B)是示出第1实施方式的密封基板制作步骤的一例的图,图3的(C)是示出第1实施方式的保持步骤的一例的图。
图4的(A)是示出第1实施方式的凹凸形成步骤的一例的图,图4的(B)是示出第1实施方式的单片化步骤的一例的图,图4的(C)是示出第1实施方式的ID标记形成步骤的一例的图。
图5是第2实施方式的半导体封装的制造方法的说明图。
图6的(A)是示出第3实施方式的密封基板制作步骤的一例的图,图6的(B)是示出第3实施方式中制作的密封基板的一例的图。
图7的(A)是示出第4实施方式的V槽形成步骤的一例的图,图7的(B)是示出第4实施方式的单片化步骤的一例的图,图7的(C)和图7的(D)是示出第4实施方式的屏蔽层形成步骤的一例的图。
图8是示出设置于试验体的屏蔽层的厚度的图。
图9是示出试验体的侧面的倾斜角与屏蔽层的厚度的关系的图。
图10是示出单片化步骤的变形例的图。
图11的(A)和图11的(B)是示出半导体封装的变形例的图。
图12的(A)、图12的(B)和图12的(C)是示出V槽形成步骤的变形例的图。
图13是示出单片化步骤的变形例的图。
图14是示出半导体封装的凹凸形状的变形例的图。
图15是示出V刀具的变形例的图。
具体实施方式
下面参照附图对本实施方式的半导体封装的制造方法进行说明。图1是本实施方式的半导体封装的截面示意图。图2是通常的半导体封装的放热性的说明图。需要说明的是,以下的实施方式只不过示出了一例,可以在各步骤间具备其他步骤,也可以适当地互换步骤的顺序。
如图1所示,半导体封装10是将半导体芯片12用树脂层(密封剂)13封装的半导体装置,其利用树脂层13保护半导体芯片12免受外部环境的影响。半导体封装10中,安装于布线基板(布线基材)11的表面的半导体芯片12被树脂层13密封,在布线基板11的背面配设有凸块14。在布线基板11上形成有与半导体芯片12连接的电极和包含接地线17在内的各种布线。在半导体封装10的侧面附有封装识别用的ID标记(未图示)。
通常在半导体封装中,有时会由于振动、冲击、水分、尘埃、磁等而引起半导体芯片12的工作不良,必须要适当地保护半导体芯片12免受这样的外部环境的影响。另外,在半导体芯片12工作时会放热,若芯片本身的温度升高,则不仅不能正常工作,而且还可能发生破损,需要将半导体芯片12维持在工作保障温度以下。如此,对于半导体封装10来说,除了保护半导体芯片12免受冲击、异物等外部环境的影响以外,还要求将半导体芯片12中产生的热散逸到外部的放热性。
另外,如图2的比较例所示,通常的半导体封装110中,布线基板111上的半导体芯片112利用树脂层113密封,半导体封装110的封装上表面114形成为平坦的面。在半导体封装110内的半导体芯片112放热时,热传递至树脂层113并由平坦的封装上表面114扩散。但是,在半导体芯片112的放热量增大时,则难以由封装上表面114使热充分扩散而适当地除去半导体芯片112的热。因此,需要进一步改善半导体封装110的放热性。
这种情况下,也考虑了通过使半导体芯片112上的树脂层113变薄来改善放热性的构成,但这样会降低半导体封装110的机械强度,可能无法保护半导体芯片112免受物理性损害等的影响。因此,如图1所示,在本实施方式中,将半导体封装10的封装上表面25制成凹凸状,使表面积增加。半导体芯片12的放热传递至封装上表面25,利用封装上表面25的凹凸有效地散热,提高半导体封装10的放热性。能够在抑制机械强度降低的同时提高放热性。
下面参照图3和图4对第1实施方式的半导体封装的制造方法进行说明。图3和图4是第1实施方式的半导体封装的制造方法的说明图。需要说明的是,图3的(A)是示出芯片接合步骤的一例的图,图3的(B)是示出密封基板制作步骤的一例的图,图3的(C)是示出保持步骤的一例的图。图4的(A)是示出凹凸形成步骤的一例的图,图4的(B)是示出单片化步骤的一例的图,图4的(C)是示出ID标记形成步骤的一例的图。
如图3的(A)所示,首先实施芯片接合步骤。在芯片接合步骤中,利用交叉的分割预定线将布线基板11的表面划分成格子状,在划分出的各器件区域将多个半导体芯片12接合至布线基板11的表面。这种情况下,引线19的一端与半导体芯片12的上表面的电极连接,引线19的另一端与布线基板11的表面的电极18连接。另外,在布线基板11内形成有接地线17等各种布线,在布线基板11的背面配设有将来自外部的信号等传递至半导体芯片12的凸块14。
如图3的(B)所示,在实施了芯片接合步骤之后实施密封基板制作步骤。在密封基板制作步骤中,对接合有多个半导体芯片12的布线基板11的上表面侧供给密封剂34,将各半导体芯片12利用密封剂34统一密封,制作出密封基板15(参见图3的(C))。这种情况下,将安装有半导体芯片12的布线基板11的背面保持在保持治具(未图示),按照覆盖布线基板11的上表面(表面)的方式配置模具31。在模具31的顶面开口有注入口32,将用于供给密封剂34的供给喷嘴33定位在注入口32的上方。
之后,从供给喷嘴33通过注入口32对布线基板11的上表面供给密封剂34,将半导体芯片12密封。在该状态下,通过对密封剂34进行加热或干燥而使其固化,制作出在布线基板11的上表面形成有树脂层13(参见图3的(C))的密封基板15。需要说明的是,密封剂34使用具有固化性的物质,可以从环氧树脂、有机硅树脂、聚氨酯树脂、不饱和聚酯树脂、丙烯酸聚氨酯树脂或聚酰亚胺树脂等中进行选择。另外,密封剂34并不限于液状,也可以使用片状、粉末状的树脂。需要说明的是,在预先准备了密封基板15的情况下,也可以省略芯片接合步骤、密封基板制作步骤。
如图3的(C)所示,在实施了密封基板制作步骤之后实施保持步骤。在保持步骤中,按照封住环状框架(未图示)的中央的方式粘贴保持带36,使密封基板15的布线基板背面侧保持于该保持带36。这种情况下,密封基板15的凸块14进入到保持带36的粘接层中,借助保持带36将密封基板15良好地支承于环状框架。需要说明的是,保持步骤可以利用安装座等专用装置机械地实施,也可以由操作者手工实施。另外,环状框架可以形成为俯视环状,也可以形成为俯视矩形框状。
如图4的(A)所示,在实施了保持步骤之后实施凹凸形成步骤。在凹凸形成步骤中,使用具有凹凸形状的加工面42的大致圆筒状的成型磨具41。成型磨具41的外周面形成为侧视观察下峰形状和谷形状沿轴向交替重复的凹凸形状,金刚石等磨粒电沉积在凹凸形状的外周面而形成加工面42。加工面42的峰形状的高度与谷形状的深度的差量形成为小于从芯片上表面21到树脂层上表面(密封剂表面)22的高度,即使切入到加工面42的谷形状,峰形状也不会到达半导体芯片12。
在密封基板15的布线基板11侧隔着保持带36保持于卡盘工作台(未图示)时,在密封基板15的外侧,成型磨具41下降到未到达半导体芯片12的深度。通过使密封基板15沿水平方向相对于成型磨具41进行加工进给,成型磨具41的加工面42的峰形状和谷形状被转印到树脂层上表面22。由此,在树脂层上表面22形成由峰形状和谷形状构成的凹凸形状,树脂层上表面22的表面积增加。另外,成型磨具41没有与半导体芯片12接触,因而在凹凸形成时也不会损伤半导体芯片12。
通过利用该成型磨具41反复进行切入动作,在树脂层上表面22的整个区域交替形成有多列的峰形状和谷形状。使卡盘工作台旋转90度,按照横穿峰形状和谷形状的方式利用成型磨具41反复进行同样的加工动作。由此,在密封基板15的树脂层上表面22形成有四棱锥形状的多个凹凸,与外部空气接触的树脂层13的表面积增加,放热性提高。需要说明的是,成型磨具41的切入量被调整为分割后的半导体封装10(参见图4的(B))可得到充分的放热性、并且可充分确保该半导体封装10的机械强度的深度。
如图4的(B)所示,在实施了凹凸形成步骤之后实施单片化步骤。在单片化步骤中,使用将金刚石磨粒等利用粘合剂固定为圆板状的直刀具44。密封基板15的布线基板11侧隔着保持带36保持于卡盘工作台(未图示),直刀具44与密封基板15的分割预定线对位。之后,在密封基板15的外侧,直刀具44下降到保持带36的厚度方向中途的深度,使密封基板15沿水平方向相对于直刀具44进行加工进给。
由此,利用直刀具44从树脂层13侧切入到保持带36的中途,对密封基板15进行全切割。在沿着一条分割预定线对密封基板15进行全切割时,直刀具44相对于相邻的分割预定线对位,对密封基板15进行全切割。通过对密封基板15反复进行该切断动作,将密封基板15沿着分割预定线单片化成各个半导体封装10。这样,在树脂层上表面22形成凹凸形状,制造出放热性得到了提高的半导体封装10。
如图4的(C)所示,在实施了单片化步骤之后实施ID标记形成步骤。在ID标记形成步骤中,在单片化后的半导体封装10的封装侧面26形成ID标记。这种情况下,以封装侧面26朝向上方的状态将半导体封装10定位在加工头46的下方,通过激光打标在封装侧面26形成ID标记。由此,即使在半导体封装10的封装上表面25形成凹凸形状,也能够在各个半导体封装10上形成ID标记。
如上所述,根据本实施方式的半导体封装10的制造方法,通过利用成型磨具41的凹凸形状的加工面42以未到达半导体芯片12的深度切入到树脂层13中,能够在不损伤半导体芯片12的情况下增加树脂层上表面22的表面积。由此,由半导体芯片12产生的热传递至树脂层上表面22,利用树脂层上表面22的凹凸面有效地散热,半导体封装10的放热性提高。
参照图5对第2实施方式的半导体封装的制造方法进行说明。第2实施方式中,与第1实施方式不同的点在于:利用单片化步骤在密封基板上形成凹凸形状、同时将密封基板单片化。因此,对于单片化步骤以外的各步骤省略说明。图5是第2实施方式的半导体封装的制造方法的说明图。
如图5所示,在实施了芯片接合步骤、密封基板制作步骤、保持步骤之后实施单片化步骤。在单片化步骤中,使用具有凹凸形状的加工面54和单片化用的一对突起53的成型磨具51。成型磨具51的基台52形成为圆筒状,一对突起53从基台52的外周面呈圆环状突出。一对突起53间形成为在侧视观察下峰形状和谷形状沿轴向交替重复的凹凸形状,除了一对突起53以外,还在一对突起53之间的凹凸形状上电沉积金刚石等磨粒而形成加工面54。加工面54的高度与谷形状的深度的差量形成为小于从半导体芯片12的芯片上表面21到树脂层上表面(密封剂表面)22的高度。
密封基板15的布线基板11侧隔着保持带36保持于卡盘工作台(未图示)时,在密封基板15的外侧,成型磨具51的一对突起53分别与分割预定线对位。即,一对突起53的间隔与分割预定线的间隔相对应。另外,在密封基板15的外侧,成型磨具51下降到能够利用一对突起53切入到保持带36的中途,凹凸形状的加工面54能够切入树脂层上表面22并且未到达半导体芯片12的深度。之后使密封基板15沿水平方向相对于成型磨具51进行加工进给,由此沿着分割预定线对密封基板15进行加工。
利用成型磨具51切入密封基板15来进行分割,并且使成型磨具51的凹凸形状转印至分割后的密封基板15的树脂层上表面22。使卡盘工作台旋转90度,利用成型磨具51实施同样的加工动作,由此将密封基板15分割成各个半导体封装10,并且在单片化后的半导体封装10的树脂层上表面22形成四棱锥形状的凹凸形状。利用凹凸形状,树脂层上表面22的表面积增加、放热性提高。另外,成型磨具51未与半导体芯片12接触,因而在凹凸形成时也不会损伤半导体芯片12。在单片化步骤后,利用ID标记形成步骤在单片化后的封装侧面26形成ID标记(参见图4的(C))。
如上所述,在本实施方式的半导体封装10的制造方法中,在成型磨具51上形成2个突起53,因而利用这2个突起53沿着分割预定线切入密封基板15而将其单片化成各个半导体封装10。通过利用成型磨具51的凹凸形状的加工面54以未到达半导体芯片12的深度切入树脂层13,在不会损伤半导体芯片12的情况下在树脂层上表面22形成凹凸,表面积增加。由此,由半导体芯片12产生的热传递至树脂层上表面22,利用树脂层上表面22的凹凸面有效地散热。如此,在对密封基板15进行分割的同时在树脂层上表面22形成凹凸,因而能够降低作业工时、并且提高半导体封装10的放热性。
参照图6对第3实施方式的半导体封装的制造方法进行说明。第3实施方式中,与第1实施方式不同的点在于:利用密封基板制作步骤由模具在密封基板的上表面形成凹凸形状。因此,对于密封基板制作步骤以外的各步骤省略说明。图6是第3实施方式的半导体封装的制造方法的说明图。
如图6的(A)所示,在实施了芯片接合步骤之后实施密封基板制作步骤。在密封基板制作步骤中,在接合有多个半导体芯片12的布线基板11的上表面侧,各半导体芯片12利用密封剂34统一密封,制作出密封基板15(参见图6的(B))。这种情况下,将安装有半导体芯片12的布线基板11的背面保持于保持治具(未图示),按照与半导体芯片12的芯片上表面21具有空间而覆盖布线基板11的方式载置模具61。即,模具61按照在半导体芯片12的芯片上表面21与模具61之间形成空间的方式配置在布线基材11的表面侧。在模具61的顶面62由四棱锥形状的多个凹部形成凹凸形状。
另外,在模具61的顶面62开口有注入口63,将密封剂34的供给喷嘴33定位在注入口63的上方。将注入口63定位在分割预定线的上方,因而在密封剂34固化后,注入口63的树脂柱65(参见图6的(B))不会形成在半导体芯片12的上方。另外,注入口63形成为直径小于后续阶段的单片化步骤所使用的直刀具44(参见图6的(B))的刀具宽度。之后,从供给喷嘴33通过注入口63将密封剂34供给至模具61的顶面62与半导体芯片12的上表面之间的空间内,对多个半导体芯片12进行密封。
如图6的(B)所示,在利用密封剂34对多个半导体芯片12进行密封时,通过对密封剂34进行加热或干燥而使其固化。将模具61从布线基板11拆下,由此制作出在布线基板11的上表面形成有树脂层13(参见图3的(C))的密封基板15。顶面62(参见图6的(A))的凹凸形状被转印至树脂层上表面22,在树脂层上表面22形成四棱锥形状的凹凸形状,树脂层上表面22的表面积增加,放热性提高。在分割预定线上形成树脂柱65,但在后续阶段的单片化步骤中,在利用直刀具44对密封基板15进行分割时,将树脂柱65除去。
需要说明的是,密封剂34使用具有固化性的物质,可以从环氧树脂、有机硅树脂、聚氨酯树脂、不饱和聚酯树脂、丙烯酸聚氨酯树脂或聚酰亚胺树脂等中进行选择。另外,密封剂34并不限于液状,也可以使用片状、粉末状的树脂。在密封基板制作步骤后,在保持步骤中利用保持带36对密封基板15的布线基板背面侧进行保持,在单片化步骤中将密封基板15单片化成各个半导体封装10。之后,在ID标记形成步骤中在单片化后的封装侧面26形成ID标记。
如上所述,根据本实施方式的半导体封装10的制造方法,通过使用在顶面62形成有凹凸形状的模具61将半导体芯片12利用密封剂34进行密封,树脂层上表面22形成凹凸面而形成表面积增加的密封基板15。由此,由半导体芯片12产生的热传递至树脂层上表面22,利用树脂层上表面22的凹凸面有效地散热。在不实施加工的情况下增加树脂层上表面22的表面积,因而在树脂层13形成凹凸时不会增加操作者的负担。如此,通过使用模具61形成凹凸,能够在不增加作业工时的情况下提高半导体封装10的放热性。
需要说明的是,上述第1至第3实施方式的半导体封装的制造方法还能够适用于需要防止所谓的EMI(Electro-Magnetic Interference,电磁干扰)的半导体封装的制造方法中。在第1至第3实施方式中,在单片化步骤前实施V槽形成步骤,在单片化步骤后实施屏蔽层形成步骤,由此能够在半导体封装的外表面形成EMI屏蔽,防止电磁噪声的泄漏。
下面参照图7对带有屏蔽层的半导体封装的制造方法进行说明。图7是第4实施方式的半导体封装的制造方法的说明图。此处对于在第1实施方式的半导体封装的制造方法中追加V槽形成步骤、屏蔽层形成步骤的一例进行说明。因此,对于V槽形成步骤、单片化步骤、屏蔽层形成步骤以外的各步骤省略说明。需要说明的是,图7的(A)是示出V槽形成步骤的一例的图,图7的(B)是示出单片化步骤的一例的图,图7的(C)和图7的(D)是示出屏蔽层形成步骤的一例的图。
如图7的(A)所示,在实施了芯片接合步骤、密封基板制作步骤、保持步骤、凹凸形成步骤之后实施V槽形成步骤。在V槽形成步骤中,使用V刀具66,该V刀具66利用结合剂将金刚石磨粒等固定成圆板状,前端(前端的截面)形成V字状。密封基板15的布线基板11侧隔着保持带36保持于卡盘工作台(未图示),V刀具66与密封基板15的分割预定线对位。在密封基板15的外侧,V刀具66下降到密封基板15的厚度方向中途的深度,使密封基板15沿水平方向相对于V刀具66进行加工进给。由此,沿着分割预定线对树脂层上表面22进行半切割,形成V槽68。
需要说明的是,在本实施方式中,V刀具66的前端形成为尖的V字形状,但并不限于该构成。V刀具66的前端只要是能够对密封基板15形成V槽68的形状即可。例如,如图15所示,V刀具99的前端也可以形成为平坦的V字形状。由此,切削刀具的前端为V字形状是指如下的形状:并不限于直至切削刀具的前端完全变尖的V字形状,也包括切削刀具的前端平坦的大致V字形状。另外,V刀具的前端的V字面不必直线状地倾斜,也可以稍微带有圆角。
如图7的(B)所示,在实施了V槽形成步骤之后实施单片化步骤。在单片化步骤中,密封基板15的布线基板11侧隔着保持带36保持于卡盘工作台(未图示),直刀具67与密封基板15的V槽68对位。在密封基板15的外侧,直刀具67下降到保持带36的厚度方向中途的深度,使密封基板15沿水平方向相对于直刀具67进行加工进给。由此,沿着分割预定线对密封基板15进行全切割,单片化成各个半导体封装10。
如图7的(C)所示,在实施了单片化步骤后实施屏蔽层形成步骤。在屏蔽层形成步骤中,在多个半导体封装10的封装外表面利用导电性材料形成屏蔽层69。这种情况下,各半导体封装10借助保持带36被搬入到等离子体装置(未图示)内,在规定的形成条件下从上方通过溅射等等离子体处理对各半导体封装10形成由导电性材料形成的屏蔽层16。由此,在各半导体封装10的封装上表面25和封装侧面26以所期望的厚度形成屏蔽层69。
此时,如图7的(D)所示,封装侧面26的倾斜面27从封装上表面25朝向下方向外侧扩展,倾斜面27相对于屏蔽层69的形成方向(铅直方向)倾斜地交叉。由此,在半导体封装10形成屏蔽层69时,不仅在封装上表面25而且在封装侧面26的倾斜面27也以可发挥出充分的屏蔽效果的厚度形成屏蔽层69。在封装上表面25形成凹凸形状,但凹凸形状以斜面形成,因而在凹凸形状的斜面也以适度的厚度形成屏蔽层69。
另外,在封装侧面26的铅直面28、封装之间的槽底29也形成了屏蔽层69,因而在从保持带36拾取半导体封装10时,在半导体封装10的下部可能会产生因屏蔽层69所致的飞边。这种情况下,除了屏蔽层69的成膜条件以外,还对封装之间的高宽比(纵横比)进行调整,由此能够抑制半导体封装10产生飞边。封装之间的高宽比通过直刀具67(参见图7的(B))的宽度尺寸和切入量进行调整。
关于封装之间的高宽比,在将从封装侧面26的倾斜面27的下端到切入保持带36的槽底29为止的深度设为Ymm、将封装侧面26的铅直面28的对置间隔设为Xmm时,该高宽比以Y/X来表示。封装侧面26的铅直面28的下侧或封装之间的槽底29容易受高宽比的影响,随着封装之间的高宽比提高,屏蔽层69形成得更薄。因此,通过提高高宽比,在不容易受到高宽比的影响的倾斜面27以适度的厚度形成屏蔽层69,在容易受到高宽比的影响的铅直面28的下侧或槽底29较薄地形成屏蔽层69,来抑制飞边的产生。
布线基板11的接地线17在封装侧面26的倾斜面27的下侧露出到外部。在倾斜面27的下侧接地线17与适度厚度的屏蔽层69连接,因此半导体封装10中产生的电磁噪声通过接地线17而散逸到半导体封装10之外。需要说明的是,在封装侧面26的铅直面28的下侧屏蔽层69变薄,但可通过布线基板11的多个布线(未图示)来切断电磁噪声。因此,整体上防止了电磁噪声向半导体封装10的周围的电子部件泄漏。
布线基板11的接地线17与屏蔽层69连接即可,也可以在封装侧面26的铅直面28与屏蔽层69连接。屏蔽层69是由铜、钛、镍、金等中的一种以上的导电性材料形成的厚度为几微米以上的金属层,可通过溅射法、离子镀法、等离子体CVD(chemical Vapor Deposition,化学气相沉积)法等的等离子体处理来形成。这样,制造出封装上表面25和封装侧面26被屏蔽层69覆盖的半导体封装10。
需要说明的是,在本实施方式中,作为保持带36,使用了由对于屏蔽层形成步骤的等离子体处理具有耐性的材料形成的保持带。对于等离子体处理的耐性表示包括耐等离子体性、耐热性、耐真空性的等离子体耐性。保持带36的带基材优选由耐热温度为150度至170度的材料形成,例如可以从聚萘二甲酸乙二醇酯树脂、聚酰亚胺树脂中选择。
接着对半导体封装的侧面的倾斜角度与屏蔽层的关系进行说明。图8是示出设置于试验体的屏蔽层的厚度的图。图9是示出试验体的侧面的倾斜角与屏蔽层的厚度的关系的图。
如图8所示,准备改变了侧面72的倾斜角度θ的多个试验体70,在180℃、8×10-4Pa的条件下通过离子镀法形成屏蔽层。侧面72的倾斜角度θ为90°、82°、68°、60°、45°中的任一种。另外,基于扫描型电子显微镜的观察图像对形成于上表面71的上部屏蔽层73的厚度t1以及形成于侧面72的侧部屏蔽层74的厚度t2进行测定。对于上部屏蔽层73和侧部屏蔽层74的厚度t1、t2,计算出下式(1)所示的阶梯包覆率(step coverage)的值,在图9中汇总了该值与倾斜角度θ的关系。
(1)阶梯包覆率(step coverage)=(t2/t1)×100
其结果,随着倾斜角度θ从90°起变小,阶梯包覆率的值缓慢变大,在倾斜角度θ为45°时,阶梯包覆率的值为100%。具体地说,在倾斜角度θ设定为45°的情况下,上部屏蔽层73的厚度t1与侧部屏蔽层74的厚度t2一致,在试验体70的上表面71和侧面72确认到了厚度均匀的屏蔽层。另外,根据发明人的实验,在阶梯包覆率的值低于50%时,侧部屏蔽层74的成膜需要时间,工艺成本会增大,因此优选阶梯包覆率的值为50%以上的范围。因此,半导体封装的侧面的倾斜角度θ优选为45°以上且为82°以下。
如以上所述,根据本实施方式的半导体封装10的制造方法,在提高半导体封装10的放热性的同时能够在封装外表面以规定的厚度形成可发挥出充分的屏蔽效果的屏蔽层69。
需要说明的是,在第1实施方式的半导体封装的制造方法中,对于在半导体封装上形成屏蔽层的一例进行了说明,但并不限于该构成。在第2、第3实施方式的半导体封装的制造方法中追加V槽形成步骤、屏蔽层形成步骤也能够在半导体封装上形成屏蔽层。另外,通过使用专用的成型磨具,可以同时实施凹凸形成步骤、V槽形成步骤、单片化步骤。
具体地说,如图10所示,一对突起83从成型磨具81的圆筒状的基台82的外周面呈圆环状突出。一对突起83的宽度分别从基端朝向突出方向变窄,从突出方向的中途到前端形成为一定宽度。即,突起83的侧面的基端侧形成倾斜面84,突起83的侧面的前端侧形成铅直面85。在一对突起83之间形成为在侧视观察下峰形状和谷形状沿轴向交互重复的凹凸形状。除了成型磨具81的突起83的两侧面和前端面以外,还在一对突起83之间电沉积金刚石等磨粒而形成加工面86。
在使用这样的专用成型磨具81实施单片化步骤时,利用成型磨具81切入密封基板15来进行分割,并且将成型磨具81的凹凸形状转印至分割后的密封基板15的树脂层上表面22。由此,将密封基板15单片化成各个半导体封装10,并且各半导体封装10的树脂层上表面22的表面积增加。由于突起83侧面的基端侧形成为倾斜面84,因而半导体封装10按照与上表面侧相比在下表面侧增大的方式使封装侧面26带有倾斜。如此,能够在使封装侧面26带有倾斜的同时将密封基板15单片化成各个半导体封装10,提高各半导体封装10的放热性。
需要说明的是,在本实施方式中,例示出了在布线基板上安装了1个半导体芯片的半导体封装,但并不限于该构成。也可以制造在布线基板上安装多个半导体芯片的半导体封装。例如,如图11的(A)所示,可以在布线基板93上安装多个(例如3个)半导体芯片92a-92c,制造半导体芯片92a-92c合在一起的半导体封装91。需要说明的是,半导体芯片92a-92c可以具有相同功能,也可以具有不同的功能。
另外,如图11的(B)所示,也可以在布线基板97上安装多个(例如2个)半导体芯片96a、96b,制造出对半导体芯片96a、96b单独进行屏蔽的半导体封装95。这种情况下,以芯片为单位在密封基板形成槽,以封装为单位对密封基板进行分割。需要说明的是,半导体芯片96a、96b可以具有相同的功能,也可以具有不同的功能。
另外,在本实施方式中,采用了在V槽形成步骤中使用V刀具作为V槽形成单元的构成,但并不限于该构成。例如,如图12的(A)所示,也可以使用通常的直刀具101作为V槽形成单元而在密封基板15上形成V槽。这种情况下,使直刀具101相对于密封基板15的分割预定线上的铅直面P按照规定角度向一侧倾斜来进行切削,之后,使直刀具101相对于铅直面P按规定角度向另一侧倾斜来进行切削。由此,通过直刀具101将密封基板15的上表面切成V状,沿着分割预定线形成V槽。
另外,图12的(B)所示,也可以使用激光烧蚀用的加工头102作为V槽形成单元而在密封基板15上形成V槽。这种情况下,使加工头102相对于密封基板15的分割预定线上的铅直面P按照规定角度在一个方向上倾斜而实施烧蚀加工,之后使加工头102相对于铅直面P按照规定角度向另一侧倾斜而实施烧蚀加工。利用对于密封基板15具有吸收性的激光光线将密封基板15的上表面切成V字状,沿着分割预定线形成V槽。
另外,如图12的(C)所示,也可以使用仿形切割机(profiler)103作为V槽形成单元而在密封基板15上形成V槽。仿形切割机103是在铝基台104的大致V字状的加工面上电沉积由金刚石磨粒构成的磨粒层而构成的。仿形切割机103与V刀具相比不容易产生消耗,能够长期持续维持V字形状。
另外,在本实施方式中,采用了在单片化步骤中使用直刀具作为分割单元的构成,但并不限于该构成。例如,如图13所示,也可以使用激光烧蚀用的加工头106作为分割单元而对密封基板15进行分割。另外,在第2实施方式中,采用了使用具有一对突起的成型磨具作为分割单元的构成,但也可以使用多个刀具来代替该成型磨具。
另外,在本实施方式中,对于在树脂层上表面形成四棱锥形状的凹凸形状的构成进行了说明,但树脂层上表面的凹凸形状只要为表面积增加的形状即可。例如,如图14所示,半导体封装108的树脂层上表面109的凹凸形状可以形成为四棱柱状。需要说明的是,在半导体封装108上形成屏蔽层的情况下,四棱柱状的凹凸形状优选考虑高宽比来形成。通过降低相邻的四棱柱的间隔与四棱柱的高度的高宽比,在四棱柱的侧面也能够形成屏蔽层。
另外,在本实施方式中,对于制造将半导体芯片藉由引线与布线基板的电极进行引线接合而成的半导体封装的构成进行了说明,但并不限于该构成。半导体封装中,半导体芯片也可以与布线基板的电极直接连接而进行倒装芯片接合。
另外,在本实施方式中,采用了对设置有凸块作为电极的密封基板进行加工的构成,但并不限于该构成。对于密封基板的电极没有特别限定,例如,可以对设置有焊盘作为电极的密封基板进行加工。
另外,在本实施方式中,采用了在保持步骤中将密封基板的与树脂层相反的一面粘贴于保持带的构成,但并不限于该构成。例如,可以将密封基板的与树脂层相反的一面用保持治具吸引保持来代替将密封基板的与树脂层相反的一面粘贴于保持带,在保持于保持治具的状态下实施后续阶段的步骤。保持治具只要能够保持基板即可,例如,其可以由卡盘工作台或基质构成。
另外,在第1实施方式中,采用了在实施了凹凸形成步骤之后实施单片化步骤的构成,但并不限于该构成。也可以在实施了单片化步骤之后实施凹凸形成步骤。
另外,在第4实施方式中,采用了不对粘贴在密封基板上的保持带进行替换而实施各步骤的构成,但并不限于该构成。也可以在V槽形成步骤和单片化步骤中使用切削用的保持带,在屏蔽层形成步骤中使用等离子体处理用的保持带。
另外,第4实施方式中,针对密封基板的V槽的形成和密封基板的单片化可以利用同一装置实施,也可以利用分开的装置实施。
另外,半导体封装并不限于用于移动电话等便携通信设备中的构成,也可以用于照相机等其他电子设备中。
另外,密封基板只要为能够形成屏蔽层的工件就没有特别限定。可以使用例如CSP(Chip Size Package,芯片尺寸封装)、WLCSP(Wafer Level Chip Size Package,晶片级芯片尺寸封装)、SIP(System In Package,系统级封装)、FOWLP(Fan Out Wafer LevelPackage,扇出型晶片级封装)用的各种基板。在FOWLP基板的情况下,也可以采用在再布线层上安装半导体芯片的构成。因此,布线基材并不限于PCB基板等布线基板,而是包括FOWLP基板的再布线层的概念。
另外,对本实施方式和变形例进行了说明,但作为本发明的其他实施方式,也可以将上述各实施方式和变形例整体或部分地组合。
另外,本发明的实施方式并不限于上述的实施方式和变形例,可以在不脱离本发明的技术思想的宗旨的范围内进行各种变更、置换、变形。进而,如果因技术的进步或衍生出的其他技术而利用其他方法实现本发明的技术思想,则也可以使用该方法进行实施。因此,权利要求书覆盖了能够包含在本发明的技术思想的范围内的全部实施方式。
另外,在本实施方式中,对于将本发明应用于半导体封装的制造方法的构成进行了说明,但也可以应用于其他封装的制造方法中。
工业实用性
如以上说明的那样,本发明具有能够提高用密封剂密封后的半导体封装的放热性的效果,特别是对用于便携通信设备的半导体封装的制造方法是有用的。
符号说明
10、108:半导体封装
11:布线基板(布线基材)
12:半导体芯片
13:树脂层
15:密封基板
22、109:树脂层上表面(密封剂表面)
34:密封剂
36:保持带
41、51、81:成型磨具
42、54、86:加工面
53、83:突起
61:模具
62:顶面
Claims (3)
1.一种半导体封装的制造方法,其制作利用密封剂进行了密封的半导体封装,其中,该制造方法具备下述步骤:
保持步骤,利用保持治具或保持带对密封基板的布线基材背面侧进行保持,该密封基板是在由交叉的分割预定线划分的布线基材表面上接合多个半导体芯片并对该布线基材的表面侧供给该密封剂进行密封而成的;
凹凸形成步骤,在实施了该保持步骤后,利用具有凹凸形状的加工面的成型磨具以未到达该半导体芯片的深度切入到该密封剂中,在该密封剂表面形成四棱锥形状的多个凹凸,使表面积增加;
单片化步骤,沿着该分割预定线将该密封基板单片化成各个半导体封装;以及
屏蔽层形成步骤,在单片化后的该半导体封装的外表面利用导电性材料形成屏蔽层。
2.一种半导体封装的制造方法,其制作利用密封剂进行了密封的半导体封装,其中,该制造方法具备下述步骤:
保持步骤,利用保持治具或保持带对密封基板的布线基材背面侧进行保持,该密封基板是在由交叉的分割预定线划分的布线基材表面上接合多个半导体芯片并对该布线基材的表面侧供给密封剂进行密封而成的;
单片化步骤,在实施了该保持步骤后,用成型磨具沿着该分割预定线切入到该保持带的中途或该保持治具内,将该密封基板单片化成各个半导体封装;以及
屏蔽层形成步骤,在单片化后的该半导体封装的外表面利用导电性材料形成屏蔽层,
该成型磨具与该分割预定线对应地形成至少2个突起,该2个突起间具有凹凸形状的加工面,
在单片化步骤中,使该突起沿着该分割预定线切入而单片化成各个半导体封装,并且以未到达进行了单片化的半导体封装的该半导体芯片的深度在该密封剂表面形成四棱锥形状的多个凹凸,使表面积增加。
3.如权利要求1或2所述的半导体封装的制造方法,其中,该制造方法包括ID标记形成步骤,在实施了该单片化步骤之后,在单片化后的半导体封装的侧面形成ID标记。
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Application Number | Priority Date | Filing Date | Title |
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JP2018052128A JP7075791B2 (ja) | 2018-03-20 | 2018-03-20 | 半導体パッケージの製造方法 |
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