CN108257879B - 半导体封装的制造方法 - Google Patents
半导体封装的制造方法 Download PDFInfo
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- CN108257879B CN108257879B CN201711338522.2A CN201711338522A CN108257879B CN 108257879 B CN108257879 B CN 108257879B CN 201711338522 A CN201711338522 A CN 201711338522A CN 108257879 B CN108257879 B CN 108257879B
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Abstract
提供半导体封装的制造方法,对侧面高效地形成规定的膜厚的屏蔽层。一种半导体封装(10)的制造方法,该半导体封装(10)由密封剂对布线基板(11)上的半导体芯片(12)进行了密封,该方法中,将多个半导体芯片接合在布线基板的正面上,对布线基板的正面提供密封剂而制作密封基板(15),从密封基板的树脂层(13)侧利用V刀具(39)进行加工而沿着分割预定线形成V槽(25),沿着V槽对布线基板进行分割而单片化成各个封装(21),在各封装的上表面(22)和侧面(23)上形成电磁波屏蔽层(16)。
Description
技术领域
本发明涉及具有屏蔽功能的半导体封装的制造方法。
背景技术
通常,在使用于移动电话等便携式通信设备的半导体封装中,要求抑制来自半导体封装的电磁噪声的泄漏。作为半导体封装,公知有利用树脂(密封剂)对搭载在布线基板上的半导体芯片进行密封并沿着树脂层的外表面形成屏蔽层的半导体封装(例如,参照专利文献1)。虽然屏蔽层有时也会通过金属板屏蔽形成,但因板厚变厚而成为阻碍设备小型化、薄型化的原因。因此,提出了通过溅射法、喷射涂布法、CVD(chemical VaporDeposition:化学气相沉积)法、喷墨法、丝网印刷法等使屏蔽层形成得较薄的技术。
专利文献1:日本特开2012-039104号公报
但是,关于专利文献1所记载的半导体封装,由于封装的侧面形成为相对于上表面大致垂直,所以很难按照均匀的厚度在封装的上表面和侧面上形成屏蔽层。并且,由于上述的溅射法等屏蔽层的成膜方法是从与半导体封装的上表面垂直的方向成膜出屏蔽层的方法,所以存在如下问题:在针对封装的侧面的屏蔽层的成膜中需要较长的时间。
发明内容
本发明是鉴于该点而完成的,其目的之一在于,提供半导体封装的制造方法,能够对侧面有效地形成规定的膜厚的屏蔽层。
根据本发明,提供半导体封装的制造方法,制造由密封剂进行了密封的半导体封装,其中,该半导体封装的制造方法具有如下的工序:芯片接合工序,将多个半导体芯片接合在布线基板正面上的由交叉的多条分割预定线划分的多个区域内;密封基板制作工序,对接合了该多个半导体芯片的该布线基板的正面侧提供密封剂而进行密封,制作密封基板;V槽形成工序,在实施了该密封基板形成工序之后,利用保持治具对该密封基板的该布线基板侧进行保持,将加工工具从该密封剂侧切入到该密封基板的厚度方向中途并沿着与该分割预定线对应的区域进行加工,按照具有从该密封剂上表面朝向加工槽底倾斜的侧面的方式形成V槽;单片化工序,在实施了该V槽形成工序之后,沿着该V槽对该布线基板进行分割而沿着该分割预定线单片化成各个封装;以及屏蔽层形成工序,在实施了该单片化工序之后,在多个该封装的该密封剂上表面和倾斜的侧面上形成电磁波屏蔽层。
根据该结构,利用加工工具从密封剂侧在密封基板上形成V槽,从而使单片化后的封装的侧面按照从密封剂侧朝下向外侧扩大的方式倾斜。由于封装的侧面在俯视下具有投影面积,所以能够容易地从与封装的上表面垂直的方向对封装的侧面形成电磁波屏蔽层。因此,能够在半导体封装的上表面和侧面按照能够发挥出充分的屏蔽效果的规定的厚度有效地形成电磁波屏蔽层。
优选半导体封装的制造方法的特征在于,还具有如下的凸块形成工序:在该V槽形成工序与该单片化工序之间,在该布线基板的背面侧形成凸块,在该单片化工序中,利用保持治具对该密封基板的该密封剂侧进行吸引保持。
优选半导体封装的制造方法还具有如下的布线基板槽形成工序:在实施该密封基板制作工序之前,沿着该分割预定线形成深度达到该布线基板的厚度方向中途的槽,在该密封基板形成工序中,将该密封剂填充到该槽内而形成该密封基板,在该V槽形成工序中,该加工工具对该密封剂进行加工而形成V槽。
根据本发明,由于单片化后的封装的侧面按照朝下向外侧扩大的方式倾斜,所以能够对侧面有效地规定的膜厚的屏蔽层。
附图说明
图1是本实施方式的半导体封装的示意性剖视图。
图2的(A)和(B)是示出比较例的半导体封装的制造方法的示意性剖视图。
图3的(A)~(D)是示出第1实施方式的半导体封装的制造方法的示意性剖视图。
图4的(A)~(C)是示出第1实施方式的半导体封装的制造方法的示意性剖视图。
图5的(A)~(D)是示出第2实施方式的半导体封装的制造方法的示意性剖视图。
图6的(A)~(C)是示出第2实施方式的半导体封装的制造方法的示意性剖视图。
图7是示出设置于试验体的电磁波屏蔽层的厚度的图。
图8是示出试验体的侧面的倾斜角与电磁波屏蔽层的厚度之间的关系的图表。
图9的(A)和(B)是示出半导体封装的变形例的示意性剖视图。
图10的(A)~(C)是示出V槽形成工序的变形例的示意性剖视图。
图11是示出半导体封装的变形例的示意性剖视图。
标号说明
10:半导体封装;11:布线基板;12:半导体芯片;13:树脂层(密封剂);14:凸块;15:密封基板;16:电磁波屏蔽层;21:封装;22:封装的上表面;23:封装的侧面;25:密封基板的V槽;26:V槽的加工槽底;27:布线基板的槽;36:保持治具;39:V刀具(加工工具)。
具体实施方式
以下,参照附图对本实施方式的半导体封装的制造方法进行说明。图1是本实施方式的半导体封装的示意性剖视图。图2是示出比较例的半导体封装的制造方法的示意性剖视图。另外,以下的实施方式只是示出了一例,在各工序之间可以具有其他工序,也可以适当更换工序的顺序。
如图1所示,半导体封装10是因所谓的EMI(Electro-Magnetic Interference:电磁干扰)而需要遮断的全部的封装的半导体装置,构成为通过外表面的电磁波屏蔽层16来抑制电磁噪声向周围泄漏。在电磁波屏蔽层16的内侧,利用树脂层(密封剂)13对安装在布线基板(中介层基板)11的上表面上的半导体芯片12进行密封,在布线基板11的下表面配设有凸块14。在布线基板11上形成有包含与半导体芯片12连接的电极及接地线17在内的各种布线。
半导体芯片12是按照硅、砷化镓等半导体基板上的器件对半导体晶片进行单片化而形成的,其接合(bonding)在布线基板11上。并且,半导体封装10的侧面23按照从上表面22朝下向外侧扩大的方式倾斜,通过溅射法等从上方对半导体封装10的倾斜的侧面23形成电磁波屏蔽层16。与一般的半导体封装的铅直的侧面不同,半导体封装10的侧面23相对于电磁波屏蔽层16的成膜方向斜交叉而容易形成电磁波屏蔽层16。
但是,通常,如图2的(A)所示的比较例那样,利用树脂层13将布线基板11上的半导体芯片12密封而得到密封基板15,使用前端为V字形状的切削刀具(以下,称为V刀具)39对密封基板15进行全切割从而使半导体封装10(参照图1)的侧面23倾斜。在该方法中,能够简化半导体封装10的制造方法,但必须在分割时对半导体封装10进行支承的保持治具111上设置用于避让凸块14的凹部112,需要重新设计保持治具111。也考虑了在将密封基板15单片化之后配设凸块14的结构,但会产生凸块14相对于封装的位置偏移。
并且,由于如上述那样在布线基板11中包含有各种布线(金属),所以在布线基板11的切削时V刀具39的消耗较严重,V刀具39的前端的V字形状容易发生变形。因此,如图2的(B)所示的比较例那样,考虑了通过使用了V刀具39和通常的切削刀具49的分步切割(stepcut)来对密封基板15进行分割的结构。由此,能够抑制V刀具39相对于布线基板11的切入量,减少V刀具39的前端的V字形状的消耗。但是,即使在这样的结构中,也必须重新设计保持治具111。
因此,在第1实施方式的半导体封装的制造方法中,在相对于密封基板15配设凸块14之前利用V刀具39对密封基板15进行半切割。由此,不需要在保持治具36(参照图3的(C))中形成用于避让凸块14的凹部,因此能够使用已知的保持治具36对密封基板15进行保持。并且,由于不使用V刀具39对密封基板15进行全切割,因此能够进行配设而不使凸块14相对于密封基板15发生位置偏移,能够抑制对布线基板11的切入量,减少V刀具39的前端的V字形状的消耗。
以下,参照图3和图4对第1实施方式的半导体封装的制造方法进行说明。图3和图4是第1实施方式的半导体封装的制造方法的说明图。另外,图3的(A)是示出芯片接合工序的一例的图,图3的(B)是示出密封基板制作工序的一例的图,图3的(C)是示出V槽形成工序的一例的图,图3的(D)是示出变形例的切削刀具的一例的图。并且,图4的(A)是示出凸块形成工序的一例的图,图4的(B)是示出单片化工序的一例的图,图4的(C)是示出屏蔽层形成工序的一例的图。
如图3的(A)所示,首先实施芯片接合工序。在芯片接合工序中,布线基板11的正面被交叉的分割预定线划分成格子状,在所划分的多个区域内接合多个半导体芯片12。在该情况下,半导体芯片12的上表面的电极与引线19的一端连接,布线基板11的正面的电极18与引线19的另一端连接。另外,在芯片接合工序中,并不限于引线接合,也可以实施如下的倒装芯片接合:将半导体芯片12的下表面的电极与布线基板11的正面的电极直接连接。
如图3的(B)所示,在实施了芯片接合工序之后实施密封基板制作工序。在密封基板制作工序中,对接合了多个半导体芯片12的布线基板11的正面侧提供密封剂24,利用密封剂24将各半导体芯片12密封而制作出密封基板15(参照图3的(C))。在该情况下,安装有半导体芯片12的布线基板11的下表面被保持在密封用的保持治具31上,并且以覆盖布线基板11的上表面的方式配置模板32。在模板32的上壁开口有注入口33,密封剂24的提供喷嘴34被定位在注入口33的上方。
然后,从提供喷嘴34通过注入口33对布线基板11的上表面提供密封剂24而将半导体芯片12密封。在该状态下,通过对密封剂24进行加热或干燥而使其硬化,制作出在布线基板11的上表面上形成了树脂层13(参照图3的(C))的密封基板15。另外,使用具有硬化性的密封剂24,例如,可以从环氧树脂、硅树脂、聚氨酯树脂、不饱和聚酯树脂、丙烯酸聚氨酯树脂或聚酰亚胺树脂等进行选择。并且,密封剂24并不限于液状,也可以使用片状、粉状的树脂。这样,将布线基板11上的多个半导体芯片12统一密封。
另外,也可以通过磨削使密封基板15(树脂层13(参照图3的(C)))的正面平坦化。通过在磨削装置(未图示)中对密封基板15进行磨削,能够将包覆于半导体芯片12的树脂层13调整为希望的厚度。这样,也可以在密封基板制作工序之后实施平坦化工序。
如图3的(C)所示,在实施了密封基板制作工序之后实施V槽形成工序。在V槽形成工序中,将密封基板15的布线基板11侧保持在V槽形成用的保持治具36上,使用前端形成为V字形状的V刀具39(加工工具)从树脂层(密封剂)13侧切入到布线基板11(密封基板15)的厚度方向中途而沿着与分割预定线对应的区域形成V槽25。在该情况下,在保持治具36的保持面37上与分割预定线对应地形成格子状的退刀槽38,在由退刀槽38划分出的各区域内形成有吸引口(未图示)。各吸引口通过吸引路与吸引源连接,通过在吸引口产生的负压将密封基板15吸引保持在保持治具36的保持面37上。
并且,V刀具39在密封基板15的外侧与密封基板15的分割预定线对齐。V刀具39利用结合剂将金刚石磨粒等固定而成形为前端呈V字形状的圆板状,并安装在主轴(未图示)的前端。V刀具39在密封基板15的外侧下降到深度达到布线基板11的厚度方向中途的位置,并使密封基板15相对于该V刀具39在水平方向上进行切削进给。由此,沿着分割预定线对密封基板15进行半切割,按照具有从树脂层13上表面朝向加工槽底26倾斜的侧面23的方式形成V槽25。
当沿着一条分割预定线对密封基板15进行半切割时,将V刀具39与相邻的分割预定线对齐而对密封基板15进行半切割。通过重复进行该半切割,在密封基板15的正面上沿着分割预定线形成多个V槽25。这样,由于在配设凸块14(参照图4的(A))之前对密封基板15进行半切割而形成V槽25,所以在V槽形成时能够使用已知的保持治具36对密封基板15进行保持。因此,不像比较例那样需要用于避让凸块14的凹部,不需要重新设计保持治具。
另外,在本实施方式中,V刀具39的前端形成为尖锐的V字形状,但并不限定于该结构。V刀具39的前端为能够对密封基板15形成V槽25的形状即可。例如,如图3的(D)所示,切削刀具40的前端也可以形成为平坦的V字形状。即,切削刀具的前端为V字形状是指如下的形状:并不限于直至切削刀具的前端完全变尖的V字形状,也包含切削刀具的前端平坦的大致V字形状。并且,V刀具的前端的V字面不需要呈直线状倾斜,也可以带圆角。
如图4的(A)所示,在实施了V槽形成工序之后实施凸块形成工序。在凸块形成工序中,在布线基板11的背面侧形成凸块14。在该情况下,将密封基板15的正背面翻转而利用凸块形成用的保持治具41对密封基板15的树脂层(密封剂)13侧进行吸引保持。然后,使密封基板15的布线基板11的背面侧向上方露出,在布线基板11的背面配设凸块14。凸块14成为将半导体封装10(参照图4的(C))安装于各种基板时的端子或电极,其形成在与布线基板11的布线图案对应的规定的位置。由于在密封基板15的单片化之前形成凸块14,所以防止了凸块14相对于密封基板15发生位置偏移。
如图4的(B)所示,在实施了凸块形成工序之后实施单片化工序。在单片化工序中,沿着V槽25对布线基板11进行分割而单片化成沿着分割预定线的各个封装21。在该情况下,在使凸块14朝向上侧的状态下将密封基板15的树脂层13侧吸引保持在单片化用的保持治具46的保持面47上,在密封基板15的外侧将切削刀具49与密封基板15的分割预定线对齐。保持治具46与V槽形成用的保持治具36同样地构成,切削刀具49利用结合剂将金刚石磨粒等固定而成形为圆板状,并安装在主轴(未图示)的前端。
切削刀具49在密封基板15的外侧下降到将布线基板11切断的深度,使密封基板15相对于该切削刀具49在水平方向上进行切削进给从而进行全切割。当沿着一条分割预定线对密封基板15进行全切割时,将相邻的分割预定线与切削刀具49对齐而对密封基板15进行全切割。通过重复进行该切断动作,将密封基板15沿着分割预定线分割成各个封装21。另外,虽然切削刀具49在切削中会消耗,但由于切削刀具49的侧面形状的变化较少,所以能够笔直地形成切断面。
如图4的(C)所示,在实施了单片化工序之后实施屏蔽层形成工序。在屏蔽层形成工序中,在多个封装21的树脂层13的上表面22和倾斜的侧面23上形成电磁波屏蔽层16。在该情况下,从保持治具46(参照图4的(B))拾取封装21,并将封装21排列配置在屏蔽用的保持治具51上。在保持治具51的保持面52上排列形成有多个凹部53,在各凹部53中收纳各封装21的凸块14。另外,保持治具51也可以在每个凹部53中形成对封装21进行吸引保持的吸引口(未图示)。
然后,相对于封装21从上方使导电性材料成膜,在封装21的上表面22和侧面23形成电磁波屏蔽层16。电磁波屏蔽层16是由铜、钛、镍、金等中的一种以上的金属形成的厚度为数μm以上的多层膜,例如,通过溅射法、离子镀法、喷射涂布法、CVD(chemical VaporDeposition)法、喷墨法、丝网印刷法来形成该电磁波屏蔽层16。另外,也可以通过如下的真空层压来形成电磁波屏蔽层16:在真空气氛下将具有上述的多层膜的金属膜粘接在封装21的上表面22和侧面23上。
此时,封装21的侧面23按照从上表面22朝下向外侧扩大的方式倾斜,封装21的侧面23的斜面相对于电磁波屏蔽层16的成膜方向(铅直方向)斜交叉。因此,当从上方对封装21成膜出电磁波屏蔽层16时,不仅能够在封装21的上表面22上,还能够在侧面23上按照能够发挥出充分屏蔽效果的程度的厚度容易地形成电磁波屏蔽层16。这样,制造出封装21的上表面22和侧面23被电磁波屏蔽层16覆盖的半导体封装10。
由于电磁波屏蔽层16与接地线17连接,所以在半导体封装10中产生的电磁噪声通过接地线17释放至半导体封装10之外。另外,由于封装21的侧面23的下端侧是垂直形成的,所以无法与斜面同样地成膜。但是,由于通过设置于布线基板11的多个布线来切断电磁噪声,所以即使封装21的侧面23的垂直部分的电磁波屏蔽层16形成得较薄,也能够充分地遮蔽电磁噪声。因此,有效地防止了电磁噪声向半导体封装10的周围的电子部件泄漏。
另外,在第1实施方式的半导体封装的制造方法中,V槽形成工序和单片化工序也可以在同一切削装置中实施。并且,在制造无凸块14的半导体封装的情况下也可以省略凸块形成工序。并且,在预先准备了密封基板15的情况下也可以省略芯片接合工序和密封基板制作工序。
如以上那样,根据第1实施方式的半导体封装的制造方法,利用V刀具39从树脂层13侧对密封基板15进行切削,由此,单片化的封装21的侧面23按照从树脂层13侧朝下向外侧扩大的方式倾斜。由于封装21的侧面23在俯视下具有投影面积,所以能够从与封装21的上表面22垂直的方向对封装21的侧面23容易地形成电磁波屏蔽层16。因此,能够在半导体封装10的上表面22和侧面23上按照能够发挥出充分的屏蔽效果的规定的厚度有效地形成电磁波屏蔽层16。
这里,密封基板15是在严重消耗V刀具39的布线基板11上层叠了对V刀具39消耗较少的树脂层13而形成的。因此,在第1实施方式的半导体封装的制造方法中,由于在V槽形成工序中同时对布线基板11和树脂层13这样种类不同的材料进行切削,所以对V刀具39的消耗量及前端的V字形状的角度管理较难。因此,在第2实施方式中,在制作密封基板15之前形成避免布线基板11与V刀具39接触的退刀槽并利用树脂填满,从而在V槽形成时利用V刀具39仅对树脂进行切削。
以下,参照图5和图6对第2实施方式的半导体封装的制造方法进行说明。图5的(A)是示出布线基板槽形成工序的一例,图5的(B)是示出芯片接合工序的一例的图,图5的(C)是示出密封基板制作工序的一例的图,图5的(D)是示出凸块形成工序的一例的图。图6的(A)是示出V槽形成工序的一例的图,图6的(B)是示出单片化工序的一例的图,图6的(C)是示出屏蔽层形成工序的一例的图。另外,简化了与第1实施方式的半导体封装的制造方法同样的结构而进行说明。
如图5的(A)所示,首先实施布线基板槽形成工序。在布线基板槽形成工序中,沿着分割预定线形成深度达到布线基板11的厚度方向中途的(例如将接地线17切断的深度)槽27。在该情况下,布线基板11的背面侧被吸引保持在槽形成用的保持治具56上,使切削刀具59在布线基板11的外侧与布线基板11的分割预定线对齐。切削刀具59利用结合剂将金刚石磨粒等固定而成形为圆板状,并安装在主轴(未图示)的前端。另外,虽然切削刀具59因切削布线基板11而产生消耗,但与V刀具39不同的是切削刀具59的侧面形状的变化较少,因此能够形成为恒定的槽宽。
切削刀具59在布线基板11的外侧下降到深度达到布线基板11的厚度方向中途的位置,并对布线基板11相对于该切削刀具59在水平方向上进行切削进给。当沿着一条分割预定线对布线基板11进行半切割时,使切削刀具59与相邻的分割预定线对齐而对布线基板11进行半切割。通过重复进行该切断动作,在布线基板11上形成沿着分割预定线的槽27。由此,沿着分割预定线而形成用于在后面的V槽形成工序中避免布线基板11与V刀具39(参照图6的(A))接触的退刀槽。
如图5的(B)所示,在实施了布线基板槽形成工序之后实施芯片接合工序。在芯片接合工序中,在由沿着分割预定线的槽27划分出的各区域内配置半导体芯片12。然后,使半导体芯片12的上表面的电极与引线19的一端连接,使布线基板11的正面的电极18与引线19的另一端连接,使布线基板11与多个半导体芯片12进行引线接合。另外,在芯片接合工序中并不限于引线接合,也可以实施将半导体芯片12的下表面的电极与布线基板11的正面的电极直接连接的倒装芯片接合。
如图5的(C)所示,在实施了芯片接合工序之后实施密封基板制作工序。在密封基板制作工序中,从提供喷嘴34通过模板32的注入口33对密封用的保持治具31上的布线基板11提供密封剂24,利用密封剂24将半导体芯片12密封,并且向布线基板11的槽27内填充密封剂24。在该状态下,通过加热或干燥来使密封剂24硬化,制作出在布线基板11的上表面上形成有树脂层13(参照图5的(D))的密封基板15。另外,也可以在密封基板制作工序之后实施通过磨削使树脂层平坦化的平坦化工序。
如图5的(D)所示,在实施了密封基板制作工序之后实施凸块形成工序。在凸块形成工序中,将密封基板15的正背面翻转而利用凸块形成用的保持治具41对密封基板15的树脂层13侧进行吸引保持。然后,使密封基板15的布线基板11的背面侧向上方露出,在布线基板11的背面上配设凸块14。凸块14成为将半导体封装10安装于各种基板时的端子或电极,并形成在与布线基板11的布线图案对应的规定位置。由于在密封基板15的单片化之前形成凸块14,所以防止了凸块14相对于密封基板15发生位置偏移。
如图6的(A)所示,在实施了凸块形成工序之后实施V槽形成工序。在V槽形成工序中,将密封基板15的布线基板11侧保持在V槽形成用的保持治具61上,利用V刀具39从树脂层13侧切入到布线基板11(密封基板15)的厚度方向中途而沿着分割预定线(槽27)形成V槽25。在该情况下,在保持治具61的保持面62上形成有对凸块14进行收纳的凹部63,在相邻的凹部63之间形成有与分割预定线对应的退刀槽64。凹部63内通过吸引路而与吸引源连接,通过产生于凹部63的负压将密封基板15吸引保持在保持治具61的保持面62上。
并且,V刀具39在密封基板15的外侧与分割预定线对齐,使密封基板15相对于V刀具39在水平方向上进行切削进给。此时,V刀具39的前端进入到布线基板11的槽27内,避免了V刀具39与布线基板11的接触。由于通过V刀具39仅对树脂层13进行切削,所以抑制了V刀具39的消耗,能够使成形修整时机延迟而延长刀具寿命。另外,V刀具39的前端是能够对密封基板15形成V槽25的形状即可,如图3的(D)所示,切削刀具40的前端也可以形成为平坦的V字形状。
如图6的(B)所示,在实施了V槽形成工序之后实施单片化工序。在单片化工序中,在密封基板15的布线基板11侧被保持在保持治具61上的状态下,利用切削刀具49对密封基板15进行全切割,将密封基板15沿着分割预定线分割成各个封装21。此时,由于切削刀具49的前端进入到保持治具61的退刀槽64中,所以防止了切削刀具49与保持治具61的干涉。另外,切削刀具49因切削布线基板11而产生消耗,但与V刀具39不同的是切削刀具49的侧面形状的变化较少,因此能够笔直地形成切断面。
如图6的(C)所示,在实施了单片化工序之后实施屏蔽层形成工序。在屏蔽层形成工序中,按照屏蔽用的保持治具51的每个凹部53来配置封装21,使导电性材料相对于封装21从上方成膜,在封装21的上表面22和侧面23形成电磁波屏蔽层16。电磁波屏蔽层16是由铜、钛、镍、金等中的一种以上的金属形成的厚度为数μm以上的多层膜,例如,也可以通过溅射法、离子镀法、喷射涂布法、CVD(chemicalVapor Deposition)法、喷墨法、丝网印刷法、真空层压法来形成该电磁波屏蔽层16。
此时,由于封装21的侧面23按照从上表面22朝下向外侧扩大的方式倾斜,所以不仅容易在封装21的上表面22上,还容易在侧面23上按照希望的厚度形成电磁波屏蔽层16。这样,制造出封装21的上表面22和侧面23被电磁波屏蔽层16覆盖的半导体封装10。由于电磁波屏蔽层16与接地线17连接,所以在半导体封装10中产生的电磁噪声通过接地线17释放至半导体封装10之外。因此,有效地防止了电磁噪声向半导体封装10的周围的电子部件泄漏。
另外,在第2实施方式中,采用了在芯片接合工序之前实施布线基板槽形成工序的结构,但并不限定于该结构。布线基板槽形成工序在密封基板制作工序之前实施即可,也可以在芯片接合工序与密封基板制作工序之间实施。此外,在第2实施方式中,也可以与第1实施方式同样地在V槽形成工序与单片化工序之间实施凸块形成工序。通过在V槽形成后形成凸块14,在V槽形成工序和单片化工序的保持治具61中不需要用于避让凸块14的凹部63,能够使用已知的保持治具。
如以上那样,根据第2实施方式的半导体封装的制造方法,与第1实施方式同样,能够在半导体封装10的上表面22和侧面23上按照能够发挥出充分的屏蔽效果的规定的厚度有效地形成电磁波屏蔽层16。并且,由于通过V刀具39仅对树脂层13进行切削,所以能够抑制V刀具39的消耗,延长刀具寿命。
接着,对半导体封装的侧面的倾斜角度与电磁波屏蔽层之间的关系进行说明。图7是示出设置于试验体的电磁波屏蔽层的厚度的图。图8是示出试验体的侧面的倾斜角与电磁波屏蔽层的厚度之间的关系的图。
如图7所示,准备多个改变了侧面82的倾斜角度θ的试验体80,在180℃、8×10-4Pa的条件下通过离子镀法来形成屏蔽层。侧面82的倾斜角度θ为90°、82°、68°、60°、45°。并且,按照形成于上表面81的上部屏蔽层83和形成于侧面82的侧部屏蔽层84来进行划分,根据扫描型电子显微镜的观察图像对上部屏蔽层83和侧部屏蔽层84的厚度t1、t2进行测量。上部屏蔽层83和侧部屏蔽层84的厚度t1、t2作为下述式(1)所示的阶部包覆率(step coverage)的值而计算出,在图8中汇总了该值与倾斜角度θ之间的关系。
step coverage=(t2/t1)×100(1)
其结果是,随着倾斜角度θ从90°变小,阶部包覆率的值逐渐变大,当倾斜角度θ为45°时阶部包覆率的值为100%。具体来说,在倾斜角度θ被设定为45°的情况下,上部屏蔽层83的厚度t1与侧部屏蔽层84的厚度t2一致,在试验体80的上表面22和侧面23上确认了厚度均匀的电磁波屏蔽层16。并且,根据发明者的实验,当阶部包覆率的值低于50%时,侧部屏蔽层84的成膜需要时间,工艺成本会增大,因此优选阶部包覆率的值为50%以上的范围。因此,优选半导体封装的侧面的倾斜角度θ为45°以上并且为82°以下,优选V刀具39的前端的角度为90°以上并且为36°以下。
另外,在第1、第2实施方式中,例示了在布线基板上安装了1个半导体芯片的半导体封装,但并不限定于该结构。也可以制造出在布线基板上安装了多个半导体芯片的半导体封装。例如,也可以制造出如下的半导体封装90:如图9的(A)所示,将多个(例如,3个)半导体芯片92a、92b、92c安装在布线基板91上,并对半导体芯片92a、92b、92c一起进行屏蔽。在该情况下,在V槽形成工序中以封装为单位在密封基板95中形成V槽,在单片化工序中以封装为单位对密封基板95进行分割。另外,半导体芯片92a、92b、92c可以具有相同的功能,也可以具有不同的功能。
并且,也可以制造出如下的半导体封装(SIP)100:如图9的(B)所示,将多个(例如,两个)半导体芯片102a、102b安装在布线基板101上,并对半导体芯片102a、102b单独进行屏蔽。在该情况下,在V槽形成工序中以半导体芯片为单位在密封基板105上形成V槽106,在单片化工序中以封装为单位对密封基板105进行分割。由此,在半导体芯片102a、102b之间形成有电磁波屏蔽层107,能够防止电磁噪声在半导体芯片102a、102b彼此之间产生影响。另外,半导体芯片102a、102b可以具有相同的功能,也可以具有不同的功能。
并且,在上述的第1、第2实施方式中,使用V刀具作为加工工具来实施V槽形成工序,但并不限定于该结构。V槽形成工序对密封基板从树脂层侧朝向槽底形成V槽即可。例如,如图10的(A)所示,也可以使用通常的切削刀具108作为加工工具而在密封基板15上形成V槽。在该情况下,使切削刀具108相对于密封基板15的分割预定线上的铅直面按照规定的角度向一侧倾斜而进行切削,之后,使切削刀具108相对于铅直面P按照规定的角度向另一侧倾斜而进行切削。由此,通过切削刀具108将密封基板15的上表面切成V状,沿着分割预定线形成V槽。
并且,如图10的(B)所示,也可以使用激光烧蚀用的加工头109作为加工工具而在密封基板15上形成V槽25。在该情况下,使加工头109相对于密封基板15的分割预定线上的铅直面P按照规定的角度在一个方向上倾斜而实施烧蚀加工,之后,使加工头109相对于铅直面P按照规定的角度向另一侧倾斜而实施烧蚀加工。通过对于密封基板15具有吸收性的激光光线将密封基板15的上表面切成V字状,沿着分割预定线形成V槽。其中,激光烧蚀是指如下的现象:当激光光线的照射强度为规定的加工阈值以上时,在固体表面上转换成电、热、光科学和力学能量,其结果是,爆炸性地释放出中性原子、分子、正负离子、自由基、簇、电子和光,固体表面被蚀刻。
并且,如图10的(C)所示,也可以使用成型工具(profiler)115作为加工工具而在密封基板16上形成V槽25。成型工具115构成为在铝基台116的大致V字状的加工面上电镀由金刚石磨粒形成的磨粒层117。成型工具115与V刀具39相比不容易产生消耗,能够较长时间地持续维持V字形状。
并且,在上述的第1、第2实施方式中,使用切削刀具来实施单片化工序,但并不限定于该结构。单片化工序将密封基板分割成各个封装即可,例如,也可以通过烧蚀加工将密封基板分割成各个封装。
并且,在上述的第1、第2实施方式中,采用将布线基板保持在各保持治具上而实施各工序的结构,但并不限定于该结构。例如,也可以在对布线基板的背面粘贴保护带并隔着带将布线基板载置在基台等上的状态下实施各工序。并且,保持治具能够对基板进行保持即可,例如,也可以适当使用具有多孔制的保持面的卡盘工作台。
半导体封装并不限于使用在移动电话等便携式通信设备中的结构,也可以使用在照相机等其他的电子设备中。
并且,在上述的第1、第2实施方式和变形例中,对制造使半导体芯片经由引线与布线基板的电极进行引线接合的半导体封装的结构进行了说明,但并不限定于该结构。如图11所示,半导体封装10也可以使半导体芯片12与布线基板11的电极直接连接而进行倒装芯片接合。
对本实施方式和变形例进行了说明,但作为本发明的其他实施方式,也可以对上述各实施方式和变形例进行整体或局部地组合。
并且,本发明的实施方式并不限定于上述的各实施方式和变形例,也可以在不脱离本发明的技术思想的主旨的范围内进行各种变更、置换、变形。进而,如果因技术的进步或衍生出的其他技术而利用其他方法实现本发明的技术思想,则也可以使用该方法进行实施。因此,权利要求书覆盖了能够包含在本发明的技术思想的范围内的所有实施方式。
并且,在本实施方式中,对将本发明应用于半导体封装的制造方法的结构进行了说明,但也可以应用在形成规定的膜厚的屏蔽层的其他封装部件的制造方法中。
如以上所说明的那样,本发明具有能够对侧面有效地形成规定的膜厚的屏蔽层的效果,特别是对使用在便携式通信设备中的半导体封装的制造方法有用。
Claims (3)
1.一种半导体封装的制造方法,制造由密封剂进行了密封的半导体封装,其中,该半导体封装的制造方法具有如下的工序:
芯片接合工序,将多个半导体芯片接合在布线基板正面上的由交叉的多条分割预定线划分的多个区域内;
密封基板制作工序,对接合了该多个半导体芯片的该布线基板的正面侧提供密封剂而进行密封,制作密封基板;
V槽形成工序,在实施了该密封基板制作工序之后,利用保持治具对该密封基板的该布线基板的背面侧进行保持,将加工工具从该密封剂侧切入到该密封基板的厚度方向中途并沿着与该分割预定线对应的区域进行加工,按照具有从该密封剂上表面朝向加工槽底倾斜的侧面的方式形成V槽;
正背面翻转工序,在该V槽形成工序之后,将该密封基板的该布线基板的正背面翻转,使得该密封基板的正面侧与保持治具对置;
单片化工序,在实施了该正背面翻转工序之后,沿着该V槽对该布线基板进行分割而沿着该分割预定线单片化成各个封装;以及
屏蔽层形成工序,在实施了该单片化工序之后,在多个该封装的该密封剂上表面和倾斜的侧面上形成电磁波屏蔽层。
2.根据权利要求1所述的半导体封装的制造方法,其中,
该方法还具有如下的凸块形成工序:在该正背面翻转工序与该单片化工序之间,在该布线基板的背面侧形成凸块,
在该单片化工序中,利用保持治具对该密封基板的该密封剂侧进行吸引保持。
3.根据权利要求1或2所述的半导体封装的制造方法,其中,
该方法还具有如下的布线基板槽形成工序:在实施该密封基板制作工序之前,沿着该分割预定线形成深度达到该布线基板的厚度方向中途的槽,
在该密封基板制作工序中,将该密封剂填充到该槽内而形成该密封基板,
在该V槽形成工序中,该加工工具对该密封剂进行加工而形成V槽。
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