TWI729235B - 半導體封裝的製造方法 - Google Patents
半導體封裝的製造方法 Download PDFInfo
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- TWI729235B TWI729235B TW106138572A TW106138572A TWI729235B TW I729235 B TWI729235 B TW I729235B TW 106138572 A TW106138572 A TW 106138572A TW 106138572 A TW106138572 A TW 106138572A TW I729235 B TWI729235 B TW I729235B
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Abstract
本發明的課題是在於有效率地對於側面形成預定的膜厚的屏蔽層。 其解決手段為一種以密封劑來密封配線基板(11)上的半導體晶片(12)之半導體封裝(10)的製造方法,在配線基板的表面接合複數的半導體晶片,在配線基板的表面供給密封劑而作成密封基板(15),從密封基板的樹脂層(13)側以V刀刃(39)加工沿著分割預定線來形成V溝(25),沿著V溝來分割配線基板而小片化成各個的封裝(21),在各封裝的上面(22)及側面(23)形成電磁波屏蔽層(16)。
Description
[0001] 本發明是有關具有屏蔽機能的半導體封裝的製造方法。
[0002] 一般,被使用在行動電話等的攜帶型通訊機器之半導體封裝是被要求抑制來自半導體封裝的電磁雜訊的洩漏。半導體封裝是有以樹脂(密封劑)來密封被搭載於配線基板上的半導體晶片,沿著樹脂層的外面來形成屏蔽層者為人所知(例如參照專利文獻1)。屏蔽層是也有以板金屏蔽來形成的情況,但因板厚變大,形成機器的小型化或薄型化的阻礙要因。因此,藉由濺射法、噴霧塗佈法、CVD(chemical Vapor Deposition)法、噴墨法、網板印刷法等來薄薄地形成屏蔽層的技術被提案。 [先前技術文獻] [專利文獻] [0003] [專利文獻1]日本特開2012-039104號公報
(發明所欲解決的課題) [0004] 然而,專利文獻1記載的半導體封裝是封裝的側面相對於上面形成大致垂直,因此難以在側面以和封裝的上面均一的厚度來形成屏蔽層。並且,上述的濺射法等的屏蔽層的成膜方法是從與半導體封裝的上面垂直的方向來將屏蔽層成膜,因此會有屏蔽層對於封裝的側面的成膜需要長時間的問題。 [0005] 本發明是有鑑於如此的點而研發者,以提供一種可有效率地對於側面形成預定的膜厚的屏蔽層之半導體封裝的製造方法為其目的之一。 (用以解決課題的手段) [0006] 若根據本發明,則可提供半導體封裝的製造方法,係製造藉由密封劑來密封的半導體封裝之半導體封裝的製造方法,其特徵係具備: 晶片接合工程,其係將複數的半導體晶片接合於藉由交叉的複數的分割預定線來區劃的配線基板表面上的複數領域; 密封基板作成工程,其係於接合有該複數的半導體晶片的該配線基板的表面側供給密封劑而密封作成密封基板; V溝形成工程,其係於實施該密封基板形成工程之後,以保持治具來保持該密封基板的該配線基板側,將加工工具從該密封劑側切入至該密封基板的厚度方向途中,沿著對應於該分割預定線的領域來加工,以具備從該密封劑上面朝加工溝底傾斜的側面之方式形成V溝; 小片化工程,其係於實施該V溝形成工程之後,沿著該V溝來分割該配線基板,沿著該分割預定線來小片化成各個的封裝;及 屏蔽層形成工程,其係於實施該小片化工程之後,在複數的該封裝的該密封劑上面及傾斜的側面形成電磁波屏蔽層。 [0007] 若根據此構成,則藉由以加工工具來從密封劑側形成V溝於密封基板,被小片化的封裝的側面會傾斜成為從密封劑側朝下方擴大至外側。由於上面視封裝的側面具有投影面積,所以可容易從與封裝的上面垂直的方向來對於封裝的側面形成電磁波屏蔽層。因此,可有效率地在半導體封裝的上面及側面以能夠發揮充分的屏蔽效果之預定的厚度來形成電磁波屏蔽層。 [0008] 較理想是半導體封裝之製造方法在該V溝形成工程與該小片化工程之間更具備凸塊形成工程,其係於該配線基板的背面側形成凸塊,在該小片化工程中,以保持治具來吸引保持該密封基板的該密封劑側為特徵。 [0009] 較理想是半導體封裝的製造方法在實施該密封基板作成工程之前,更具備配線基板溝形成工程,其係沿著該分割預定線來形成至該配線基板的厚度方向途中的深度的溝,在該密封基板形成工程中,使該密封劑充填於該溝內而形成該密封基板,在該V溝形成工程中,該加工工具係加工該密封劑來形成V溝。 [發明的效果] [0010] 若根據本發明,則由於被小片化的封裝的側面會以朝下方擴大至外側的方式傾斜,因此可有效率地對於側面形成預定的膜厚的屏蔽層。
[0012] 以下,參照附圖來說明有關本實施形態的半導體封裝的製造方法。圖1是本實施形態的半導體封裝的模式性剖面圖。圖2是表示比較例的半導體封裝的製造方法的模式性剖面圖。另外,以下的實施形態究竟是表示一例,亦可在各工程間具備其他的工程,或適當替換工程的順序。 [0013] 如圖1所示般,半導體封裝10是所謂的EMI(Electro-Magnetic Interference)需要遮斷的全部的封裝的半導體裝置,被構成為藉由外面的電磁波屏蔽層16來抑制朝周圍之電磁雜訊的洩漏。在電磁波屏蔽層16的內側,被安裝於配線基板(中介層基板)11的上面之半導體晶片12會以樹脂層(密封劑)13來密封,在配線基板11的下面配設有凸塊14。在配線基板11是形成有包含被連接至半導體晶片12的電極或接地線17之各種配線。 [0014] 半導體晶片12是按矽、鎵砷等的半導體基板上的每個裝置來使半導體晶圓小片化而形成,被接合於配線基板11上。並且,半導體封裝10的側面23是以從上面22朝下方擴大至外側的方式傾斜,對於半導體封裝10的傾斜後的側面23,藉由濺射法等來從上方形成電磁波屏蔽層16。與一般性的半導體封裝的鉛直的側面不同,半導體封裝10的側面23是對於電磁波屏蔽層16的成膜方向傾斜地交叉而容易形成電磁波屏蔽層16。 [0015] 可是通常如圖2A所示的比較例般,使用前端為V字形狀的切削刀刃(以下稱為V刀刃)39來全切以樹脂層13密封配線基板11上的半導體晶片12之密封基板15,藉此半導體封裝10(參照圖1)的側面23會被傾斜。此方法是可使半導體封裝10的製造方法簡略化,但在分割時必須在支撐半導體封裝10的保持治具111設置用以使凸塊14逃避的凹部112,需要重新設計保持治具111。雖亦可思考在使密封基板15小片化後配設凸塊14的構成,但會發生凸塊14對於封裝的位移。 [0016] 又,如上述般,由於在配線基板11是含有各種的配線(金屬),因此在配線基板11的切削時,V刀刃39的消耗激烈,V刀刃39的前端的V字形狀容易崩潰。因此,如圖2B所示的比較例般,可思考以使用V刀刃39及通常的切削刀刃49之階梯式切割來分割密封基板15的構成。藉此,壓低V刀刃39對於配線基板11的切入量,可使V刀刃39的前端的V字形狀的消耗減少。然而,即使是如此的構成,也必須重新設計保持治具111。 [0017] 於是,在第1實施形態的半導體封裝的製造方法中,使在凸塊14對於密封基板15的配設前以V刀刃39來半切(half-cut)密封基板15。藉此,由於在保持治具36(參照圖3C)不須形成用以避開凸塊14的凹部,因此可使用既存的保持治具36來保持密封基板15。又,由於不以V刀刃39來全切密封基板15,因此對於密封基板15可不位移凸塊14來配設,壓低對於配線基板11的切入量而可使V刀刃39的前端的V字形狀的消耗減少。 [0018] 以下,參照圖3及圖4來說明有關第1實施形態的半導體封裝的製造方法。圖3及圖4是第1實施形態的半導體封裝的製造方法的說明圖。另外,圖3A是晶片接合工程,圖3B是密封基板作成工程,圖3C是V溝形成工程,圖3D是變形例的切削刀刃,分別表示各一例的圖。又,圖4A是凸塊形成工程,圖4B是小片化工程,圖4C是屏蔽層形成工程,分別表示各一例的圖。 [0019] 如圖3A所示般,首先晶片接合工程會被實施。在晶片接合工程中,配線基板11的表面會藉由交叉的分割預定線來區劃成格子狀,複數的半導體晶片12會接合於被區劃的複數的領域。此情況,接線19的一端會被連接至半導體晶片12的上面的電極,接線19的另一端會被連接至配線基板11的表面的電極18。另外,在晶片接合工程中,不限於打線接合,亦可實施將半導體晶片12的下面的電極直接連接至配線基板11的表面的電極之覆晶接合。 [0020] 如圖3B所示般,晶片接合工程被實施後,密封基板作成工程會被實施。在密封基板作成工程中,密封劑24會被供給至接合有複數的半導體晶片12之配線基板11的表面側,各半導體晶片12會以密封劑24來密封而作成密封基板15(參照圖3C)。此情況,安裝有半導體晶片12的配線基板11的下面會被保持於密封用的保持治具31,以覆蓋配線基板11的上面之方式配置框架32。在框架32的上壁是開有注入口33,在注入口33的上方是定位有密封劑24的供給噴嘴34。 [0021] 然後,從供給噴嘴34經由注入口33來供給密封劑24至配線基板11的上面而密封半導體晶片12。在此狀態下,密封劑24會被藉由加熱或乾燥而被硬化,作成在配線基板11的上面形成樹脂層13(參照圖3C)的密封基板15。另外,密封劑24是使用具有硬化性者,例如可由環氧樹脂、矽樹脂、聚氨酯樹脂、不飽和聚酯纖維樹脂、丙烯聚氨酯樹脂、或聚醯亞胺樹脂等來選擇。並且,密封劑24是不限於液狀,亦可使用薄板狀、粉末狀的樹脂。如此,配線基板11上的複數的半導體晶片12會一起被密封。 [0022] 另外,亦可藉由研削來使密封基板15(樹脂層13(參照圖3C))的表面平坦化。藉由以研削裝置(未圖示)來研削密封基板15,可將被覆半導體晶片12的樹脂層13調整成所望的厚度。如此,亦可在密封基板作成工程之後實施平坦化工程。 [0023] 如圖3C所示般,密封基板作成工程被實施後,V溝形成工程會被實施。在V溝形成工程中,密封基板15的配線基板11側會被保持於V溝形成用的保持治具36,以前端被形成V字形狀的V刀刃39(加工工具)來從樹脂層(密封劑)13側切入至配線基板11(密封基板15)的厚度方向途中,沿著對應於分割預定線的領域來形成V溝25。此情況,在保持治具36的保持面37是對於分割預定線而形成有格子狀的逃避溝38,在以逃避溝38所區劃的各領域形成有吸引口(未圖示)。各吸引口是經由吸引路來連接至吸引源,藉由在吸引口產生的負壓,密封基板15會被吸引保持於保持治具36的保持面37。 [0024] 並且,V刀刃39是在密封基板15的外側被對位於密封基板15的分割預定線。V刀刃39是以結合劑來固定鑽石砥粒等,被形成前端為V字形狀的圓板狀,安裝於主軸(未圖示)的前端。在密封基板15的外側,V刀刃39被下降至配線基板11的厚度方向途中的深度為止,相對於此V刀刃39,密封基板15會被切削進給於水平方向。藉此,密封基板15會沿著分割預定線來半切,以具備從樹脂層13上面朝加工溝底26傾斜的側面23之方式形成V溝25。 [0025] 一旦沿著一條的分割預定線來半切密封基板15,則V刀刃39會被對位於旁邊的分割預定線來半切密封基板15。藉由重複此半切,複數的V溝25會沿著分割預定線來形成於密封基板15的表面。如此,由於在配設凸塊14(參照圖4A)之前密封基板15會被半切而形成有V溝25,所以在V溝形成時利用既存的保持治具36來保持密封基板15。因此,不需要如比較例般用以使凸塊14逃避的凹部,不須重新設計保持治具。 [0026] 另外,在本實施形態中,V刀刃39的前端會被形成尖的V字形狀,但並限於此構成。V刀刃39的前端是只要對於密封基板15可形成V溝25的形狀即可。例如圖3D所示般,切削刀刃40的前端亦可形成平坦的V字形狀。亦即,所謂切削刀刃的前端為V字形狀,是不限於至切削刀刃的前端為止完全尖的V字形狀,也包含切削刀刃的前端為平坦的大致V字形狀的形狀。並且,V刀刃的前端的V字面是不須直線地傾斜,亦可些微帶圓弧。 [0027] 如圖4A所示般,V溝形成工程被實施後,凸塊形成工程會被實施。在凸塊形成工程中,凸塊14會被形成於配線基板11的背面側。此情況,密封基板15會被表背反轉,密封基板15的樹脂層(密封劑)13側會以凸塊形成用的保持治具41來吸引保持。然後,密封基板15的配線基板11的背面側會被露出於上方,在配線基板11的背面配設有凸塊14。凸塊14是形成將半導體封裝10(參照圖4C)安裝於各種基板時的端子或電極,被形成於對應於配線基板11的配線圖案之預定位置。由於在密封基板15的小片化前形成凸塊14,因此凸塊14對於密封基板15的位移會被防止。 [0028] 如圖4B所示般,凸塊形成工程被實施後,小片化工程會被實施。在小片化工程中,沿著V溝25來分割配線基板11而被小片化成沿著分割預定線的各個的封裝21。此情況,在將凸塊14朝向上側的狀態下,密封基板15的樹脂層13側會被吸引保持於小片化用的保持治具46的保持面47,在密封基板15的外側,切削刀刃49會被對位於密封基板15的分割預定線。保持治具46是與V溝形成用的保持治具36同樣構成,切削刀刃49是以結合劑來固定鑽石砥粒等而被成形為圓板狀,安裝於主軸(未圖示)的前端。 [0029] 在密封基板15的外側,切削刀刃49會下降至將配線基板11切斷的深度,相對於此切削刀刃49,密封基板15會被切削進給於水平方向,藉此被全切。一旦沿著一條的分割預定線來全切密封基板15,則切削刀刃49會被對位於旁邊的分割預定線來全切密封基板15。藉由重複此切斷動作,密封基板15會沿著分割預定線來分割成各個的封裝21。另外,在切削中雖切削刀刃49會消耗,但由於切削刀刃49的側面形狀的變化少,因此可鉛直地形成切剖面。 [0030] 如圖4C所示般,小片化工程被實施後,屏蔽層形成工程會被實施。在屏蔽層形成工程中,電磁波屏蔽層16會被形成於複數的封裝21的樹脂層13的上面22及傾斜的側面23。此情況,從保持治具46(參照圖4B)拾取封裝21,排列配置於屏蔽用的保持治具51。在保持治具51的保持面52是排列形成有多數的凹部53,各封裝21的凸塊14會被收容於各凹部53。另外,保持治具51是亦可按每個凹部53來形成吸引保持封裝21的吸引口(未圖示)。 [0031] 然後,對於封裝21從上方形成導電性材料膜,在封裝21的上面22及側面23形成電磁波屏蔽層16。電磁波屏蔽層16是藉由銅、鈦、鎳、金等的其中一個以上的金屬來成膜之厚度數μm以上的多層膜,例如藉由濺射法、離子電鍍法、噴霧塗佈法、CVD(chemical Vapor Deposition)法、噴墨法、網板印刷法來形成。另外,電磁波屏蔽層16是亦可藉由在真空環境下將具有上述的多層膜之金屬薄膜附著於封裝21的上面22及側面23的真空層壓來形成。 [0032] 此時,封裝21的側面23是以從上面22朝下方擴大至外側的方式傾斜,封裝21的側面23的斜面會對於電磁波屏蔽層16的成膜方向(鉛直方向)傾斜地交叉。因此,由上方來將電磁波屏蔽層16成膜於封裝21時,不僅封裝21的上面22,在側面23也可容易以能夠發揮充分的屏蔽效果的程度的厚度來形成電磁波屏蔽層16。如此,製造一種封裝21的上面22及側面23會被電磁波屏蔽層16所覆蓋的半導體封裝10。 [0033] 由於電磁波屏蔽層16被連接至接地線17,因此在半導體封裝10所產生的電磁雜訊會通過接地線17來脫逃至半導體封裝10外。另外,封裝21的側面23的下端側是被形成鉛直,因此無法與斜面同樣地成膜。然而,由於電磁雜訊會藉由被設在配線基板11的多數的配線來截斷,所以即使封裝21的側面23的鉛直部分的電磁波屏蔽層16被薄薄地形成,也可充分地遮蔽電磁雜訊。因此,朝半導體封裝10的周圍的電子零件之電磁雜訊的洩漏會被有效地防止。 [0034] 另外,在第1實施形態的半導體封裝的製造方法中,V溝形成工程、小片化工程是亦可被實施於同一的切削裝置。並且,在製造無凸塊14的半導體封裝時是亦可省略凸塊形成工程。而且,在密封基板15被預先準備時,亦可省略晶片接合工程、密封基板作成工程。 [0035] 如以上般,若根據第1實施形態的半導體封裝的製造方法,則藉由以V刀刃39來從樹脂層13側切削密封基板15,被小片化的封裝21的側面23會以從樹脂層13側朝下方擴大至外側的方式傾斜。由於上面視封裝21的側面23具有投影面積,所以可容易從與封裝21的上面22垂直的方向來對於封裝21的側面23形成電磁波屏蔽層16。因此,可有效率地在半導體封裝10的上面22及側面23以能夠發揮充分的屏蔽效果之預定的厚度來形成電磁波屏蔽層16。 [0036] 在此,密封基板15是在V刀刃39的消耗劇烈的配線基板11上層疊V刀刃39的消耗少的樹脂層13來形成。為此,在第1實施形態的半導體封裝的製造方法中,於V溝形成工程,配線基板11與樹脂層13的異種材料會同時被切削,因此V刀刃39的消耗量或前端的V字形狀的角度管理難。於是,在第2實施形態中,在密封基板15的作成前形成避免配線基板11與V刀刃39的接觸之逃避溝而以樹脂填埋,藉此在V溝形成時V刀刃39只切削樹脂。 [0037] 以下,參照圖5及圖6來說明有關第2實施形態的半導體封裝的製造方法。圖5A是配線基板溝形成工程,圖5B是晶片接合工程,圖5C是密封基板作成工程,圖5D是凸塊形成工程,分別表示各一例的圖。圖6A是V溝形成工程,圖6B是小片化工程,圖6C是屏蔽層形成工程,分別表示各一例的圖。另外,有關與第1實施形態的半導體封裝的製造方法同樣的構成是簡略化說明。 [0038] 如圖5A所示般,首先配線基板溝形成工程會被實施。在配線基板溝形成工程中,至配線基板11的厚度方向途中的深度,例如切斷接地線17的深度的溝27會沿著分割預定線來形成。此情況,配線基板11的背面側會被吸引保持於溝形成用的保持治具56,在配線基板11的外側,切削刀刃59會被對位於配線基板11的分割預定線。切削刀刃59是以結合劑來固定鑽石砥粒等而被成形為圓板狀,安裝於主軸(未圖示)的前端。另外,因切削配線基板11,切削刀刃59會消耗,但與V刀刃39不同,切削刀刃59的側面形狀的變化少,因此可形成一定的溝寬。 [0039] 在配線基板11的外側,切削刀刃59會下降至配線基板11的厚度方向途中的深度為止,相對於此切削刀刃59,配線基板11會被切削進給於水平方向。一旦沿著一條的分割預定線來半切配線基板11,則切削刀刃59會對位於旁邊的分割預定線來半切配線基板11。藉由重複此切斷動作,在配線基板11形成沿著分割預定線的溝27。藉此,用以在後段的V溝形成工程避免配線基板11與V刀刃39(參照圖6A)的接觸之逃避溝會沿著分割預定線來形成。 [0040] 如圖5B所示般,配線基板溝形成工程被實施後,晶片接合工程會被實施。在晶片接合工程中,在以沿著分割預定線的溝27所區劃的各領域配置有半導體晶片12。而且,接線19的一端會被連接至半導體晶片12的上面的電極,接線19的另一端會被連接至配線基板11的表面的電極18,複數的半導體晶片12會被打線接合於配線基板11。另外,在晶片接合工程中,不限於打線接合,亦可實施將半導體晶片12的下面的電極直接連接至配線基板11的表面的電極之覆晶接合。 [0041] 如圖5C所示般,晶片接合工程被實施後,密封基板作成工程會被實施。在密封基板作成工程中,對於密封用的保持治具31上的配線基板11,經由框架32的注入口33來從供給噴嘴34供給密封劑24,半導體晶片12會被密封劑24密封,且密封劑24會被充填於配線基板11的溝27內。在此狀態下,密封劑24會藉由加熱或乾燥來硬化,作成在配線基板11的上面形成有樹脂層13(參照圖5D)的密封基板15。另外,在密封基板作成工程之後,以研削來使樹脂層平坦化的平坦化工程亦可被實施。 [0042] 如圖5D所示般,密封基板作成工程被實施後,凸塊形成工程會被實施。在凸塊形成工程中,密封基板15會被表背反轉,密封基板15的樹脂層13側會以凸塊形成用的保持治具41來吸引保持。而且,密封基板15的配線基板11的背面側會被露出於上方,在配線基板11的背面配設有凸塊14。凸塊14是形成將半導體封裝10安裝於各種基板時的端子或電極,被形成於對應於配線基板11的配線圖案之預定位置。由於在密封基板15的小片化前形成凸塊14,因此凸塊14對於密封基板15的位移會被防止。 [0043] 如圖6A所示般,凸塊形成工程被實施後,V溝形成工程會被實施。在V溝形成工程中,密封基板15的配線基板11側會被保持於V溝形成用的保持治具61,以V刀刃39來從樹脂層13側切入至配線基板11(密封基板15)的厚度方向途中,沿著分割預定線(溝27)來形成V溝25。此情況,在保持治具61的保持面62是形成有收容凸塊14的凹部63,在相鄰的凹部63之間形成有對應於分割預定線的逃避溝64。凹部63內是經由吸引路來連接至吸引源,藉由在凹部63產生的負壓,密封基板15會被吸引保持於保持治具61的保持面62。 [0044] 並且,V刀刃39會在密封基板15的外側被對位於分割預定線,相對於V刀刃39,密封基板15會被切削進給於水平方向。此時,V刀刃39的前端會進入至配線基板11的溝27內,可避免V刀刃39與配線基板11的接觸。由於僅樹脂層13藉由V刀刃39來切削,因此V刀刃39的消耗會被抑制,使整形琢磨時間延遲,可拉長刀刃壽命。另外,V刀刃39的前端是只要可對於密封基板15形成V溝25的形狀即可,如圖3D所示般,切削刀刃40的前端亦可被形成平坦的V字形狀。 [0045] 如圖6B所示般,V溝形成工程被實施後,小片化工程會被實施。在小片化工程中,在密封基板15的配線基板11側被保持於保持治具61的狀態下,以切削刀刃49來全切密封基板15,密封基板15會沿著分割預定線來分割成各個的封裝21。此時,由於切削刀刃49的前端會進入至保持治具61的逃避溝64,因此切削刀刃49與保持治具61的干擾會被防止。另外,雖切削刀刃49會因切削配線基板11而消耗,但與V刀刃39不同,切削刀刃49的側面形狀的變化少,所以可鉛直地形成切剖面。 [0046] 如圖6C所示般,小片化工程被實施後,屏蔽層形成工程會被實施。在屏蔽層形成工程中,按屏蔽用的保持治具51的每個凹部53配置封裝21,對於封裝21從上方形成導電性材料膜,在封裝21的上面22及側面23形成電磁波屏蔽層16。電磁波屏蔽層16是藉由銅、鈦、鎳、金等的其中一個以上的金屬來成膜之厚度數μm以上的多層膜,例如亦可藉由濺射法、離子電鍍法、噴霧塗佈法、CVD(chemical Vapor Deposition)法、噴墨法、網板印刷法、真空層壓法來形成。 [0047] 此時,由於封裝21的側面23會以從上面22朝下方擴大至外側的方式傾斜,因此不僅封裝21的上面22,在側面23也容易以所望的厚度形成電磁波屏蔽層16。如此,製造一種封裝21的上面22及側面23會被電磁波屏蔽層16所覆蓋的半導體封裝10。由於電磁波屏蔽層16被連接至接地線17,所以在半導體封裝10產生的電磁雜訊會通過接地線17來脫逃至半導體封裝10外。因此,朝半導體封裝10的周圍的電子零件之電磁雜訊的洩漏會被有效地防止。 [0048] 另外,第2實施形態是形成在晶片接合工程前實施配線基板溝形成工程的構成,但並非限於此構成。配線基板溝形成工程是只要在密封基板作成工程之前被實施即可,亦可在晶片接合工程與密封基板作成工程之間被實施。而且,在第2實施形態中,亦可與第1實施形態同樣,在V溝形成工程與小片化工程之間實施凸塊形成工程。藉由在V溝形成後形成凸塊14,在V溝形成工程及小片化工程的保持治具61不需要用以使凸塊14逃避之凹部63,可使用既存的保持治具。 [0049] 如以上般,若根據第2實施形態的半導體封裝的製造方法,則與第1實施形態同樣,可有效率地在半導體封裝10的上面22及側面23以能夠發揮充分的屏蔽效果之預定的厚度來形成電磁波屏蔽層16。又,由於僅樹脂層13藉由V刀刃39來切削,因此可抑制V刀刃39的消耗來拉長刀刃壽命。 [0050] 接著,說明有關半導體封裝的側面的傾斜角度與電磁波屏蔽層的關係。圖7是表示設在試驗體的電磁波屏蔽層的厚度的圖。圖8是表示試驗體的側面的傾斜角與電磁波屏蔽層的厚度的關係的圖。 [0051] 如圖7所示般,準備改變側面82的傾斜角度θ的複數的試驗體80,在180℃、8×10-4
Pa的條件下,藉由離子電鍍法來形成屏蔽層。側面82的傾斜角度θ是設為90°、82°、68°、60°、45°。並且,分成被形成於上面81的上部屏蔽層83、被形成於側面82的側部屏蔽層84,根據掃描型電子顯微鏡的觀察畫像來測定上部屏蔽層83、側部屏蔽層84的厚度t1、t2。上部屏蔽層83及側部屏蔽層84的厚度t1、t2是作為次式(1)所示的階梯覆蓋(step coverage)的值算出,將此值與傾斜角度θ的關係彙整於圖8。 step coverage=(t2/t1)×100 ---(1) [0052] 此結果,隨著傾斜角度θ從90°變小,階梯覆蓋的值會慢慢地變大,一旦傾斜角度θ形成45°,則階梯覆蓋的值會形成100%。具體而言,當傾斜角度θ設定成為45°時,上部屏蔽層83的厚度t1與側部屏蔽層84的厚度t2會一致,在試驗體80的上面22及側面23被確認均一的厚度的電磁波屏蔽層16。又,根據發明者的實驗,一但階梯覆蓋的值低於50%,則在側部屏蔽層84的成膜需要時間,製程成本會增大,因此階梯覆蓋的值成為50%以上的範圍為理想。所以,半導體封裝的側面的傾斜角度θ是45°以上且82°以下為理想,V刀刃39的前端的角度是90°以上且36°以下為理想。 [0053] 另外,在第1、第2實施形態中,舉例顯示在配線基板安裝了1個的半導體晶片的半導體封裝,但並非限於此構成。亦可製造在配線基板安裝了複數的半導體晶片的半導體封裝。例如圖9A所示般,亦可在配線基板91安裝複數(例如3個)的半導體晶片92a、92b、92c,製造一起屏蔽半導體晶片92a、92b、92c的半導體封裝90。此情況,在V溝形成工程中以封裝單位在密封基板95形成V溝,在小片化工程中以封裝單位分割密封基板95。另外,半導體晶片92a、92b、92c是亦可具有同一機能或不同的機能。 [0054] 又,如圖9B所示般,亦可在配線基板101安裝複數(例如2個)的半導體晶片102a、102b,製造個別地屏蔽半導體晶片102a、102b的半導體封裝(SIP)100。此情況,在V溝形成工程中以半導體晶片單位在密封基板105形成V溝106,在小片化工程中以封裝單位分割密封基板105。藉此,在半導體晶片102a、102b之間形成電磁波屏蔽層107,可在半導體晶片102a、102b的相互間防止電磁雜訊的影響。另外,半導體晶片102a、102b是亦可具有同一機能或不同的機能。 [0055] 並且,在上述的第1、第2實施形態中,V溝形成工程是使用V刀刃作為加工工具來實施,但並非限於此構成。V溝形成工程是只要對於密封基板從樹脂層側朝溝底形成V溝的構成即可。例如圖10A所示般,亦可使用通常的切削刀刃108作為加工工具,在密封基板15形成V溝。此情況,對於密封基板15的分割預定線上的鉛直面P僅預定角度將切削刀刃108傾斜至一方側而切削後,對於鉛直面P僅預定角度將切削刀刃108傾斜至另一方側而切削。藉此,密封基板15的上面會藉由切削刀刃108來切去成V狀,沿著分割預定線來形成V溝。 [0056] 又,如圖10B所示般,亦可使用雷射燒蝕用的加工頭109作為加工工具,在密封基板15形成V溝25。此情況,對於密封基板15的分割預定線上的鉛直面P僅預定角度將加工頭109傾斜至一方向來實施燒蝕加工後,對於鉛直面P僅預定角度將加工頭109傾斜至另一方側來實施燒蝕加工。藉由對於密封基板15具有吸收性的雷射光線來將密封基板15的上面切去成V字狀,沿著分割預定線來形成V溝。另外,所謂雷射燒蝕是意指一旦雷射光線的照射強度形成預定的加工臨界值以上,則在固體表面被變換成電子、熱性、光學性及力學性的能量,其結果,中性原子、分子、正負的離子、自由基、集合體、電子、光會被爆發性地放出,固體表面被蝕刻的現象。 [0057] 又,如圖10C所示般,亦可使用靠模銑床115作為加工工具,在密封基板16形成V溝25。靠模銑床115是在鋁基台116的大致V字狀的加工面電沈積由鑽石砥粒所成的砥粒層117來構成。靠模銑床115是比V刀刃39難消耗,可長期持續維持V字形狀。 [0058] 並且,在上述的第1、第2實施形態中,小片化工程是利用切削刀刃來實施,但並非限於此構成。小片化工程是只要將密封基板分割成各個的封裝的構成即可,例如亦可藉由燒蝕加工來將密封基板分割成各個的封裝。 [0059] 而且,在上述的第1、第2實施形態中,形成配線基板被保持於各保持治具來實施各工程的構成,但並非限於此構成。例如,亦可在配線基板的背面貼附保護膠帶,經由膠帶來將配線基板載置於基台等上的狀態下實施各工程。並且,保持治具是只要能保持基板即可,例如,亦可適當使用具有多孔製的保持面的吸盤平台。 [0060] 半導體封裝是不限於使用在行動電話等的攜帶型通訊機器的構成,亦可使用在照相機等的其他的電子機器。 [0061] 並且,在上述的第1、第2實施形態及變形例中,說明有關製造半導體晶片會經由接線來被打線接合於配線基板的電極之半導體封裝的構成,但不限於此構成。如圖11所示般,半導體封裝10是亦可半導體晶片12被直接連接至配線基板11的電極來覆晶接合。 [0062] 說明了本實施形態及變形例,但亦可將上述各實施形態及變形例全體或部分地組合,作為本發明的其他的實施形態。 [0063] 又,本發明的實施形態並非限於上述的各實施形態及變形例,亦可在不脫離本發明的技術思想的主旨範圍中實施各種變更、置換、變形。又,只要能藉由技術的進步或衍生的別的技術,以別的方法來實現本發明的技術思想,亦可使用該方法來實施。因此,申請專利範圍是涵蓋本發明的技術思想的範圍內所能含的全部的實施形態。 [0064] 並且,在本實施形態中,說明有關將本發明適用於半導體封裝的製造方法的構成,但亦可適用在形成有預定的膜厚的屏蔽層之其他的封裝零件的製造方法。 [0065] 如以上說明般,本發明是具有可有效率地對於側面形成預定的膜厚的屏蔽層之效果,特別是被使用在攜帶型通訊機器的半導體封裝的製造方法有用。
[0066]10‧‧‧半導體封裝11‧‧‧配線基板12‧‧‧半導體晶片13‧‧‧樹脂層(密封劑)14‧‧‧凸塊15‧‧‧密封基板16‧‧‧電磁波屏蔽層21‧‧‧封裝22‧‧‧封裝的上面23‧‧‧封裝的側面25‧‧‧密封基板的V溝26‧‧‧V溝的加工溝底27‧‧‧配線基板的溝36‧‧‧保持治具39‧‧‧V刀刃(加工工具)
[0011] 圖1是本實施形態的半導體封裝的模式性剖面圖。 圖2是表示比較例的半導體封裝的製造方法的模式性剖面圖。 圖3是表示第1實施形態的半導體封裝的製造方法的模式性剖面圖。 圖4是表示第1實施形態的半導體封裝的製造方法的模式性剖面圖。 圖5是表示第2實施形態的半導體封裝的製造方法的模式性剖面圖。 圖6是表示第2實施形態的半導體封裝的製造方法的模式性剖面圖。 圖7是表示設在試驗體的電磁波屏蔽層的厚度的圖。 圖8是表示試驗體的側面的傾斜角與電磁波屏蔽層的厚度的關係的圖表。 圖9是表示半導體封裝的變形例的模式性剖面圖。 圖10是表示V溝形成工程的變形例的模式性剖面圖。 圖11是表示半導體封裝的變形例的模式性剖面圖。
10‧‧‧半導體封裝
11‧‧‧配線基板
12‧‧‧半導體晶片
13‧‧‧樹脂層(密封劑)
14‧‧‧凸塊
15‧‧‧密封基板
16‧‧‧電磁波屏蔽層
17‧‧‧接地線
21‧‧‧封裝
22‧‧‧封裝的上面
23‧‧‧封裝的側面
25‧‧‧密封基板的V溝
46‧‧‧治具
47‧‧‧保持面
49‧‧‧切削刀刃
41、51‧‧‧保持治具
52‧‧‧保持面
53‧‧‧凹部
Claims (2)
- 一種半導體封裝的製造方法,係製造藉由密封劑來密封的半導體封裝之半導體封裝的製造方法,其特徵係具備:晶片接合工程,其係將複數的半導體晶片接合於藉由交叉的複數的分割預定線來區劃的配線基板表面上的複數領域;密封基板作成工程,其係於接合有該複數的半導體晶片的該配線基板的表面側供給密封劑而密封,作成密封基板;V溝形成工程,其係於實施該密封基板形成工程之後,以保持治具來保持該密封基板的該配線基板側,將加工工具從該密封劑側切入至該密封基板的厚度方向途中,沿著對應於該分割預定線的領域來加工,以具備從該密封劑上面朝加工溝底傾斜的側面之方式形成V溝;小片化工程,其係於實施該V溝形成工程之後,沿著該V溝來分割該配線基板,沿著該分割預定線來小片化成各個的封裝;及屏蔽層形成工程,其係於實施該小片化工程之後,在複數的該封裝的該密封劑上面及傾斜的側面形成電磁波屏蔽層,在該V溝形成工程與該小片化工程之間更具備凸塊形成工程,其係於該配線基板的背面側形成凸塊, 在該小片化工程中,以保持治具來吸引保持該密封基板的該密封劑側。
- 一種半導體封裝的製造方法,係製造藉由密封劑來密封的半導體封裝之半導體封裝的製造方法,其特徵係具備:晶片接合工程,其係將複數的半導體晶片接合於藉由交叉的複數的分割預定線來區劃的配線基板表面上的複數領域;密封基板作成工程,其係於接合有該複數的半導體晶片的該配線基板的表面側供給密封劑而密封,作成密封基板;V溝形成工程,其係於實施該密封基板形成工程之後,以保持治具來保持該密封基板的該配線基板側,將加工工具從該密封劑側切入至該密封基板的厚度方向途中,沿著對應於該分割預定線的領域來加工,以具備從該密封劑上面朝加工溝底傾斜的側面之方式形成V溝;小片化工程,其係於實施該V溝形成工程之後,沿著該V溝來分割該配線基板,沿著該分割預定線來小片化成各個的封裝;及屏蔽層形成工程,其係於實施該小片化工程之後,在複數的該封裝的該密封劑上面及傾斜的側面形成電磁波屏蔽層,在實施該密封基板作成工程之前,更具備配線基板溝 形成工程,其係沿著該分割預定線來形成至該配線基板的厚度方向途中的深度的溝,在該密封基板形成工程中,使該密封劑充填於該溝內而形成該密封基板,在該V溝形成工程中,該加工工具係加工該密封劑來形成V溝。
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