CN107546193A - 积体扇出型封装体 - Google Patents

积体扇出型封装体 Download PDF

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Publication number
CN107546193A
CN107546193A CN201611038412.XA CN201611038412A CN107546193A CN 107546193 A CN107546193 A CN 107546193A CN 201611038412 A CN201611038412 A CN 201611038412A CN 107546193 A CN107546193 A CN 107546193A
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China
Prior art keywords
storage component
integrated circuit
component part
line structure
conducting
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Pending
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CN201611038412.XA
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English (en)
Inventor
余振华
余国宠
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN107546193A publication Critical patent/CN107546193A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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Abstract

一种积体扇出型封装体，其包括集成电路、多个存储器器件、绝缘封装体以及重布线路结构。存储器器件与集成电路电性连接。集成电路与存储器器件相互堆叠，且存储器器件嵌于绝缘封装体中。重布线路结构配置于绝缘封装体上，且重布线路结构与集成电路以及存储器器件电性连接。此外，上述积体扇出型封装体的制造方法亦被提出。

Description

积体扇出型封装体
技术领域
本发明一实施例是有关于一种积体扇出型封装体。
背景技术
由于不同电子器件(例如是晶体管、二极管、电阻、电容等)的积体密度持续地增进，半导体工业经历了快速成长。大部分而言，积集度的增进是来自于最小特征尺寸(feature size)上不断地缩减，这允许更多的较小器件能够被整合到一预定区域内。较小的电子器件会需要比以往体积更小的封装。较小型的半导体器件封装包括有四面扁平封装(quad flat packages，QFPs)、接脚栅格阵列(pin grid array，PGA)封装、球状栅格阵列(ball grid array，BGA)封装等等。
近来，由于积体扇出型封装体的高积集度(compactness)，积体扇出型封装体提供了低功率消耗、高效能、较小的封装体积以及较具竞争性的制造成本，因此积体扇出型封装体已逐渐成为主流。如何增进积体扇出型封装体的效能，且特别是在高密度、高功率方面的应用上，是相当重要的焦点。
发明内容
依据本发明的一些实施例，积体扇出型封装体包括集成电路、多个存储器器件、绝缘封装体以及重布线路结构。存储器器件与集成电路电性连接。集成电路与存储器器件相互堆叠，且存储器器件嵌于绝缘封装体中。重布线路结构配置于绝缘封装体上，且重布线路结构与集成电路以及存储器器件电性连接。
附图说明
包含附图以便进一步理解本发明，且附图并入本说明书中并构成本说明书的一部分。附图说明本发明的实施例，并与描述一起用于解释本发明的原理。
图1至图8为依照一些实施例所绘示的一种积体扇出型封装体的制造流程剖视图。
图9为依照一些其他实施例所绘示的积体扇出型封装体的剖视图。
图10至图17为依照一些实施例所绘示的另一种积体扇出型封装体的制造流程剖视图。
图18以及图19为依照一些其他实施例所绘示的积体扇出型封装体的剖视图。
图20至图27为依照一些实施例所绘示的另一种积体扇出型封装体的制造流程剖视图。
图28为依照一些其他实施例所绘示的积体扇出型封装体的剖视图。
具体实施方式
以下揭露内容提供用于实施所提供的目标之不同特征的许多不同实施例或实例。以下所描述的构件及配置的具体实例是为了以简化的方式传达本发明为目的。当然，这些仅仅为实例而非用以限制。举例来说，于以下描述中，在第一特征上方或在第一特征上形成第二特征可包括第二特征与第一特征形成为直接接触的实施例，且亦可包括第二特征与第一特征之间可形成有额外特征使得第二特征与第一特征可不直接接触的实施例。此外，本发明在各种实例中可使用相同的器件符号及/或字母来指代相同或类似的部件。器件符号的重复使用是为了简单及清楚起见，且并不表示所欲讨论的各个实施例及/或配置本身之间的关系。
另外，为了易于描述附图中所绘示的一个构件或特征与另一器件或特征的关系，本文中可使用例如「在…下」、「在…下方」、「下部」、「在…上」、「在…上方」、「上部」及类似术语的空间相对术语。除了附图中所绘示的定向之外，所述空间相对术语意欲涵盖器件在使用或操作时的不同定向。设备可被另外定向(旋转90度或在其他定向)，而本文所用的空间相对术语相应地做出解释。
图1至图8为依照一些实施例所绘示的一种积体扇出型封装体的制造流程剖视图。请参照图1，提供一晶片(wafer)W，其包括阵列排列的多个集成电路110。在一些实施例中，集成电路110可为系统级芯片(System on Chip,SOC)集成电路。在对晶片W进行晶片切割工艺之前，晶片W中的集成电路110是相互连接的，如图1所绘示。在一些实施例中，晶片W包括半导体衬底SUB以及多个形成在半导体衬底SUB上的导电接垫PAD。举例而言，半导体衬底SUB可为包括有有源器件(例如晶体管或其他类似器件)以及(例如电阻器、电容器、电感器或其他类似器件)形成在其上的硅衬底；并且，导电接垫PAD可为铝接垫、铜接垫或其他合适的金属接垫。
在一些实施例中，晶片W可选择性地包括至少一形成在半导体衬底SUB上的钝化层(未绘示)。钝化层可包括多个接触开口，且导电接垫PAD被钝化层的接触开口所暴露。在一些实施例中，钝化层的材质例如为聚酰亚胺(polyimide，PI)、聚苯恶唑(polybenzoxazole，PBO)或其他适合的聚合物或有机材料。
请参照图2，于晶片W上形成多个导电柱体120，以使导电柱体120与集成电路110接触并且热耦接至集成电路110。各个集成电路110可包括有源表面110a以及与有源表面110a相对的背面110b。部分的导电柱体120与集成电路110的有源表面110a接触并且热耦接至集成电路110的有源表面110a，而其余的导电柱体120则与集成电路110的导电接垫PAD电性连接。换句话说，部分的导电柱体120为热传导柱体，用以传导由集成电路110所产生的热，而其余的导电柱体120与集成电路110的导电接垫PAD电性连接，用以传输及接收信号。在一些其他实施例中，所有的导电柱体120皆与集成电路110的导电接垫PAD电性连接，用以传输及接收信号。
在一些实施例中，导电柱体120是镀覆(plate)在集成电路110上。用以制造导电柱体120的镀覆工艺将于后进行详细的描述。首先，通过溅射(sputter)工艺在晶片W上形成种子层(seed layer)。接着，通过微影工艺在种子层上形成图案化光刻胶层(未绘示)，其中对应于导电柱体120所在位置的种子层会被图案化光刻胶层所暴露。包括有图案化光刻胶层形成在其上的晶片W会被浸入镀覆槽(plating bath)内的镀覆溶液，以使得导电柱体120被镀覆在种子层被暴露的部分上。在镀覆形成导电柱体120之后，将图案化光刻胶层剥除。之后，以导电柱体120为掩模，通过蚀刻工艺将未被导电柱体120所覆盖的部分种子层移除，直到集成电路110的有源表面110a被暴露为止。上述用以制造导电柱体120的镀覆工艺仅是示例说明。然而，本发明不限于此。
请参照图3，在晶片W上形成多个存储器器件体130，以使存储器器件130与集成电路110接触并且电性连接。存储器器件130例如是通过覆晶接合(flip-chip bonding)工艺以及底填(under-fill)工艺而设置在晶片W上。在一些实施例中，各个存储器器件130包括多个相互堆叠的存储器芯片132以及至少一个控制器134。各个存储器芯片132包括多个微凸块132a，且部分的存储器芯片132包括多个导通孔132b(例如贯穿硅基材的导电通孔，TSV)。控制器134包括多个微凸块134a以及多个与微凸块134a电性连接的导通孔134b(例如贯穿硅基材的导电通孔，TSV)。通过微凸块132a、导通孔132b以及导通孔134b，存储器芯片132可与控制器134电性连接。通过控制器134的微凸块134a，存储器器件130能够与晶片W中的集成电路110电性连接。如图3所示，位在最上方的存储器芯片132中不需制作导电通孔。
如图3所示，存储器器件130例如为多个高带宽存储器堆叠结构(high bandwidthmemory cubes)。然而，前述高带宽存储器堆叠结构仅为示例之用，然本发明不以此为限。
在一些实施例中，导电柱体120的高度可与存储器器件130的厚度实质上相同。在一些其他实施例中，导电柱体120的高度可大于存储器器件130的厚度。
如图2与图3所示，导电柱体120是在将存储器器件130设置在晶片W上之前形成。然而，本发明不限于此。在一些其他实施例中，导电柱体120可在将存储器器件130设置在晶片W上之后形成。
请参照图4，在晶片W形成绝缘封装体140以包覆存储器器件130以及导电柱体120，进而使得集成电路110、导电柱体120以及存储器器件130可被嵌于绝缘封装体140中。在一些实施例中，绝缘封装体140可为模塑工艺所形成的封装胶体。绝缘封装体140的材料包括环氧化合物(epoxy)或其他合适的介电材料。
绝缘封装体140可通过包覆型模塑工艺(over mold)以及抛光工艺(grinding)形成。在一些实施例中，可通过包覆型模塑工艺在晶片W上形成绝缘材料以全面性覆盖导电柱体120以及存储器器件130，接着，绝缘材料可通过机械抛光工艺及/或化学机械抛光工艺进行抛光，直到全部导电柱体120的顶表面以及存储器器件130的顶表面被暴露为止。在一些实施例中，导电柱体120的顶表面以及存储器器件130的顶表面实质上同平面(在同一水平高度上)。
请参照图5，在绝缘封装体140形成之后，在绝缘封装体140的顶表面、导电柱体120的顶表面以及存储器器件130的顶表面上形成重布线路结构150。在一些实施例中，重布线路结构150热耦接至跟集成电路110的有源表面110a热耦接的部分导电柱体120，且重布线路结构150电性连接至跟集成电路110的导电接垫PAD电性连接的其余导电柱体120。当部分导电柱体120用以作为热传导柱体时，重布线路结构150可包括多个与热传导柱体120热耦接的导热通孔。通过重布线路结构150中的热传导柱体120以及导热通孔，集成电路110所产生的热可被有效率地传导与逸散。
在一些实施例中，重布线路结构150与全部的导电柱体120电性连接。虽然全部的导电柱体120皆是用以传送及接收信号，导电柱体120仍能够传导集成电路110产生的热。当全部的导电柱体120皆用以作为信号传导柱体时，重布线路结构150亦可包括多个与信号传导柱体120热耦接的导热通孔。通过重布线路结构150中的导电柱体120以及导热通孔，集成电路110所产生的热可被有效率地传导与逸散。
如图5所示，重布线路结构150通过导电柱体120而与集成电路110以及存储器器件130电性连接。在一些实施例中，重布线路结构150通过导电柱体120以及集成电路110的线路层而与存储器器件130电性连接。
请参照图6，在重布线路结构150形成之后，接着形成多个与重布线路结构150电性连接的导电端子160。重布线路结构150位在导电端子160以及存储器器件130之间。换言之，导电端子160分布在重布线路结构150的一侧，而集成电路110、导电柱体120以及存储器器件130分布在重布线路结构150的另一侧。在一些实施例中，导电端子160可为导电凸块(conductive bumps)或导电球(conductive balls)。
请参照图6与图7，沿着切割线SL进行晶片切割工艺以将图6中所绘示的结构单体化，进而形成多个单体化的封装体100。在晶片切割工艺进行的期间，重布线路结构150、绝缘封装体140以及晶片W会被切割以形成多个单体化的积体扇出型封装体100。
如图7所示，单体化的积体扇出型封装体100包括集成电路110、存储器器件130、绝缘封装体140以及重布线路结构150。存储器器件130与集成电路110电性连接。集成电路110与存储器器件130相互堆叠，且存储器器件130嵌于绝缘封装体140中。重布线路结构150配置在绝缘封装体140上，且重布线路结构150与集成电路110以及存储器器件130电性连接。在一些实施例中，可选择性地形成导电端子160。
如图7所示，积体扇出型封装体100中的集成电路110未嵌于绝缘封装体140中，且存储器器件130配置在重布线路结构150以及集成电路110之间。
请参照图8，在单体化的积体扇出型封装体100形成之后，可将其中一个单体化的积体扇出型封装体100拾取并设置在封装线路衬底170上。单体化的积体扇出型封装体100中的重布线路结构150通过导电端子160与封装线路衬底170电性连接。在一些实施例中，封装线路衬底170可包括多个分布在其底表面上的导电球172。举例而言，导电球172可为焊料球或其他金属球。值得注意的是，导电端子160的排列间距例如小于导电球172的排列间距。换句话说，具有导电球172排列在其上的封装线路衬底170可为球格阵列线路板，且球格阵列封装体100a包括单体化的积体扇出型封装体100以及封装线路衬底170。
如图8所示，为了增进导电端子160的接合可靠度，可在重布线路结构150与封装线路衬底170之间填入底填层180。底填层180包覆导电端子160以确保导电端子160的结构完整度，且由于重布线路结构150与封装线路衬底170之间的热膨胀系数差异，底填层180可确保其与重布线路结构150与封装线路衬底170之间的接合介面(interface)。换句话说，热膨胀系数差异所导致的剪应力可被底填层180所吸收，且导电端子160可被底填层180保护。
在一些实施例中，为了进一步增进散热能力，可将散热器190黏贴在集成电路100的背面100b上。举例而言，散热器190的材料包括铝或其他适合的金属材料。
图9为依照一些其他实施例所绘示的积体扇出型封装体的剖视图。请参照图9，本实施例未使用高带宽存储器堆叠结构(HBM cubes)，而是使用与存储器器件130(绘示于图3中)不同架构的存储器器件130a。值得注意的是，本发明的实施例不限定存储器器件130a的数量。
图10至图17为依照一些实施例所绘示的另一种积体扇出型封装体的制造流程剖视图。
请参照图10，提供具有剥离层DB形成在其上的载板C。在一些实施例中，载板C例如是玻璃衬底，而剥离层DB例如是形成在玻璃衬底上的光热转换释放层(LTHC releaselayer)。然而，本发明的实施例不限定载板C与剥离层DB的材质。
在提供具有剥离层DB的载板C之后，可通过黏着层AD将多个存储器器件130设置在剥离层DB以及载板C上。举例而言，晶粒贴附工艺中所使用的晶粒贴附薄膜(DieAttachment Film，DAF)可用以作为黏着层AD。在一些实施例中，各个存储器器件130包括多个相互堆叠的存储器芯片132以及至少一个控制器134。各个存储器芯片132包括多个微凸块132a，且部分的存储器芯片132包括多个导通孔132b(例如贯穿硅基材的导电通孔，TSV)。控制器134包括多个与存储器芯片132的微凸块132a电性连接的导电通孔134b。通过微凸块132a、导通孔132b以及导通孔134b，存储器芯片132可与控制器134电性连接。如图10所示，位在最下方的存储器芯片132中不需制作导电通孔，且控制器134堆叠在存储器芯片132下方。
如图10所示，存储器器件130例如为多个高带宽存储器堆叠结构(high bandwidthmemory cubes)。然而，前述高带宽存储器堆叠结构仅为示例之用，然本发明不以此为限。
请参照图11，将第一绝缘部分140a形成在剥离层DB以及载板C上以包覆存储器器件130的侧壁，进而使得存储器器件130嵌于第一绝缘部分140a中。在一些实施例中，第一绝缘部分140a可为模塑工艺所形成的封装胶体。第一绝缘部分140a的材料包括环氧化合物(epoxy)或其他合适的介电材料。
第一绝缘部分140a可通过包覆型模塑工艺(over mold)以及抛光工艺(grinding)形成。在一些实施例中，可通过包覆型模塑工艺在剥离层DB以及载板C上形成绝缘材料以全面性覆盖存储器器件130，接着，绝缘材料可通过机械抛光工艺及/或化学机械抛光工艺进行抛光，直到存储器器件130的顶表面被暴露为止。
请参照图12，在存储器器件130及/或第一绝缘部分140a上形成多个导电柱体120。在一些实施例中，在形成导电柱体120之前，可在存储器器件130的顶表面及/或第一绝缘部分140a的顶表面上形成重布线层RDL。导电柱体120例如是通过重布线层RDL而与存储器器件130电性连接。
在一些实施例中，导电柱体120是通过镀覆工艺所形成。导电柱体120的镀覆工艺将于后进行详细的描述。首先，通过溅射在存储器器件130的顶表面上以及第一绝缘部分140a的顶表面上形成种子层。接着，通过微影工艺在种子层上形成图案化光刻胶层(未绘示)，其中对应于导电柱体120所在位置的种子层被图案化光刻胶层所暴露。接着，进行镀覆工艺以在种子层被暴露出的部分上形成导电柱体120。在镀覆形成导电柱体120之后，将图案化光刻胶层剥除。之后，以导电柱体120为掩模，通过蚀刻将未被导电柱体120所覆盖的部分种子层移除，直到存储器器件130的顶表面以及第一绝缘部分140a的顶表面被暴露为止。上述用以制造导电柱体120的镀覆工艺仅是示例说明。然而，本发明不限于此。
请参照图13，在形成导电柱体120之后，将集成电路110拾取并设置在存储器器件130以及第一绝缘部分140a上。集成电路110例如是通过覆晶接合(flip-chip bonding)工艺以及底填(under-fill)工艺而设置在存储器器件130上。集成电路110包括有源表面110a、与有源表面110a相对的背面110b，集成电路110的有源表面110a朝向存储器器件130设置，且集成电路110通过多个位在有源表面110a与存储器器件130之间的凸块112与存储器器件130电性连接。在一些实施例中，集成电路110通过位在集成电路110与存储器器件130之间的重布线层RDL与存储器器件130电性连接。在一些其他实施例中，集成电路110可与存储器器件130直接电性连接，且集成电路110可透过重布线层RDL与导电柱体120直接电性连接。集成电路110、导电柱体120以及存储器器件130之间的电性连接方式可依据不同设计需求更动，然本发明的实施例不限于此。
请参照图14，在第一绝缘部分140a上形成第二绝缘部分140b以包覆集成电路110以及导电柱体120。在一些实施例中，第二绝缘部分140b可为模塑工艺所形成的封装胶体。第二绝缘部分140b的材料包括环氧化合物(epoxy)或其他合适的介电材料。举例而言，第一绝缘部分140a的材质可与第二绝缘部分140b的材质相同。
第二绝缘部分140b可通过包覆型模塑工艺(over mold)以及抛光工艺(grinding)形成。在一些实施例中，可通过包覆型模塑工艺形成绝缘材料以包覆集成电路110以及导电柱体120，接着，绝缘材料可通过机械抛光工艺及/或化学机械抛光工艺进行抛光，直到集成电路110的背面110b以及全部导电柱体120的顶表面被暴露为止。在第二绝缘部分140b被抛光的期间，集成电路110以及导电柱体120会被抛光至相同水平高度。
第一绝缘部分140a以及第二绝缘部分140b构成绝缘封装体140。如图14所示，集成电路110、导电柱体120以及存储器器件130嵌于绝缘封装体140中。
在一些实施例中，导电柱体120的高度可与集成电路110的厚度以及第二绝缘部分140b的厚度实质上相同。
请参照图15，在绝缘封装体140形成之后，在绝缘封装体140的顶表面、导电柱体120的顶表面以及集成电路110的背面110b上形成重布线路结构150。在一些实施例中，导电柱体120与存储器器件130以及重布线路结构150电性连接。换句话说，重布线路结构150通过导电柱体120以及重布线层RDL而与集成电路110以及存储器器件130电性连接。
在一些实施例中，重布线路结构150包括多个与集成电路110的背面110b热耦接的导热通孔。通过重布线路结构150中的导热通孔以及导热通孔，集成电路110所产生的热可被有效率地传导与逸散。
请参照图16，在重布线路结构150形成之后，接着形成多个与重布线路结构150电性连接的导电端子160。集成电路110配置在重布线路结构150以及存储器器件130之间。换言之，导电端子160分布在重布线路结构150的一侧，而集成电路110、导电柱体120以及存储器器件130分布在重布线路结构150的另一侧。在一些实施例中，导电端子160可为导电凸块(conductive bumps)或导电球(conductive balls)。
如图16所示，积体扇出型封装体200包括集成电路110、存储器器件130、绝缘封装体140以及重布线路结构150。存储器器件130与集成电路110电性连接。重布线路结构150配置在绝缘封装体140上，且重布线路结构150与集成电路110以及存储器器件130电性连接。在一些实施例中，可选择性地形成导电端子160。如图16所示，在积体扇出型封装体200中，集成电路110以及存储器器件130嵌于绝缘封装体140中。
请参照图17，令积体扇出型封装体200从剥离层DB以及载板C上剥离。在一些实施例中，剥离层DB(例如，光热转换释放层)可被紫外光激光照射以使得积体扇出型封装体200能够与剥离层DB以及载板C分离。积体扇出型封装体200可被拾取并且设置在封装线路衬底170上。积体扇出型封装体200中的重布线路结构150通过导电端子160与封装线路衬底170电性连接。在一些实施例中，封装线路衬底170可包括多个分布在其底表面上的导电球172。举例而言，导电球172可为焊料球或其他金属球。值得注意的是，导电端子160的排列间距例如小于导电球172的排列间距。换句话说，具有导电球172排列在其上的封装线路衬底170可为球格阵列线路板，且球格阵列封装体200a包括积体扇出型封装体200以及封装线路衬底170。
如图17所示，为了增进导电端子160的接合可靠度，可在重布线路结构150与封装线路衬底170之间填入底填层180。底填层180包覆导电端子160以确保导电端子160的结构完整度，且由于重布线路结构150与封装线路衬底170之间的热膨胀系数差异，底填层180可确保其与重布线路结构150与封装线路衬底170之间的接合介面。换句话说，热膨胀系数差异所导致的剪应力可被底填层180所吸收，且导电端子160可被底填层180保护。
在一些实施例中，为了进一步增进散热能力，可将散热器190黏贴在存储器器件130被暴露出的表面上以及绝缘封装体140的顶表面上。举例而言，散热器190的材料包括铝或其他适合的金属材料。
图18以及图19为依照一些其他实施例所绘示的积体扇出型封装体的剖视图。请参照图18与图19，本实施例未使用高带宽存储器堆叠结构(HBM cubes)，而是使用与存储器器件130(绘示于图17中)不同架构的存储器器件130a。值得注意的是，本发明的实施例不限定存储器器件130a的数量。此外，如图18所示，图19中的封装线路衬底170在积体扇出型封装体中是选择性构件。
图20至图27为依照一些实施例所绘示的另一种积体扇出型封装体的制造流程剖视图。请参照图20至图22，图20至图22中的工艺与图10至图12中的工艺类似，故省略其详细描述。
请参照图23，在形成导电柱体120之后，将集成电路110拾取并设置在存储器器件130以及第一绝缘部分140a上。举例而言，集成电路110通过晶粒接合工艺中所使用的晶粒贴附薄膜(DAF)而设置在存储器器件130以及第一绝缘部分140a上。集成电路110包括有源表面110a以及与有源表面110a相对的背面110b，且集成电路110的背面110b朝向存储器器件130。
请参照图24，在第一绝缘部分140a上形成第二绝缘部分140b以包覆集成电路110以及导电柱体120。在一些实施例中，第二绝缘部分140b可为模塑工艺所形成的封装胶体。第二绝缘部分140b的材料包括环氧化合物(epoxy)或其他合适的介电材料。举例而言，第一绝缘部分140a的材质可与第二绝缘部分140b的材质相同。
第二绝缘部分140b可通过转移模塑工艺(transfer mold)工艺形成。在一些实施例中，通过转移模塑工艺形成绝缘材料以包覆集成电路110以及导电柱体120，并且使集成电路110的有源表面110a以及导电柱体120的顶表面暴露。在一些实施例中，可通过包覆型模塑工艺形成绝缘材料以包覆集成电路110以及导电柱体120，接着，绝缘材料可通过机械抛光工艺及/或化学机械抛光工艺进行抛光，直到集成电路110的金属柱体(未绘示)以及全部导电柱体120的顶表面被暴露为止。
第一绝缘部分140a以及第二绝缘部分140b构成绝缘封装体140。如图24所示，集成电路110、导电柱体120以及存储器器件130嵌于绝缘封装体140中。
请参照图25，在绝缘封装体140形成之后，在绝缘封装体140的顶表面、导电柱体120的顶表面以及集成电路110的有源表面110a上形成重布线路结构150。在一些实施例中，重布线路结构150与集成电路110以及导电柱体120电性连接，且重布线路结构150通过导电柱体120以及重布线层RDL而与存储器器件130电性连接。换句话说，集成电路110通过重布线路结构150、导电柱体120以及重布线层RDL与存储器器件130电性连接。
在一些实施例中，重布线路结构150包括多个与集成电路110的有源表面110a热耦接的导热通孔。通过重布线路结构150中的导热通孔以及导热通孔，集成电路110所产生的热可被有效率地传导与逸散。
请参照图26，在重布线路结构150形成之后，接着形成多个与重布线路结构150电性连接的导电端子160。请参照图26，集成电路110配置在重布线路结构150以及存储器器件130之间。换言之，导电端子160分布在重布线路结构150的一侧，而集成电路110、导电柱体120以及存储器器件130分布在重布线路结构150的另一侧。在一些实施例中，导电端子160可为导电凸块(conductive bumps)或导电球(conductive balls)。
如图26所示，积体扇出型封装体300包括集成电路110、存储器器件130、绝缘封装体140以及重布线路结构150。换句话说，存储器器件130例如是通过重布线路结构150、导电柱体120以及重布线层RDL与集成电路110电性连接。集成电路110与存储器器件130相互堆叠。在一些实施例中，可选择性地形成导电端子160。
请参照图27，令积体扇出型封装体300从剥离层DB以及载板C上剥离。在一些实施例中，剥离层DB(例如，光热转换释放层)可被紫外光激光照射以使得积体扇出型封装体300能够与剥离层DB以及载板C分离。积体扇出型封装体300可被拾取并且设置在封装线路衬底170上。积体扇出型封装体300中的重布线路结构150通过导电端子160与封装线路衬底170电性连接。在一些实施例中，封装线路衬底170可包括多个分布在其底表面上的导电球172。举例而言，导电球172可为焊料球或其他金属球。值得注意的是，导电端子160的排列间距例如小于导电球172的排列间距。换句话说，具有导电球172排列在其上的封装线路衬底170可为球格阵列线路板，且球格阵列封装体300a包括积体扇出型封装体300以及封装线路衬底170。
如图27所示，为了增进导电端子160的接合可靠度，可在重布线路结构150与封装线路衬底170之间填入底填层180。底填层180包覆导电端子160以确保导电端子160的结构完整度，且由于重布线路结构150与封装线路衬底170之间的热膨胀系数差异，底填层180可确保其与重布线路结构150与封装线路衬底170之间的接合介面。换句话说，热膨胀系数差异所导致的剪应力可被底填层180所吸收，且导电端子160可被底填层180保护。
在一些实施例中，为了进一步增进散热能力，可将散热器190黏贴在存储器器件130被暴露出的表面上以及绝缘封装体140的表面上。举例而言，散热器190的材料包括铝或其他适合的金属材料。
图28为依照一些其他实施例所绘示的积体扇出型封装体的剖视图。请参照图28，本实施例未使用高带宽存储器堆叠结构(HBM cubes)，而是使用与存储器器件130(绘示于图27中)不同架构的存储器器件130a。值得注意的是，本发明的实施例不限定存储器器件130a的数量。此外，图28中的封装线路衬底170在积体扇出型封装体中是选择性构件。
在上述实施例中，集成电路110以及存储器器件130的堆叠架构可以减小集成电路110的输入/输出介面与存储器器件130之间的距离。据此，积体扇出型封装体的效能(例如集成电路与存储器器件之间的短信号传输路径)可获得增进。此外，基于集成电路110与存储器器件130堆叠架构，积体扇出型封装体的积集度可获得增进。
依据本发明的一些实施例，积体扇出型封装体包括集成电路、多个存储器器件、绝缘封装体以及重布线路结构。存储器器件与集成电路电性连接。集成电路与存储器器件相互堆叠，且存储器器件嵌于绝缘封装体中。重布线路结构配置于绝缘封装体上，且重布线路结构与集成电路以及存储器器件电性连接。
在所述的积体扇出型封装体中，集成电路与存储器器件嵌于绝缘封装体中。
在所述的积体扇出型封装体中，各个存储器器件包括：多个堆叠的存储器芯片，各个存储器芯片包括多个凸块；以及控制器，其中存储器芯片与控制器相互堆叠并且通过凸块相互电性连接。
在所述的积体扇出型封装体中，集成电路包括有源表面以及与有源表面相对的背面，集成电路的有源表面朝向存储器器件，且集成电路通过位在有源表面与存储器器件之间的凸块与存储器器件电性连接。
在所述的积体扇出型封装体中，存储器器件位在重布线路结构与集成电路之间。此外，所述的积体扇出型封装体进一步包括多个嵌于绝缘封装体中的导电柱体，其中导电柱体与集成电路以及重布线路结构电性连接。
在所述的积体扇出型封装体中，集成电路位在重布线路结构与存储器器件之间。此外，所述的积体扇出型封装体进一步包括多个嵌于绝缘封装体中的导电柱体，其中导电柱体与集成电路以及重布线路结构电性连接。
所述的积体扇出型封装体进一步包括位于集成电路与存储器器件之间的重布线层，其中重布线层位在存储器器件的表面上，且存储器器件通过重布线层与集成电路电性连接。
在所述的积体扇出型封装体中，集成电路包括有源表面以及与有源表面相对的背面，集成电路的背面朝向存储器器件，集成电路的有源表面朝向重布线路结构，且集成电路与重布线路结构电性连接。
所述的积体扇出型封装体进一步包括：多个嵌于绝缘封装体中的导电柱体，导电柱体与存储器器件以及重布线路结构电性连接；以及位于存储器器件的表面上的重布线层，集成电路通过重布线路结构、导电柱体以及重布线层而与存储器器件电性连接。
所述的积体扇出型封装体进一步包括：多个与重布线路结构电性连接的导电端子，其中重布线路结构位在导电端子与存储器器件之间。
所述的积体扇出型封装体进一步包括封装线路衬底，其中重布线路结构通过导电端子与封装线路衬底电性连接。
依据本揭露的另一些实施例，一种积体扇出型封装体的制造方法被提出。将多个存储器器件设置在一芯片上，其中芯片包括多个排列成阵列的集成电路，且存储器器件与集成电路电性连接。在芯片上形成绝缘封装体以包覆存储器器件。在绝缘封装体以及存储器器件上形成重布线路结构配置，其中重布线路结构与集成电路以及存储器器件电性连接。切割重布线路结构、绝缘封装体以及芯片，以形成多个单体化的封装体。
所述的积体扇出型封装体的制造方法进一步包括：在绝缘封装体形成之前，在晶片上形成多个导电柱体，其中导电柱体与集成电路电性连接，而在绝缘封装体与重布线路结构形成之后，导电柱体嵌于绝缘封装体中并且与重布线路结构电性连接。
所述的积体扇出型封装体的制造方法进一步包括：形成多个与重布线路结构电性连接的导电端子，其中重布线路结构位在导电端子与存储器器件之间。
所述的积体扇出型封装体的制造方法进一步包括：将至少一个单体化的封装体设置在封装线路衬底上，其中所述至少一个单体化的封装体中的重布线路结构通过导电端子与封装线路衬底电性连接。
依据本揭露的另一些实施例，一种积体扇出型封装体的制造方法被提出。将多个存储器器件设置在载板上。在载板上形成绝缘封装体的第一绝缘部分，以包覆存储器器件。将集成电路设置在存储器器件上，其中集成电路与存储器器件电性连接。在第一绝缘部分上形成绝缘封装体的第二绝缘部分，以包覆集成电路。在绝缘封装体以及集成电路上形成重布线路结构配置，其中重布线路结构与集成电路以及存储器器件电性连接。
所述的积体扇出型封装体的制造方法进一步包括：在绝缘封装体的第二绝缘部分形成之前，在存储器器件上形成多个导电柱体，其中导电柱体与集成电路以及存储器器件电性连接，而在绝缘封装体的第二绝缘部分与重布线路结构形成之后，导电柱体嵌于导电柱体嵌于绝缘封装体的第二绝缘部分中并且与重布线路结构电性连接。
在所述的积体扇出型封装体的制造方法中，集成电路包括有源表面以及与有源表面相对的背面，且在集成电路被设置在存储器器件上之后，集成电路的有源表面或背面会朝向存储器器件。
以上概述了数个实施例的特征，使本领域具有通常知识者可更佳了解本发明的态样。本领域具有通常知识者应理解，其可轻易地使用本发明作为设计或修改其他工艺与结构的依据，以实行本文所介绍的实施例的相同目的及/或达到相同优点。本领域具有通常知识者还应理解，这种等效的配置并不悖离本发明的精神与范畴，且本领域具有通常知识者在不悖离本发明的精神与范畴的情况下可对本文做出各种改变、置换以及变更。
附图标号说明
100、200、300：积体扇出型封装体
100a、200a、300a：球格阵列封装体
110：集成电路
110a：有源表面
110b：背面
120：导电柱体
130：存储器器件
132：存储器芯片
132a：微凸块
132b：导通孔
134：控制器
134a：微凸块
134b：导通孔
140：绝缘封装体
150：重布线路结构
160：导电端子
170：封装线路衬底
172：导电球
180：底填层
190：散热器
AD：黏着层
C：载板
DB：剥离层
PAD：导电接垫
RDL：重布线层
SUB：半导体衬底
SL：切割线
W：晶片。

Claims (1)

1.一种积体扇出型封装体，其特征在于，包括:
集成电路；
多个存储器器件，与所述集成电路电性连接；
绝缘封装体，所述集成电路与所述存储器器件相互堆叠，且所述存储器器件嵌于所述绝缘封装体中；以及
重布线路结构，配置于所述绝缘封装体上，且所述重布线路结构与所述集成电路以及所述存储器器件电性连接。
CN201611038412.XA 2016-06-24 2016-11-11 积体扇出型封装体 Pending CN107546193A (zh)

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