CN105097792A - 晶片封装体及其制造方法 - Google Patents
晶片封装体及其制造方法 Download PDFInfo
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- CN105097792A CN105097792A CN201510239639.XA CN201510239639A CN105097792A CN 105097792 A CN105097792 A CN 105097792A CN 201510239639 A CN201510239639 A CN 201510239639A CN 105097792 A CN105097792 A CN 105097792A
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- substrate
- conductive structure
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- conductive
- layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims description 183
- 239000000758 substrate Substances 0.000 claims abstract description 255
- 238000005538 encapsulation Methods 0.000 claims description 92
- 230000004888 barrier function Effects 0.000 claims description 68
- 239000000463 material Substances 0.000 claims description 37
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 33
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 239000010410 layer Substances 0.000 description 105
- 235000012431 wafers Nutrition 0.000 description 83
- 238000000576 coating method Methods 0.000 description 22
- 238000002161 passivation Methods 0.000 description 21
- 238000005240 physical vapour deposition Methods 0.000 description 18
- UFWIBTONFRDIAS-UHFFFAOYSA-N Naphthalene Chemical compound C1=CC=CC2=CC=CC=C21 UFWIBTONFRDIAS-UHFFFAOYSA-N 0.000 description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 239000004020 conductor Substances 0.000 description 14
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 13
- 229910052737 gold Inorganic materials 0.000 description 13
- 239000010931 gold Substances 0.000 description 13
- 239000011248 coating agent Substances 0.000 description 11
- 238000005520 cutting process Methods 0.000 description 10
- 239000003292 glue Substances 0.000 description 10
- 229910044991 metal oxide Inorganic materials 0.000 description 10
- 150000004706 metal oxides Chemical class 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 238000000151 deposition Methods 0.000 description 9
- 230000008021 deposition Effects 0.000 description 9
- 238000000059 patterning Methods 0.000 description 9
- 229920000052 poly(p-xylylene) Polymers 0.000 description 9
- 229920001721 polyimide Polymers 0.000 description 9
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 239000003822 epoxy resin Substances 0.000 description 8
- 229910052731 fluorine Inorganic materials 0.000 description 8
- 239000011737 fluorine Substances 0.000 description 8
- 229910010272 inorganic material Inorganic materials 0.000 description 8
- 239000011147 inorganic material Substances 0.000 description 8
- 239000011810 insulating material Substances 0.000 description 8
- 229910052759 nickel Inorganic materials 0.000 description 8
- 239000011368 organic material Substances 0.000 description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
- 229920000647 polyepoxide Polymers 0.000 description 8
- 239000009719 polyimide resin Substances 0.000 description 8
- 229920000642 polymer Polymers 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 239000011241 protective layer Substances 0.000 description 7
- 229910052718 tin Inorganic materials 0.000 description 7
- 239000011135 tin Substances 0.000 description 7
- 239000004411 aluminium Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 238000003466 welding Methods 0.000 description 5
- 238000007772 electroless plating Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000011133 lead Substances 0.000 description 3
- 238000003801 milling Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000002390 adhesive tape Substances 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000002322 conducting polymer Substances 0.000 description 2
- 229920001940 conductive polymer Polymers 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000003973 paint Substances 0.000 description 2
- 238000010422 painting Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- OGZARXHEFNMNFQ-UHFFFAOYSA-N 1-butylcyclobutene Chemical compound CCCCC1=CCC1 OGZARXHEFNMNFQ-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 150000001252 acrylic acid derivatives Chemical class 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920000417 polynaphthalene Polymers 0.000 description 1
- 238000010897 surface acoustic wave method Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
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Abstract
本发明揭露一种晶片封装体及其制造方法,该晶片封装体包括:一第一基底,第一基底内包括一感测装置;一第二基底,贴附于第一基底上,第二基底内包括一集成电路装置;一第一导电结构,通过设置于第一基底上的重布线层电性连接感测装置及集成电路装置;一绝缘层,覆盖第一基底、第二基底及重布线层,其中绝缘层内具有孔洞;以及一第二导电结构,设置于孔洞的底部下方。本发明能够缩小后续接合的电路板的尺寸,进而缩小具有感测功能的电子产品的尺寸。
Description
技术领域
本发明有关于一种晶片封装技术,特别为有关于一种晶片封装体及其制造方法。
背景技术
晶片封装制程是形成电子产品过程中的重要步骤。晶片封装体除了将晶片保护于其中,使其免受外界环境污染外,还提供晶片内部电子元件与外界的电性连接通路。
具有感测功能的晶片封装体通常与其他集成电路晶片各自独立地设置于电路板上,再通过打线彼此电性连接。
然而,上述制造方法限制了电路板的尺寸,进而导致具有感测功能的电子产品的尺寸难以进一步缩小。
因此,有必要寻求一种新颖的晶片封装体及其制造方法,其能够解决或改善上述的问题。
发明内容
本发明提供一种晶片封装体,包括:一第一基底,第一基底内包括一感测装置;一第二基底,贴附于第一基底上,其中第二基底内包括一集成电路装置;一第一导电结构,通过设置于第一基底上的重布线层电性连接感测装置及集成电路装置;一绝缘层,覆盖第一基底、第二基底及重布线层,其中绝缘层内具有孔洞;以及一第二导电结构,设置于孔洞的底部下方。
本发明还提供一种晶片封装体的制造方法,包括:提供一第一基底,其中第一基底内包括一感测装置;将一第二基底贴附于第一基底上,其中第二基底内包括一集成电路装置;形成一第一导电结构,以通过该第一基底上的一重布线层将感测装置电性连接至集成电路装置;以及形成一第二导电结构及一绝缘层,其中绝缘层覆盖第一基底、第二基底及重布线层,且绝缘层内具有孔洞,一第二导电结构位于孔洞的底部下方。
本发明能够缩小后续接合的电路板的尺寸,进而缩小具有感测功能的电子产品的尺寸。
附图说明
图1A至1F是绘示出根据本发明一实施例的晶片封装体的制造方法的剖面示意图。
图2是绘示出根据本发明一实施例的晶片封装体的平面示意图。
图3A及3B是分别绘示出根据本发明另一实施例的晶片封装体的剖面示意图及平面示意图。
图4A及4B是分别绘示出根据本发明又另一实施例的晶片封装体的剖面示意图及平面示意图。
图5A至5F是绘示出根据本发明另一实施例的晶片封装体的制造方法的剖面示意图。
图6是绘示出根据本发明又另一实施例的晶片封装体的剖面示意图。
其中,附图中符号的简单说明如下:
100第一基底;
100a第一表面;
100b第二表面;
120晶片区;
140、320导电垫;
160感测装置;
170、330内连线结构;
175光学部件;
180间隔层;
200盖板;
220第一开口;
240、400绝缘层;
260重布线层;
280粘着层;
300第二基底;
310集成电路装置;
340第一导电结构;
360第二导电结构;
420孔洞;
440金属层;
460钝化保护层;
480第二开口;
500第三导电结构。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然而应注意的是,本发明提供许多可供应用的发明概念,其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式,非用以限制本发明的范围。此外,在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明,不代表所讨论的不同实施例及/或结构之间具有任何关连性。再者,当述及一第一材料层位于一第二材料层上或之上时,包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装微机电系统晶片。然其应用不限于此,例如在本发明的晶片封装体的实施例中,其可应用于各种包含有源元件或无源元件(activeorpassiveelements)、数字电路或模拟电路(digitaloranalogcircuits)等集成电路的电子元件(electroniccomponents),例如是有关于光电元件(optoelectronicdevices)、微机电系统(MicroElectroMechanicalSystem,MEMS)、生物辨识元件(biometricdevice)、微流体系统(microfluidicsystems)、或利用热、光线、电容及压力等物理量变化来测量的物理感测器(PhysicalSensor)。特别是可选择使用晶圆级封装(waferscalepackage,WSP)制程对影像感测元件、发光二极管(light-emittingdiodes,LEDs)、太阳能电池(solarcells)、射频元件(RFcircuits)、加速计(accelerators)、陀螺仪(gyroscopes)、指纹辨识器(fingerprintrecognitiondevice)、微制动器(microactuators)、表面声波元件(surfaceacousticwavedevices)、压力感测器(processsensors)或喷墨头(inkprinterheads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后,再予以切割成独立的封装体,然而,在一特定实施例中,例如将已分离的半导体晶片重新分布在一承载晶圆上,再进行封装制程,亦可称之为晶圆级封装制程。另外,上述晶圆级封装制程亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶圆,以形成多层集成电路(multi-layerintegratedcircuitdevices)或系统级封装(SysteminPackage,SIP)的晶片封装体。
请参照图1F及2,其分别绘示出根据本发明一实施例的晶片封装体的剖面示意图及平面示意图,其中图1F是绘示出沿着图2中的剖线I-I’的剖面示意图。在本实施例中,晶片封装体包括一第一基底100、一第二基底300及多个第一导电结构340。第一基底100具有一第一表面100a及与其相对的一第二表面100b。在一实施例中,第一基底100可为一硅基底或其他半导体基底。
在本实施例中,第一基底100内包括一感测装置160及一个或一个以上的导电垫140,其可邻近于第一表面100a。在一实施例中,导电垫140可为单层导电层或具有多层的导电层结构。为简化图式,此处仅以单层导电层作为范例说明(如图1F所示),且仅绘示出第一基底100内的六个导电垫140作为范例说明(如图2所示)。在本实施例中,第一基底100内还包括多个第一开口220,其自第二表面100b朝第一表面100a延伸,并暴露出对应的导电垫140。
在一实施例中,感测装置160包括一影像感测元件(例如,互补式金属氧化物半导体影像感测元件(ComplementaryMetal-Oxide-SemiconductorImageSensor,CIS)),且一光学部件175对应于感测装置160而设置于第一表面100a上。光学部件175可包括滤光层及微透镜或其他适合的光学部件。在另一实施例中,感测装置160用以感测生物特征,且可包括一指纹辨识元件。又另一实施例中,感测装置160用以感测环境特征,且可包括一温度感测元件、一湿度感测元件、一压力感测元件、一电容感测元件或其他适合的感测元件。在一实施例中,感测装置160内的感测元件可通过第一基底100内的内连线结构(其可包括多层介电层、接触窗、多层金属导线及介层窗)而与导电垫140电性连接。为简化图式,此处仅以虚线170表示感测装置160与导电垫140之间的内连线结构。
一盖板200通过一间隔层(或称作围堰(dam))180贴附于第一基底100的第一表面100a上。间隔层180覆盖导电垫140,并暴露出感测装置160及光学部件175,而盖板200保护暴露出的感测装置160及光学部件175。在一实施例中,间隔层180大致上不吸收水气。在一实施例中,间隔层180不具有粘性,因此间隔层180可通过额外的粘着胶,以将盖板200贴附于第一基底100上。在另一实施例中,间隔层180可具有粘性,因此间隔层180可不与任何的粘着胶接触,以确保间隔层180的位置不因粘着胶而移动。同时,由于不需使用粘着胶,可避免粘着胶溢流而污染感测装置160。在本实施例中,间隔层180可包括环氧树脂、无机材料(例如,氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如,聚酰亚胺树脂(polyimide)、苯环丁烯(butylcyclobutene,BCB)、聚对二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))、光阻材料或其他适合的绝缘材料。再者,盖板200可包括玻璃、蓝宝石或其他适合的保护材料。
一绝缘层240顺应性设置于第一基底100的第二表面100b上,且延伸至第一基底100的第一开口220内,并暴露出部分的导电垫140。在本实施例中,绝缘层240可包括环氧树脂、无机材料(例如,氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如,聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
一图案化的重布线层(redistributionlayer,RDL)260设置于绝缘层240上,且顺应性延伸至第一开口220的侧壁及底部上。重布线层260可经由第一开口220直接或间接接触暴露出的导电垫140,以电性连接至导电垫140,且通过绝缘层240与第一基底100电性隔离。因此,第一开口220内的重布线层260也称为硅通孔电极(throughsiliconvia,TSV)。在一实施例中,重布线层260可包括铜、铝、金、铂、镍、锡、前述的组合、导电高分子材料、导电陶瓷材料(例如,氧化铟锡或氧化铟锌)或其他适合的导电材料。
在另一实施例中,第一基底100的第一开口220可至少穿过导电垫140,使得重布线层260可与导电垫140的内部直接接触,而以环型接触(ring-contact)的方式电性连接至导电垫140。
第二基底300可通过一粘着层(例如,粘着胶(glue))280贴附于第二表面100b上的绝缘层240上。在本实施例中,第二基底300内包括一集成电路装置310。再者,集成电路装置310可包括信号处理元件(例如,影像信号处理元件(ImageSignalProcess,ISP))或其他特定应用集成电路元件(Application-specificintegratedcircuit,ASIC)。
在本实施例中,第二基底300内可包括一个或一个以上的导电垫320,其可邻近于第二基底300的上表面(即,相对于第二表面100b的表面)。相似地,导电垫320可为单层导电层或具有多层的导电层结构。为简化图式,此处仅以单层导电层作为范例说明。在一实施例中,导电垫320可通过第二基底300内的内连线结构而与集成电路装置310内的集成电路元件电性连接。为简化图式,此处仅以虚线330表示集成电路装置310与导电垫320之间的内连线结构。
在本实施例中,第一基底100的尺寸大于第二基底300的尺寸。再者,当第一基底100的尺寸足够大时,可在第一基底100的第二表面100b上设置一个以上具有不同集成电路功能的第二基底300。在本实施例中,第二基底300与第一基底100的感测装置160完全上下重叠。在其他实施例中,第二基底300也可与第一基底100的感测装置160部分上下重叠或未上下重叠。
第一导电结构340设置于对应的重布线层260及导电垫320上,并通过重布线层260及导电垫140电性连接至感测装置160以及通过导电垫320电性连接至集成电路装置310,因此第一导电结构340使感测装置160与集成电路装置310彼此电性连接。在一实施例中,第一导电结构340由导电垫320上的接合球(bondingball)及自接合球延伸至重布线层260的接线(wire)所构成。再者,第一导电结构340可包括金或其他适合的导电材料。
在本实施例中,晶片封装体还包括多个第二导电结构360、一绝缘层400、一图案化的金属层440、一钝化保护(passivation)层460及多个第三导电结构500,设置于第一基底100的第二表面100b上。第二导电结构360设置于对应的重布线层260上,且通过重布线层260与对应的导电垫140电性连接。在本实施例中,第二导电结构360由接合球所构成,且可包括金或其他适合的导电材料。在一实施例中,第二导电结构360的材料相同于第一导电结构340的材料。
绝缘层400覆盖第二基底300、绝缘层240、重布线层260及第一导电结构340,且具有多个孔洞420,暴露出对应的第二导电结构360,也就是说第二导电结构360位于孔洞420的底部下方。在本实施例中,绝缘层400未填入第一基底100的第一开口220内。在其他实施例中,绝缘层400可部分填入第一基底100的第一开口220内或将其填满。在本实施例中,绝缘层400可包括环氧树脂、无机材料(例如,氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如,聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
图案化的金属层440设置于绝缘层400上,且填入绝缘层400的孔洞420内,以经由孔洞420电性连接至暴露出的第二导电结构360。在本实施例中,金属层440填满绝缘层400的孔洞420。在其他实施例中,金属层440可顺应性设置于孔洞420的侧壁及底部,而未填满绝缘层400的孔洞420。在一实施例中,金属层440可包括铜、铝、金、铂、镍、锡、前述的组合或其他适合的导电材料。
钝化保护层460设置于金属层440及绝缘层400上,且具有多个第二开口480,暴露出位于绝缘层400上的金属层440的一部分。在本实施例中,钝化保护层460可包括环氧树脂、绿漆(soldermask)、无机材料(例如,氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如,聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)、光阻材料或其他适合的绝缘材料。
第三导电结构500对应地设置于钝化保护层460的第二开口480内,以直接接触暴露出的金属层440,而与金属层440电性连接。在本实施例中,第三导电结构500未重叠第二基底300(如图2所示)。在另一实施例中,第三导电结构500可重叠第二基底300。在其他实施例中,第三导电结构500可排列为一矩阵,以利于后续能提供稳固的接合。可以理解的是,第一导电结构340、第二导电结构360及第三导电结构500的位置取决于设计需求而不限定于此。
在本实施例中,第三导电结构500可为凸块(例如,接合球或导电柱)或其他适合的导电结构,且可包括锡、铅、铜、金、镍、前述的组合或其他适合的导电材料。举例来说,第三导电结构500可为焊球(solderball)。在一实施例中,第二导电结构360及第三导电结构500皆为接合球,且第三导电结构500的尺寸大于第二导电结构360的尺寸。在一实施例中,第三导电结构500的材料不同于第二导电结构360的材料。
请参照图3A及3B,其分别绘示出根据本发明另一实施例的晶片封装体的剖面示意图及平面示意图,其中相同于前述图1F及2的实施例的部件使用相同的标号并省略其说明。图3A及3B中的晶片封装体的结构类似于图1F及2中的晶片封装体的结构。从剖面方向来看,图1F中的两个第二导电结构360皆设置于第一基底100上,进而通过重布线层260及第一导电结构340与对应的两个导电垫320电性连接。在图3A中,其中一个第二导电结构360设置于第一基底100上,且通过重布线层260及第一导电结构320与对应的一个导电垫320电性连接,而另一个第二导电结构360设置于第二基底300上,且直接设置于对应的导电垫320上方而与其直接或间接电性连接,因此暴露出第二导电结构360的其中一个孔洞420与其中一个导电垫320上下重叠。在其他实施例中,多个第二导电结构360设置于第二基底300上,且皆设置于对应的导电垫320上方而与其电性连接,因此暴露出第二导电结构360的多个孔洞420也可与多个导电垫320上下重叠。
再者,从俯视方向来看,图2中的所有第二导电结构360皆位于第二基底300的外侧,而在图3B中,一部分的第二导电结构360位于第二基底300的外侧,另一部分的第二导电结构360位于第二基底300上方而与第二基底300上下重叠。在其他实施例中,所有第二导电结构360可皆位于第二基底300上方而与第二基底300上下重叠。
请参照图4A及4B,其分别绘示出根据本发明又另一实施例的晶片封装体的剖面示意图及平面示意图,其中相同于前述图1F及2的实施例的部件使用相同的标号并省略其说明。图4A及4B中的晶片封装体的结构类似于图1F及2中的晶片封装体的结构。从剖面方向来看,图1F中的第二基底300通过粘着层280贴附于第一基底100的第二表面100b上,使得导电垫320背向第一基底100的第二表面100b,且第一导电结构340设置于导电垫320上并延伸至对应的重布线层260上。此时,第一导电结构340由接合球及接线所构成。而在图4A中,重布线层260进一步延伸至第二基底300与第一基底100的第二表面100b之间,且第二基底300通过第一导电结构340接合至重布线层260上,使得导电垫320朝向第一基底100的第二表面100b。此时,第一导电结构340可为凸块(例如,接合球或导电柱)。在一实施例中,第一导电结构340、第二导电结构360及第三导电结构500皆为接合球。再者,第二导电结构360的尺寸小于第三导电结构500的尺寸,且大于第一导电结构340的尺寸。
从俯视方向来看,图2中的重布线层260位于第二基底300的外侧,且第一导电结构340位于第二基底300上方并延伸至重布线层260上,而在图4B中,重布线层260延伸至第二基底300的下方,且第一导电结构340位于第二基底300下方并与第二基底300完全上下重叠。可以理解的是,前述图式所绘示出的重布线层260、第一导电结构340、第二导电结构360及第三导电结构500的位置仅为范例说明,其取决于设计需求而不限定于此。
具有感测功能的晶片封装体内的感测装置及导电垫通常位于晶片封装体的有源面。由于有源面上的感测装置需避免被遮蔽,且无法通过打线接合制程在有源面与相对的非有源面之间形成电性连接通路,因此具有感测功能的晶片封装体通常与其他集成电路晶片各自独立地设置于电路板上,再通过打线而彼此电性连接。
根据本发明的上述实施例,由于重布线层260构成硅通孔电极而电性连接至第一基底100内的导电垫140及感测装置160,因此第二基底300可设置于第一基底100的第二表面100b上而避免遮蔽第一基底100内邻近第一表面100a的感测装置160,并可通过第一导电结构(例如,打线)340而将第一基底100内的感测装置160电性连接至第二基底300内的集成电路装置310。因此,根据本发明实施例能够将感测装置及一个或一个以上的集成电路装置整合于同一晶片封装体内,且缩小后续接合的电路板的尺寸,进而能够进一步缩小具有感测功能的电子产品的尺寸。
图1F、2、3A、3B、4A及4B中的晶片封装体是以具有前照式影像感测元件的晶片封装体作为范例,然而本发明亦可应用于其他晶片封装体,例如具有背照式影像感测元件的晶片封装体或具有不同功能的晶片封装体。
举例来说,图5F及6中的晶片封装体的结构分别类似于图4A及3A中的晶片封装体的结构,差异在于图5F及6中的晶片封装体具有背照式影像感测元件,而图4A及3A中的晶片封装体具有前照式影像感测元件,图5F及6中相同于前述图4A及3A的实施例的部件使用相同的标号并省略其说明。在图5F及6中,第一基底100内不具有第一开口220,且重布线层260、第二基底300及绝缘层400等结构设置于第一基底100的第一表面100a上,而光学部件175设置于第一基底100的第二表面100b上且盖板200通过间隔层180贴附于第二表面100b上。
根据本发明上述各种实施例,不论是前照式或背照式影像感测元件,皆能够将感测装置及一个或一个以上的集成电路装置整合于同一晶片封装体内,因此可大幅降低电子产品的尺寸。
以下配合图1A至1F说明本发明一实施例的晶片封装体的制造方法,其中图1A至1F是绘示出根据本发明一实施例的晶片封装体的制造方法的剖面示意图。
请参照图1A,提供一第一基底100,其具有一第一表面100a及与其相对的一第二表面100b,且包括多个晶片区120。在一实施例中,第一基底100可为一硅基底或其他半导体基底。举例来说,第一基底100可为一硅晶圆,以利于进行晶圆级封装制程。
在本实施例中,第一基底100的每一晶片区120内具有一个或一个以上的导电垫140,其可邻近于第一表面100a。为简化图式,此处仅绘示出第一基底100的单一晶片区120以及位于其中的两个导电垫140。在一实施例中,导电垫140可为单层导电层或具有多层的导电层结构。此处,仅以单层导电层作为范例说明。
在本实施例中,第一基底100的每一晶片区120内还具有一感测装置160,其可邻近于第一表面100a。在一实施例中,感测装置160包括一影像感测元件(例如,互补式金属氧化物半导体影像感测元件(CIS))。在另一实施例中,感测装置160用以感测生物特征,且可包括一指纹辨识元件。又另一实施例中,感测装置160用以感测环境特征,且可包括一温度感测元件、一湿度感测元件、一压力感测元件、一电容感测元件或其他适合的感测元件。在一实施例中,感测装置160内的感测元件可通过第一基底100内的内连线结构而与导电垫140电性连接。为简化图式,此处仅以虚线170表示感测装置160与导电垫140之间的内连线结构。
可通过涂布、曝光及显影制程,在第一基底100的第一表面100a上形成对应于感测装置160的一光学部件175。光学部件175可包括滤光层及微透镜或其他适合的光学部件。接着,可通过一间隔层(或称作围堰)180,将一盖板200贴附于第一基底100的第一表面100a上。间隔层180覆盖导电垫140,而暴露出感测装置160及光学部件175。在一实施例中,间隔层180大致上不吸收水气。在一实施例中,间隔层180不具有粘性,因此间隔层180可与额外的粘着胶接触。在另一实施例中,间隔层180可具有粘性,因此间隔层180可不与任何的粘着胶接触,以确保间隔层180的位置不因粘着胶而移动。同时,由于不需使用粘着胶,可避免粘着胶溢流而污染感测装置160。在本实施例中,间隔层180可包括环氧树脂、无机材料(例如,氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如,聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)、光阻材料或其他适合的绝缘材料。再者,盖板200可包括玻璃、蓝宝石或其他适合的保护材料。
请参照图1B,以盖板200作为承载基板,对第一基底100的第二表面100b进行薄化制程(例如,蚀刻制程、铣削(milling)制程、机械研磨(mechanicalgrinding)制程或化学机械研磨(chemicalmechanicalpolishing)制程),以减少第一基底100的厚度。
接着,可通过微影制程及蚀刻制程(例如,干蚀刻制程、湿蚀刻制程、电浆蚀刻制程、反应性离子蚀刻制程或其他适合的制程),在第一基底100的每一晶片区120内形成多个第一开口220。第一开口220自第一基底100的第二表面100b朝第一表面100a延伸,且分别暴露出邻近于第一表面100a的对应的导电垫140。
请参照图1C,可通过沉积制程(例如,涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程),在第一基底100的第二表面100b上顺应性形成一绝缘层240,其延伸至第一基底100的第一开口220内。在本实施例中,绝缘层240可包括环氧树脂、无机材料(例如,氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如,聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
接着,可通过微影制程及蚀刻制程(例如,干蚀刻制程、湿蚀刻制程、电浆蚀刻制程、反应性离子蚀刻制程或其他适合的制程),去除第一开口220的底部上的绝缘层240,以暴露出导电垫140的表面。接着,可通过沉积制程(例如,涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、微影制程及蚀刻制程,在绝缘层240上形成图案化的重布线层260。
重布线层260顺应性延伸至第一基底100的第一开口220的侧壁及底部上,且可经由第一开口220与暴露出的导电垫140直接或间接接触,以电性连接至导电垫140,并通过绝缘层240与第一基底100电性隔离。因此,第一开口220内的重布线层260也称为硅通孔电极。在一实施例中,重布线层260可包括铜、铝、金、铂、镍、锡、前述的组合、导电高分子材料、导电陶瓷材料(例如,氧化铟锡或氧化铟锌)或其他适合的导电材料。
在另一实施例中,第一基底100的第一开口220可至少穿过导电垫140,使得重布线层260可与导电垫140的内部直接接触,而以环型接触的方式电性连接至导电垫140。
请参照图1D,可通过一粘着层(例如,粘着胶)280,将一第二基底300贴附于第二表面100b上的绝缘层240上。在本实施例中,第二基底300内包括一集成电路装置310。再者,集成电路装置310可包括信号处理元件(例如,影像信号处理元件(ISP))或其他特定应用集成电路元件(ASIC)。
在本实施例中,第二基底300内可包括一个或一个以上的导电垫320,其可邻近于第二基底300的上表面。为简化图式,此处仅绘示出第二基底300内的两个导电垫320。在一实施例中,导电垫320可为单层导电层或具有多层的导电层结构。此处,仅以单层导电层作为范例说明。在一实施例中,导电垫320可通过第二基底300内的内连线结构(如虚线330所示)而与集成电路装置310内的集成电路元件电性连接。
在本实施例中,第一基底100的尺寸大于第二基底300的尺寸。再者,当第一基底100的尺寸足够大时,可在第一基底100的第二表面100b上设置一个以上具有不同集成电路功能的第二基底300。在一实施例中,第二基底300与第一基底100的感测装置160完全上下重叠。在其他实施例中,第二基底300也可与第一基底100的感测装置160部分上下重叠或未上下重叠。
接着,可通过打线接合(WireBonding)制程,将一第一导电结构340形成于对应的导电垫320及重布线层260上,并将一第二导电结构360形成于对应的重布线层260上。在一实施例中,可通过同一打线接合制程,形成第一导电结构340及第二导电结构360。在其他实施例中,可通过个别的打线接合制程,分别形成第一导电结构340及第二导电结构360。
第一导电结构340通过重布线层260及导电垫140电性连接至感测装置160,且通过导电垫320电性连接至集成电路装置310,因此第一导电结构340使感测装置160与集成电路装置310彼此电性连接。在一实施例中,第一导电结构340由导电垫320上的接合球及自接合球延伸至重布线层260的接线所构成。再者,第一导电结构340可包括金或其他适合的导电材料。
第二导电结构360通过重布线层260与对应的导电垫140电性连接。在一实施例中,第二导电结构360由位于重布线层260上的接合球所构成。再者,第二导电结构360可包括金或其他适合的导电材料。在一实施例中,第二导电结构360的材料可相同于第一导电结构340的材料。
请参照图1E,可通过模塑成型(molding)制程或沉积制程(例如,涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程),在第一基底100的第二表面100b上形成一绝缘层400,以覆盖第二基底300、绝缘层240、重布线层260及第一导电结构340。在本实施例中,绝缘层400未填入第一基底100的第一开口220内。在其他实施例中,绝缘层400可部分填入第一基底100的第一开口220内或将其填满。在本实施例中,绝缘层400可包括环氧树脂、无机材料(例如,氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如,聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
接着,可通过激光钻孔(laserdrilling)制程或微影及蚀刻制程(例如,干蚀刻制程或湿蚀刻制程),在绝缘层400内形成多个孔洞420,分别暴露出对应的第二导电结构360,因此第二导电结构360位于孔洞420的底部下方。
在本实施例中,重布线层260上的第二导电结构360可于形成孔洞420的制程(例如,激光钻孔制程)中作为缓冲层,以避免上述制程破坏重布线层260,因此能够提升晶片封装体的可靠度或品质。再者,由于重布线层260上形成有第二导电结构360,因此可降低孔洞420的深度,进而可降低孔洞420的深宽比(aspectratio,AR)而有利于制作孔洞420。
在另一实施例中,在进行打线接合制程之后,可将一个或一个以上的第二导电结构360形成于对应的导电垫320上,而将其他第二导电结构360形成于对应的重布线层260上,如此一来,一个或一个以上的第二导电结构360位于第二基底300上方而与第二基底300上下重叠。接着,在绝缘层400内形成孔洞420而分别暴露出对应的第二导电结构360,使得一个或一个以上的孔洞420与对应的导电垫320上下重叠,而其他孔洞420则与对应的重布线层260上下重叠,如图3A及3B所示。
在其他实施例中,也可将所有的第二导电结构360形成于对应的导电垫320上,使得所有的第二导电结构360皆位于第二基底300上方而与第二基底300上下重叠,且所有的孔洞420与对应的导电垫320上下重叠。请参照图1F,可通过沉积制程(例如,涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、微影制程及蚀刻制程,在绝缘层400上形成图案化的金属层440,且填入绝缘层400的孔洞420内,以经由孔洞420电性连接至暴露出的第二导电结构360。在本实施例中,金属层440填满绝缘层400的孔洞420。在其他实施例中,金属层440可顺应性形成于孔洞420的侧壁及底部,而未填满绝缘层400的孔洞420。在一实施例中,金属层440可包括铜、铝、金、铂、镍、锡、前述的组合或其他适合的导电材料。
接着,可通过沉积制程(例如,涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程),在金属层440及绝缘层400上形成一钝化保护层460。接着,可通过微影制程及蚀刻制程,在每一晶片区120的钝化保护层460内形成多个第二开口480,以暴露出位于绝缘层400上的金属层440的一部分。在本实施例中,钝化保护层460可包括环氧树脂、绿漆、无机材料(例如,氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如,聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。在另一实施例中,钝化保护层460可包括光阻材料,且可通过微影制程,在钝化保护层460内形成第二开口480。
接着,将第三导电结构500对应地设置于钝化保护层460的第二开口480内,以直接接触暴露出的金属层440,而与金属层440电性连接。在本实施例中,第三导电结构500可为凸块(例如,接合球或导电柱)或其他适合的导电结构。举例来说,可通过电镀制程、网版印刷制程或其他适合的制程,在钝化保护层460的第二开口480内形成焊料,且进行回焊制程而形成焊球,以作为第三导电结构500。在本实施例中,第三导电结构500可包括锡、铅、铜、金、镍、前述的组合或其他适合的导电材料。
在一实施例中,第二导电结构360及第三导电结构500皆为接合球,且第三导电结构500的尺寸大于第二导电结构360的尺寸。在一实施例中,第三导电结构500的材料不同于第二导电结构360的材料。在一实施例中,第三导电结构500的形成方法不同于第二导电结构360的形成方法。举例来说,第三导电结构500通过回焊制程所形成,而第二导电结构360通过打线接合制程所形成。根据本发明实施例,第二导电结构360由能够与重布线层260的材料(例如,铝)直接共晶接合的材料(例如,金)所构成,因此第二导电结构360可直接形成于重布线层260上,而无需额外对重布线层260进行表面处理(例如,在重布线层260与第二导电结构360之间额外形成镍层)。再者,由于可采用打线接合制程而非回焊制程来形成第二导电结构360,因此亦能够简化制程。
在一实施例中,第三导电结构500未重叠第二基底300(如图2所示)。在另一实施例中,第三导电结构500可重叠第二基底300。在其他实施例中,第三导电结构500可排列为一矩阵,以利于后续能提供稳固的接合。可以理解的是,第一导电结构340、第二导电结构360及第三导电结构500的位置取决于设计需求而不限定于此。
接着,可在钝化保护层460及第三导电结构500上形成一保护层(例如,胶带(未绘示)),以提供平坦的表面及保护第三导电结构500。接着,以保护层作为支撑,沿着相邻晶片区120之间的切割道(未绘示),依序对盖板200、第一基底100及绝缘层400进行切割制程,并去除保护层,以形成多个独立的晶片封装体。在上述实施例中,盖板200可由透光材料(例如,玻璃、蓝宝石或其他适合的透光材料)所构成,其有利于沿着自盖板200朝第一基底100的方向进行切割制程,进而提升对位的精准度。
在另一实施例中,可直接利用盖板200提供平坦的表面,沿着自第一基底100朝盖板200的方向进行上述切割制程,而无需形成上述保护层。在上述实施例中,若盖板200是易于刮伤材料(例如,玻璃、蓝宝石或其他易于刮伤材料),也可在盖板200上形成一保护层(例如,胶带(未绘示))。接着,以保护层作为支撑,沿着相邻晶片区120之间的切割道(未绘示),依序对绝缘层400、第一基底100及盖板200进行切割制程,并去除保护层,以形成多个独立的晶片封装体。
在本实施例中,可进一步在独立的晶片封装体的第一基底100的第二表面100b上提供一电路板(未绘示),且通过第三导电结构500将第一基底100内的感测装置160及第二基底300内的集成电路装置310电性连接至电路板。在上述各种实施例中,第二导电结构360的位置及数量取决于设计需求,而未加以限定。举例来说,在一实施例中,将第二导电结构360皆形成于第二基底300上,使得第二基底300的信号或其他输出电路(例如,电源供应或接地)经由第二导电结构360直接向外输出,而第一基底100的信号或其他输出电路(例如,电源供应或接地)则经由第一导电结构340、第二基底300及第二导电结构360向外输出。在另一实施例中,将第二导电结构360皆形成于第一基底100上,使得第一基底100及第二基底300的信号或其他输出电路皆经由第二导电结构360向外输出。在其他实施例中,第二导电结构360可各自形成于第一基底100及第二基底300上,使得第二基底300的信号或其他输出电路经由第二基底300上的第二导电结构360直接向外输出,第一基底100的信号或其他输出电路可选择性经由第一导电结构340、第二基底300及第二基底300上的第二导电结构360向外输出或是不经由第二基底300而经由第一基底100上的第二导电结构360直接向外输出。
根据本发明的上述实施例,由于采用硅通孔电极(即,重布线层260)作为具有感测装置160的第一基底100的外部电性连接的路径,因此第二基底300可设置于第一基底100的第二表面100b上而避免遮蔽第一基底100内邻近第一表面100a的感测装置160。再者,可通过打线接合制程形成第一导电结构340,而将第一基底100内的感测装置160电性连接至第二基底300内的集成电路装置310。因此,根据本发明实施例能够将感测装置及一个或一个以上的集成电路装置整合于同一晶片封装体内,进而缩小后续接合的电路板的尺寸。如此一来,能够进一步缩小具有感测功能的电子产品的尺寸。再者,采用晶圆级制程来制作晶片封装体,可大量生产晶片封装体,进而降低成本并节省制程时间。
以下配合图5A至5F说明本发明另一实施例的晶片封装体的制造方法,其中图5A至5F是绘示出根据本发明另一实施例的晶片封装体的制造方法的剖面示意图,且其中相同于前述图1A至1F的实施例的部件使用相同的标号并省略其说明。
请参照图5A,提供一第一基底100,其具有一第一表面100a及与其相对的一第二表面100b。为简化图式,此处仅绘示出第一基底100的单一晶片区120以及位于其中的两个导电垫140。
在本实施例中,第一基底100的每一晶片区120内还具有一感测装置160,其可邻近于第一表面100a。在一实施例中,感测装置160内的感测元件可通过第一基底100内的内连线结构而与导电垫140电性连接。为简化图式,此处仅以虚线170表示感测装置160与导电垫140之间的内连线结构。
接着,可通过沉积制程(例如,涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、微影制程及蚀刻制程,在第一基底100的第一表面100a上形成图案化的重布线层260,重布线层260延伸至感测装置160上方。在本实施例中,重布线层260与导电垫140直接或间接电性连接,且通过内连线结构中的介电材料与第一基底100电性隔离。在其他实施例中,重布线层260与内连线结构之间可形成其他介电材料层。
请参照图5B,可通过多个第一导电结构340,将一第二基底300接合于第一基底100上。第一导电结构340形成于第一表面100a上的重布线层260与第二基底300的导电垫320之间,亦即导电垫320朝向第一基底100的第一表面100a。在本实施例中,感测装置160及集成电路装置310通过导电垫140、重布线层260、第一导电结构340及导电垫320彼此电性连接。在本实施例中,第一导电结构340可为凸块(例如,接合球或导电柱)或其他适合的导电结构,且可包括铜、铝、焊料或其他适合的导电材料。举例来说,可在第二基底300中导电垫320所邻近的表面上形成光阻,其具有第一导电结构340的预定图案,并在光阻的图案内沉积前述导电材料,之后去除光阻,进而在第二基底300的导电垫320上形成第一导电结构340。接着,再利用第一导电结构340将第二基底300接合于重布线层260上。
在本实施例中,第一基底100的尺寸大于第二基底300的尺寸。再者,当第一基底100的尺寸足够大时,可在第一基底100的第一表面100a上设置一个以上具有不同集成电路功能的第二基底300。在一实施例中,第二基底300与第一基底100的感测装置160完全上下重叠。在其他实施例中,第二基底300也可与第一基底100的感测装置160部分上下重叠或未上下重叠。
接着,可通过打线接合制程,在重布线层260上形成多个第二导电结构360。在一实施例中,第二导电结构360由位于重布线层260上的接合球所构成。再者,第二导电结构360可包括金或其他适合的导电材料。在一实施例中,第二导电结构360的材料不同于第一导电结构340的材料。在一实施例中,第二导电结构360的尺寸大于第一导电结构340的尺寸。在一实施例中,第二导电结构360的形成方法不同于第一导电结构340的形成方法。在本实施例中,来自第一基底100及第二基底300的信号或其他输出电路(例如,电源供应或接地)皆经由第二导电结构360向外输出。
请参照图5C,可通过模塑成型制程或沉积制程(例如,涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程),在第一基底100的第一表面100a上形成一绝缘层400,以覆盖第二基底300、重布线层260及第二导电结构360,并围绕第一基底100与第二基底300之间的第一导电结构340。
接着,以绝缘层400作为支撑,对第一基底100的第二表面100b进行薄化制程(例如,蚀刻制程、铣削制程、机械研磨制程或化学机械研磨制程),以减少第一基底100的厚度。
请参照图5D,可通过涂布、曝光及显影制程,在薄化后的第一基底100的第二表面100b上形成一光学部件175。接着,可通过一间隔层180,将一盖板200贴附于第一基底100的第二表面100b上。间隔层180暴露出对应于感测装置160的光学部件175。
请参照图5E,可通过激光钻孔制程或微影及蚀刻制程(例如,干蚀刻制程或湿蚀刻制程),在绝缘层400内形成多个孔洞420,分别暴露出对应的第二导电结构360,因此第二导电结构360位于孔洞420的底部下方。接着,可通过沉积制程(例如,涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、微影制程及蚀刻制程,在绝缘层400上形成图案化的金属层440,且填入绝缘层400的孔洞420内,以经由孔洞420电性连接至暴露出的第二导电结构360。在本实施例中,金属层440填满绝缘层400的孔洞420。在其他实施例中,金属层440可顺应性形成于孔洞420的侧壁及底部,而未填满绝缘层400的孔洞420。
请参照图5F,可通过沉积制程(例如,涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程),在金属层440及绝缘层400上形成一钝化保护层460。接着,可通过微影制程及蚀刻制程,在每一晶片区120的钝化保护层460内形成多个第二开口480,以暴露出位于绝缘层400上的金属层440的一部分。
之后,将第三导电结构500对应地设置于钝化保护层460的第二开口480内,以直接接触暴露出的金属层440,而与金属层440电性连接。在本实施例中,第三导电结构500可为凸块(例如,接合球或导电柱)或其他适合的导电结构。举例来说,可通过电镀制程、网版印刷制程或其他适合的制程,在钝化保护层460的第二开口480内形成焊料,且进行回焊制程而形成焊球,以作为第三导电结构500。在本实施例中,第三导电结构500可包括锡、铅、铜、金、镍、前述的组合或其他适合的导电材料。
在一实施例中,第一导电结构340、第二导电结构360及第三导电结构500皆为球型,第二导电结构360的尺寸小于第三导电结构500的尺寸且大于第一导电结构340的尺寸。在一实施例中,第三导电结构500的材料不同于第二导电结构360的材料。在一实施例中,第三导电结构500的形成方法不同于第二导电结构360的形成方法。举例来说,第三导电结构500通过回焊制程所形成,而第二导电结构360通过打线接合制程所形成。
接着,沿着相邻晶片区120之间的切割道(未绘示),对盖板200、第一基底100及绝缘层400进行切割制程,以形成多个独立的晶片封装体。在本实施例中,可进一步在独立的晶片封装体的第一基底100的第一表面100a上提供一电路板(未绘示),且通过第三导电结构500将第一基底100内的感测装置160及第二基底300内的集成电路装置310电性连接至电路板。
此外,图1A至1F的实施例也可与图5A至5F的实施例互相结合。举例来说,请参照图6,可通过类似图5A的制造方法,在第一基底100的第一表面100a上形成图案化的重布线层260,但重布线层260不延伸至感测装置160上方。
接着,可通过类似图1D的制造方法,通过粘着层280将第二基底300贴附于第一基底100的第一表面100a上,并进行打线接合制程,将第一导电结构340形成于对应的导电垫320及重布线层260上,并将一个或一个以上的第二导电结构360形成于对应的导电垫320上,而将其他第二导电结构360形成于对应的重布线层260上。
接着,可通过类似图5C的制造方法,在第一基底100的第一表面100a上形成绝缘层400,以覆盖第二基底300、重布线层260、第一导电结构340及第二导电结构360。之后,以绝缘层400作为支撑,对第一基底100的第二表面100b进行薄化制程。
接着,可通过类似图5D的制造方法,在薄化后的第一基底100的第二表面100b上形成光学部件175,并通过间隔层180将盖板200贴附于第一基底100的第二表面100b上。
之后,可通过类似图1E或5E的制造方法,在绝缘层400内形成多个孔洞420,分别暴露出对应的第二导电结构360。
在本实施例中,导电垫320及重布线层260上的第二导电结构360可于形成孔洞420的制程(例如,激光钻孔制程)中作为缓冲层。再者,由于一个或一个以上的第二导电结构360形成于对应的导电垫320而非重布线层260上,因此可降低孔洞420的深度,进而可降低孔洞420的深宽比而有利于制作孔洞420。
在其他实施例中,也可将所有的第二导电结构360形成于对应的导电垫320或重布线层260上,且后续形成的所有孔洞420与对应的导电垫320或重布线层260上下重叠。
接着,可通过类似图1F或5E的制造方法,在绝缘层400上形成图案化的金属层440,且填入绝缘层400的孔洞420内。之后,可通过类似图1F或5F的制造方法,在金属层440及绝缘层400上形成钝化保护层460,且在钝化保护层460内形成多个第二开口480,并将第三导电结构500对应地设置于钝化保护层460的第二开口480内。接着,沿着相邻晶片区120之间的切割道(未绘示)进行切割制程,以形成多个独立的晶片封装体,进而可制作出图6所示的晶片封装体。
以上所述仅为本发明较佳实施例,然其并非用以限定本发明的范围,任何熟悉本项技术的人员,在不脱离本发明的精神和范围内,可在此基础上做进一步的改进和变化,因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
Claims (34)
1.一种晶片封装体,其特征在于,包括:
一第一基底,该第一基底内包括一感测装置;
一第二基底,贴附于该第一基底上,其中该第二基底内包括一集成电路装置;
一第一导电结构,通过设置于该第一基底上的一重布线层电性连接该感测装置及该集成电路装置;
一绝缘层,覆盖该第一基底、该第二基底及该重布线层,其中该绝缘层内具有一孔洞;以及
一第二导电结构,设置于该孔洞的底部下方。
2.根据权利要求1所述的晶片封装体,其特征在于,该第一基底的尺寸大于该第二基底的尺寸。
3.根据权利要求1所述的晶片封装体,其特征在于,该第一基底具有一第一表面及与该第一表面相对的一第二表面,该感测装置邻近于该第一表面,且该第二基底贴附于该第二表面,其中该第一基底内还包括:
一导电垫,邻近于该第一表面;以及
一第一开口,自该第二表面朝该第一表面延伸,并暴露出该导电垫。
4.根据权利要求3所述的晶片封装体,其特征在于,该重布线层设置于该第一基底的该第二表面上,且经由该第一开口电性连接暴露出的该导电垫,其中该第二导电结构电性连接该重布线层。
5.根据权利要求4所述的晶片封装体,其特征在于,该第二导电结构的材料相同于该第一导电结构的材料。
6.根据权利要求1所述的晶片封装体,其特征在于,还包括:
一金属层,设置于该绝缘层上,且经由该孔洞电性连接该第二导电结构;以及
一第三导电结构,电性连接该绝缘层上的该金属层。
7.根据权利要求6所述的晶片封装体,其特征在于,该第三导电结构的材料不同于该第二导电结构的材料。
8.根据权利要求6所述的晶片封装体,其特征在于,该第二导电结构及该第三导电结构为接合球。
9.根据权利要求8所述的晶片封装体,其特征在于,该第三导电结构的尺寸大于该第二导电结构的尺寸。
10.根据权利要求1所述的晶片封装体,其特征在于,该集成电路装置为一信号处理装置。
11.根据权利要求1所述的晶片封装体,其特征在于,该第一导电结构设置于该第二基底上,且延伸至该重布线层上,其中该第二导电结构设置于该第一基底上。
12.根据权利要求1所述的晶片封装体,其特征在于,该第一导电结构设置于该第二基底上,且延伸至该重布线层上,其中该第二导电结构设置于该第二基底上。
13.根据权利要求1所述的晶片封装体,其特征在于,该第一导电结构设置于该第一基底与该第二基底之间,且该第二导电结构设置于该第一基底上。
14.根据权利要求1所述的晶片封装体,其特征在于,该第一基底具有一第一表面及与该第一表面相对的一第二表面,该感测装置邻近于该第一表面,且该第二基底接合于该第一表面,其中该第一基底内还包括一导电垫,该导电垫邻近于该第一表面。
15.根据权利要求14所述的晶片封装体,其特征在于,该重布线层设置于该第一基底的该第一表面上,且电性连接该导电垫及该第二导电结构。
16.根据权利要求1所述的晶片封装体,其特征在于,该第二导电结构的材料不同于该第一导电结构的材料。
17.根据权利要求16所述的晶片封装体,其特征在于,该第二导电结构的尺寸大于该第一导电结构的尺寸。
18.一种晶片封装体的制造方法,其特征在于,包括:
提供一第一基底,其中该第一基底内包括一感测装置;
将一第二基底贴附于该第一基底上,其中该第二基底内包括一集成电路装置;
形成一第一导电结构,以通过该第一基底上的一重布线层将该感测装置电性连接至该集成电路装置;以及
形成一第二导电结构及一绝缘层,其中该绝缘层覆盖该第一基底、该第二基底及该重布线层,且该绝缘层内具有一孔洞,其中该第二导电结构位于该孔洞的底部下方。
19.根据权利要求18所述的晶片封装体的制造方法,其特征在于,该第一基底的尺寸大于该第二基底的尺寸。
20.根据权利要求18所述的晶片封装体的制造方法,其特征在于,该第一基底具有一第一表面及与该第一表面相对的一第二表面,该感测装置邻近于该第一表面,且该第二基底贴附于该第二表面,其中该第一基底内还包括一导电垫,该导电垫邻近于该第一表面,且该晶片封装体的制造方法还包括:
在该第一基底内形成一第一开口,该第一开口自该第二表面朝该第一表面延伸,且暴露出该导电垫,其中该重布线层位于该第一基底的该第二表面上,且经由该第一开口电性连接暴露出的该导电垫,且该第二导电结构电性连接该重布线层。
21.根据权利要求20所述的晶片封装体的制造方法,其特征在于,该第二导电结构的材料相同于该第一导电结构的材料。
22.根据权利要求18所述的晶片封装体的制造方法,其特征在于,还包括:
在该绝缘层上形成一金属层,其中该金属层经由该孔洞电性连接该第二导电结构;以及
在该绝缘层上的该金属层上形成一第三导电结构。
23.根据权利要求22所述的晶片封装体的制造方法,其特征在于,该第三导电结构的材料不同于该第二导电结构的材料。
24.根据权利要求22所述的晶片封装体的制造方法,其特征在于,该第二导电结构及该第三导电结构为接合球。
25.根据权利要求24所述的晶片封装体的制造方法,其特征在于,该第三导电结构的尺寸大于该第二导电结构的尺寸。
26.根据权利要求22所述的晶片封装体的制造方法,其特征在于,该第三导电结构的形成方法不同于该第二导电结构的形成方法。
27.根据权利要求18所述的晶片封装体的制造方法,其特征在于,该集成电路装置为一信号处理装置。
28.根据权利要求18所述的晶片封装体的制造方法,其特征在于,该第一导电结构形成于该第二基底上,且延伸至该重布线层上,其中该第二导电结构形成于该第一基底上。
29.根据权利要求18所述的晶片封装体的制造方法,其特征在于,该第一导电结构形成于该第二基底上,且延伸至该重布线层上,其中该第二导电结构形成于该第二基底上。
30.根据权利要求18所述的晶片封装体的制造方法,其特征在于,该第一导电结构形成于该第一基底与该第二基底之间,且该第二导电结构形成于该第一基底上。
31.根据权利要求18所述的晶片封装体的制造方法,其特征在于,该第一基底具有一第一表面及与该第一表面相对的一第二表面,该感测装置邻近于该第一表面,且该第二基底接合于该第一表面,其中该第一基底内还包括一导电垫,该导电垫邻近于该第一表面,该重布线层设置于该第一基底的该第一表面上且电性连接该导电垫及该第二导电结构。
32.根据权利要求18所述的晶片封装体的制造方法,其特征在于,该第二导电结构的材料不同于该第一导电结构的材料。
33.根据权利要求32所述的晶片封装体的制造方法,其特征在于,该第二导电结构的尺寸大于该第一导电结构的尺寸。
34.根据权利要求18所述的晶片封装体的制造方法,其特征在于,该第二导电结构的形成方法不同于该第一导电结构的形成方法。
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