CN104681516B - 晶片封装体及其制造方法 - Google Patents

晶片封装体及其制造方法 Download PDF

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Publication number
CN104681516B
CN104681516B CN201410705224.2A CN201410705224A CN104681516B CN 104681516 B CN104681516 B CN 104681516B CN 201410705224 A CN201410705224 A CN 201410705224A CN 104681516 B CN104681516 B CN 104681516B
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substrate
conductive pad
encapsulation body
wafer encapsulation
conductive
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CN104681516A (zh
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刘建宏
温英男
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XinTec Inc
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XinTec Inc
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Abstract

本发明揭露一种晶片封装体及其制造方法。该晶片封装体包括：一第一基底，其中多个第一导电垫设置于第一基底的一第一侧上；一第二基底，贴附于相对于第一基底的第一侧的一第二侧上，其中第二基底具有一微电子元件，且具有对应第一导电垫的多个第二导电垫，所述第二导电垫设置于第二基底的一第一侧上，且位于第一基底与第二基底之间；一重布线层，设置于相对于第二基底的第一侧的一第二侧上，且穿过第二基底、第二导电垫及第一基底而延伸至第一导电垫内，以与第一导电垫及第二导电垫电性连接。本发明通过重布线层进行电性连接而不需使用焊线，缩小了晶片封装体的尺寸，降低了成本。

Description

晶片封装体及其制造方法
技术领域
本发明有关于一种晶片封装体及其制造方法，特别为有关于以晶圆级封装制程所形成的晶片封装体。
背景技术
晶片封装制程是形成电子产品过程中的重要步骤。晶片封装体除了将晶片保护于其中，使免受外界环境污染外，还提供晶片内部电子元件与外界的电性连接通路。
制作晶片封装体的过程包括将晶圆基底切割为多个晶片之后，将晶片放置于尺寸大于晶片的导线架(lead frame)上，接着通过金焊线将晶片上的导电垫电性连接至导线架的接合垫，以形成晶片的外部电性连接的路径。
然而，由于使用金焊线及导线架作为外部电性连接的路径，成本较高，且使得晶片封装体的整体尺寸增加，因此难以进一步缩小晶片封装体的尺寸。
因此，有必要寻求一种新颖的晶片封装体及其制造方法，其能够解决或改善上述的问题。
发明内容
本发明实施例提供一种晶片封装体，包括：一第一基底，其中多个第一导电垫设置于第一基底的一第一侧上；一第二基底，贴附于相对于第一基底的第一侧的一第二侧上，其中第二基底具有一微电子元件，且具有对应第一导电垫的多个第二导电垫，所述第二导电垫设置于第二基底的一第一侧上，且位于第一基底与第二基底之间；一重布线层，设置于相对于第二基底的第一侧的一第二侧上，且穿过第二基底、第二导电垫及第一基底而延伸至第一导电垫内，以与第一导电垫及第二导电垫电性连接。
本发明实施例提供一种晶片封装体的制造方法，包括：提供一第一基底，其中多个第一导电垫设置于第一基底的一第一侧上；将一第二基底贴附于相对于第一基底的第一侧的一第二侧上，其中第二基底具有一微电子元件，且具有对应第一导电垫的多个第二导电垫，所述第二导电垫设置于第二基底的一第一侧上，且位于第一基底与第二基底之间；在相对于第二基底的第一侧的一第二侧上形成一重布线层，其中重布线层穿过第二基底、第二导电垫及第一基底而延伸至第一导电垫内，以与第一导电垫及第二导电垫电性连接。
本发明通过重布线层进行电性连接而不需使用焊线，缩小了晶片封装体的尺寸，降低了成本。
附图说明
图1A至1G绘示出根据本发明一实施例的晶片封装体的制造方法的剖面示意图。
图2A至2G绘示出根据本发明另一实施例的晶片封装体的制造方法的剖面示意图。
其中，附图中符号的简单说明如下：
100、600：第一基底；100a、300a、600a：第一侧；100b、300b、600b：第二侧；120、320、620：介电层；140、340、640：导电垫；180、380、420、465、680：开口；200：第三基底；220：第一层；250、650：光学部件；260：第二层/围堰；265：空腔；280：盖板；300：第二基底；360：粘着层；310：电子元件区；400、460：绝缘层；440：重布线层；480：导电结构；500、700：晶片封装体；SC：切割道。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定形式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关连性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装微机电系统晶片。然其应用不限于此，例如在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(optoelectronic devices)、微机电系统(Micro Electro Mechanical System；MEMS)、微流体系统(micro fluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package；WSP)制程对影像感测装置、发光二极管(light-emitting diodes；LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(microactuators)、表面声波元件(surface acoustic wave devices)、压力感测器(processsensors)或喷墨头(ink printer heads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layerintegrated circuit devices)的晶片封装体。
请参照图1G，其绘示出根据本发明一实施例的晶片封装体500的剖面示意图。在本实施例中，晶片封装体500包括一第一基底100、一第二基底300及一重布线层440。第一基底100具有一第一侧100a及与其相对的一第二侧100b。在本实施例中，第一基底100可由空白晶圆(raw wafer)所构成，且不具有任何有源、无源元件或微电子元件。
第二基底300贴附于第一基底100的第二侧100b上，且具有一微电子元件(未绘示)位于一电子元件区310内。在一实施例中，微电子元件可为数字信号处理(digital signalprocessor，DSP)元件或其他适合的微电子元件。
第二基底300具有一第一侧300a及与其相对的一第二侧300b，且具有一介电层320及位于介电层320内的多个第二导电垫340，设置于第二基底300的第一侧300a上，且位于第一基底100与第二基底300之间。在本实施例中，第二基底300具有多个开口380(绘示于图1E及1F)，对应于每一第二导电垫340。在一实施例中，第二基底300为一半导体晶圆(例如，硅晶圆)，以利于进行晶圆级封装制程。在另一实施例中，第二基底300为一半导体晶片。在一实施例中，第二导电垫340可为单层导电层或具有多层的导电层结构，且通过内连线结构(未绘示)而与电子元件区310内的微电子元件电性连接。
一粘着层360设置于第一基底100与第二基底300的介电层320之间，以将第二基底300贴附于第一基底100。在一实施例中，粘着层360可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
一绝缘层400设置于第二基底300的第二侧300b上，且填入第二基底300的开口380(绘示于图1E及1F)内。在一实施例中，绝缘层400可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
一第三基底200贴附于第一基底100的第一侧100a上，且具有一光学部件250设置于其上。在一实施例中，第三基底200包括一背照式(back side illumination，BSI)互补型金属氧化物半导体影像感测(complementary metal oxide semiconductor imagesensor，CIS)装置(未绘示)。在一实施例中，第三基底200为一半导体晶圆(例如，硅晶圆)，以利于进行晶圆级封装制程。在另一实施例中，第三基底200为一半导体晶片。在一实施例中，光学部件250可为用于影像感测装置的微透镜阵列或其他适合的光学部件。
第三基底200具有一介电层120及位于介电层120内的多个第一导电垫140，第一导电垫140对应于第二导电垫340且设置于第一基底100与第三基底200之间(即，位于第一基底100的第一侧100a上)。在一实施例中，第一导电垫140可为单层导电层或具有多层的导电层结构，且通过内连线结构(未绘示)而与影像感测装置(未绘示)电性连接。
在本实施例中，第一基底100具有多个开口180(绘示于图1C及1D)，对应地暴露出每一第一导电垫140。设置于第一基底100与第二基底300之间的粘着层360填入于第一基底100的开口180内。
一间隔层对应于第一导电垫140而设置于第三基底200的介电层120上(即，位于第一基底100的第一侧100a上)，且包括第一层(或围堰(dam))260及第二层220。在一实施例中，第一层260及第二层220可分别包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂(polyimide)、苯环丁烯(butylcyclobutene，BCB)、聚对二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))或其他适合的绝缘材料。
一盖板280设置于围堰260上。位于第三基底200与盖板280之间的围堰260在其间形成一空腔265，使得光学部件250位于空腔265内的第三基底200上，且通过盖板280保护光学部件250。在一实施例中，盖板280可包括玻璃或其他适合的材料。
在一实施例中，多个开口420位于第二基底300的开口380(绘示于图1E及1F)内，且穿过对应的第二导电垫340、第一基底100的开口180(绘示于图1C及1D)及对应的第一导电垫140而延伸至间隔层的第二层220内。重布线层440设置于第二基底300的第二侧300b上，且延伸进入开口420内，而穿过第二导电垫340及第一导电垫140，并延伸至间隔层的第二层220内，以与第一导电垫140及第二导电垫340电性连接。开口420内的重布线层440也称为硅通孔电极(through silicon via，TSV)。在一实施例中，重布线层440可包括铜、铝、金、铂或其他适合的导电材料。
在另一实施例中，开口420可还延伸至间隔层的第一层260内，使得重布线层440也还延伸至第一层260内(未绘示)。又另一实施例中，开口420可穿过第一导电垫140，而未延伸至间隔层内，使得重布线层440也未延伸至间隔层内(未绘示)。又另一实施例中，开口420可延伸至第一导电垫140内，而未穿过第一导电垫140，使得重布线层440也未穿过第一导电垫140(未绘示)。
在本实施例中，重布线层440以环型接触(ring-contact)的方式电性连接第一导电垫140及第二导电垫340。在本实施例中，重布线层440通过绝缘层400与第二基底300电性隔离，且通过粘着层360与第一基底100电性隔离。
在本实施例中，晶片封装体500还包括一绝缘层460(例如，钝化护层)及一导电结构480(例如，焊球、凸块或导电柱)，设置于第二基底300的第二侧300b上。绝缘层460覆盖重布线层440，且具有多个开口465，以暴露出重布线层440的一部分。在一实施例中，绝缘层460可包括环氧树脂、绿漆(soldermask)、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
在一实施例中，绝缘层460经由开口420穿过第二基底300、第二导电垫340、第一基底100及第一导电垫140，而延伸至间隔层的第二层220内。在另一实施例中，绝缘层460还延伸至间隔层的第一层260内(未绘示)。又另一实施例中，绝缘层460未延伸至间隔层内(未绘示)。又另一实施例中，绝缘层460未穿过第一导电垫140(未绘示)。
导电结构480填入于绝缘层460的开口465内，以与重布线层440电性连接。在一实施例中，导电结构480可包括锡、铅、铜、金、镍、或前述的组合。
请参照图2G，其绘示出根据本发明另一实施例的晶片封装体700的剖面示意图，其中相同于图1G中的部件使用相同的标号并省略其说明。在本实施例中，晶片封装体700包括一第一基底600、一第二基底300及一重布线层440。不同于图1G的晶片封装体500中的第一基底100由空白晶圆所构成，且不具有任何有源或无源元件，在本实施例中，第一基底600具有一介电层620及位于介电层620内的多个第一导电垫640，设置于第一基底600的第一侧600a上，且具有一光学部件650设置于介电层620上。在一实施例中，第一基底600包括一前照式(front side illumination，FSI)互补型金属氧化物半导体影像感测(CIS)装置(未绘示)。在一实施例中，第一基底600为一半导体晶圆(例如，硅晶圆)，以利于进行晶圆级封装制程。在另一实施例中，第一基底600为一半导体晶片。在一实施例中，光学部件650可为用于影像感测装置的微透镜阵列或其他适合的光学部件。在一实施例中，第一导电垫640可为单层导电层或具有多层的导电层结构，且通过内连线结构(未绘示)而与影像感测装置(未绘示)电性连接。
在本实施例中，第一基底600具有多个开口680(绘示于图2C及2D)，对应地暴露出每一第一导电垫640。设置于第一基底600与第二基底300之间的粘着层360填入于第一基底600的开口680内。
不同于图1G的晶片封装体500中的间隔层包括第一层260及第二层220，在本实施例中，间隔层由一围堰260所构成，其对应于第一导电垫640而设置于第一基底600的介电层620上(即，位于第一基底600的第一侧600a上)。一盖板280设置于围堰260上。位于第一基底600与盖板280之间的围堰260在其间形成一空腔265，使得光学部件650位于空腔265内的第一基底600上，且通过盖板280保护光学部件650。
在本实施例中，晶片封装体700中的重布线层440经由开口420穿过第二基底300、第二导电垫340、第一基底600及第一导电垫640而延伸至围堰260内。在另一实施例中，重布线层440可穿过第一导电垫640，而未延伸至围堰260内(未绘示)。又另一实施例中，重布线层440可延伸至第一导电垫640内，而未穿过第一导电垫640(未绘示)。
根据本发明的上述实施例，将互补式金属氧化物半导体影像感测(CIS)装置及数字信号处理(DSP)元件垂直堆叠，且开口420穿过第二基底300、对应的第二导电垫340及第一基底100/600而延伸至对应的第一导电垫140/640内，因此可通过延伸至开口420内的重布线层440电性连接互补式金属氧化物半导体影像感测装置与数字信号处理元件，且以硅通孔电极(即，重布线层440)作为晶片封装体的外部电性连接的路径，而不需使用焊线及导线架，能够节省成本，并使得结合互补式金属氧化物半导体影像感测装置及数字信号处理元件的晶片封装体的尺寸能够进一步缩小。
以下配合图1A至1G说明本发明一实施例的晶片封装体的制造方法，其中图1A至1G绘示出根据本发明一实施例的晶片封装体500的制造方法的剖面示意图。
请参照图1A，提供一第一基底100，其具有一第一侧100a及与其相对的一第二侧100b。在本实施例中，第一基底100可由空白晶圆所构成，且不具有任何有源、无源元件或微电子元件。
一第三基底200贴附于第一基底100的第一侧100a上，且具有一光学部件250设置于其上。在一实施例中，第三基底200包括一背照式(BSI)互补型金属氧化物半导体影像感测(CIS)装置(未绘示)。在一实施例中，第三基底200为一半导体晶圆(例如，硅晶圆)，以利于进行晶圆级封装制程。在一实施例中，光学部件250可为用于影像感测装置的微透镜阵列或其他适合的光学部件。
第三基底200具有一介电层120及位于介电层120内的多个第一导电垫140，设置于第一基底100与第三基底200之间(即，位于第一基底100的第一侧100a上)。在一实施例中，第一导电垫140可为单层导电层或具有多层的导电层结构，且通过内连线结构(未绘示)而与影像感测装置(未绘示)电性连接。
一间隔层对应于第一导电垫140而设置于第三基底200的介电层120上。在本实施例中，间隔层可包括位于介电层120上的一第二层220及位于第二层220上的一第一层(或围堰)260，如图1B所示。在一实施例中，第二层220可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯(BCB)、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)，在第三基底200上形成第一层260，使第一层260对应于第一导电垫140。在一实施例中，第一层260可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯(BCB)、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
接着，在围堰260上提供一盖板280，以在第三基底200与盖板280之间形成一空腔265，使得光学部件250位于空腔265内的第三基底200上，且通过盖板280保护光学部件250。在一实施例中，盖板280可包括玻璃或其他适合的材料。
请参照图1C，以盖板280作为承载基板，对第一基底100的第二侧100b的表面进行薄化制程(例如，蚀刻制程、铣削(milling)制程、磨削(grinding)制程或研磨(polishing)制程)，以减少第一基底100的厚度。
接着，通过微影制程及蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、等离子蚀刻制程、反应性离子蚀刻制程或其他适合的制程)，在第一基底100内形成多个开口180，对应地暴露出每一第一导电垫140。
请参照图1D，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)，在第一基底100的第二侧100b上形成一粘着层360，且填入于第一基底100的开口180内。在一实施例中，粘着层360可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
接着，通过粘着层360，将一第二基底300贴附于第一基底100的第二侧100b上。第二基底300具有一微电子元件(未绘示)位于一电子元件区310内。在一实施例中，微电子元件可为数字信号处理(DSP)元件或其他适合的微电子元件。第二基底300具有一第一侧300a及与其相对的一第二侧300b，且具有一介电层320及位于介电层320内的多个第二导电垫340。第二导电垫340对应于第一导电垫140，且设置于第二基底300的第一侧300a上以及位于第一基底100与第二基底300之间。
请参照图1E，以盖板280作为承载基板，对第二基底300的第二侧300b的表面进行薄化制程(例如，蚀刻制程、铣削制程、磨削制程或研磨制程)，以减少第二基底300的厚度。
接着，通过微影制程及蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、等离子蚀刻制程、反应性离子蚀刻制程或其他适合的制程)，在第二基底300内形成多个开口380，对应于每一第二导电垫340。在一实施例中，第二基底300为一半导体晶圆(例如，硅晶圆)，以利于进行晶圆级封装制程。在一实施例中，第二导电垫340可为单层导电层或具有多层的导电层结构，且通过内连线结构(未绘示)而与电子元件区310内的微电子元件电性连接。
请参照图1F，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)，在第二基底300的第二侧300b上形成一绝缘层400，且填入于第二基底300的开口380内。在一实施例中，绝缘层400可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
接着，可通过激光钻孔制程、蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、等离子蚀刻制程、反应性离子蚀刻制程)或其他适合的制程，在每一开口380(绘示于图1E及1F)内的绝缘层400内形成一开口420。
接着，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、微影制程及蚀刻制程，在第二基底300的第二侧300b上形成图案化的重布线层440，且延伸进入每一开口420内。在一实施例中，重布线层440可包括铜、铝、金、铂或其他适合的导电材料。
在一实施例中，开口420穿过对应的第二导电垫340、第一基底100的开口180(绘示于图1C及1D)及对应的第一导电垫140而延伸至间隔层的第二层220内，因而重布线层440也穿过对应的第二导电垫340及第一导电垫140，并延伸至间隔层的第二层220内，以与第一导电垫140及第二导电垫340电性连接。
在另一实施例中，开口420可还延伸至间隔层的第一层260内，使得重布线层440也还延伸至间隔层的第一层260内(未绘示)。又另一实施例中，开口420可穿过第一导电垫140，而未延伸至间隔层内，使得重布线层440也未延伸至间隔层内(未绘示)。又另一实施例中，开口420可延伸至第一导电垫140内，而未穿过第一导电垫140，使得重布线层440也未穿过第一导电垫140(未绘示)。
在本实施例中，重布线层440以环型接触(ring-contact)的方式电性连接第一导电垫140及第二导电垫340。在本实施例中，重布线层440通过绝缘层400与第二基底300电性隔离，且通过粘着层360与第一基底100电性隔离。
请参照图1G，可通过沉积制程，在第二基底300的第二侧300b上形成绝缘层460(例如，钝化护层)，以覆盖重布线层440。在一实施例中，绝缘层460填入开口420而穿过第二基底300、对应的第二导电垫340、第一基底100及对应的第一导电垫140，并延伸至间隔层的第二层220内。在另一实施例中，绝缘层460还延伸至间隔层的第一层260内(未绘示)。又另一实施例中，绝缘层460未延伸至间隔层内(未绘示)。又另一实施例中，绝缘层460未穿过第一导电垫140(未绘示)。在一实施例中，绝缘层460可包括环氧树脂、绿漆、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
接着，可通过微影制程及蚀刻制程，在绝缘层460内形成开口465，以暴露出图案化的重布线层440的一部分。接着，在绝缘层460的开口465内填入导电结构480(例如，焊球、凸块或导电柱)，以与图案化的重布线层440电性连接。举例来说，可通过电镀制程、网版印刷制程或其他适合的制程，在绝缘层460的开口465内形成焊料(solder)，且进行回焊(reflow)制程，以形成导电结构480。在一实施例中，导电结构480可包括锡、铅、铜、金、镍、或前述的组合。接着，沿着切割道SC，切割第二基底300、第一基底100及盖板280，以形成多个独立的晶片封装体500。
以下配合图2A至2G说明本发明另一实施例的晶片封装体的制造方法。图2A至2G绘示出根据本发明另一实施例的晶片封装体700的制造方法的剖面示意图，其中相同于图1A至1G中的部件使用相同的标号并省略其说明。
请参照图2A，提供一第一基底600，其具有一第一侧600a及与其相对的一第二侧600b。在本实施例中，第一基底600具有一介电层620及位于介电层620内的多个第一导电垫640，设置于第一基底600的第一侧600a上，且具有一光学部件650设置于介电层620上。在一实施例中，第一基底600包括一前照式(FSI)互补型金属氧化物半导体影像感测(CIS)装置(未绘示)。在一实施例中，第一基底600为一半导体晶圆(例如，硅晶圆)，以利于进行晶圆级封装制程。在一实施例中，光学部件650可为用于影像感测装置的微透镜阵列或其他适合的光学部件。在一实施例中，第一导电垫640可为单层导电层或具有多层的导电层结构，且通过内连线结构(未绘示)而与影像感测装置(未绘示)电性连接。
请参照图2B，可通过与图1B相同或相似的步骤，在第一基底600的介电层620上(即，第一基底600的第一侧600a上)形成一围堰260，其对应于第一导电垫640。接着，在围堰260上提供一盖板280，以在第一基底600与盖板280之间形成一空腔265，使得光学部件650位于空腔265内的第一基底600上，且通过盖板280保护光学部件650。
请参照图2C至2E，可通过与图1C至1E相同或相似的步骤，薄化第一基底600且于其中形成多个开口680，对应地暴露出每一第一导电垫640，如图2C所示。接着，在第一基底600的第二侧600b上形成一粘着层360，且填入于第一基底600的开口680内，并通过粘着层360，将一第二基底300贴附于第一基底600的第二侧600b上，如图2D所示。在薄化第二基底300之后，在第二基底300内形成多个开口380，对应于第二基底300的每一第二导电垫340，如图2E所示。
第二基底300具有一微电子元件(未绘示)位于一电子元件区310内。在一实施例中，微电子元件可为数字信号处理(DSP)元件或其他适合的微电子元件。
请参照图2F至2G，可通过与图1F至1G相同或相似的步骤，依序在第二基底300的第二侧300b上形成一绝缘层400、多个开口420以及图案化且填入开口420内的重布线层440，如图2F所示。接着，依序形成具有多个开口465的一绝缘层460以及填入开口465内的导电结构480，并沿着切割道SC，切割第二基底300、第一基底600及盖板280，以形成多个独立的晶片封装体700，如图2G所示。
在本实施例中，重布线层440经由开口420穿过第二基底300、第二导电垫340、第一基底600及第一导电垫640而延伸至围堰260内。在另一实施例中，重布线层440可穿过第一导电垫640，而未延伸至围堰260内(未绘示)。又另一实施例中，重布线层440可延伸至第一导电垫640内，而未穿过第一导电垫640(未绘示)。
根据本发明的上述实施例，由于将互补式金属氧化物半导体影像感测装置及数字信号处理元件垂直堆叠，且通过激光钻孔制程，形成开口420，以穿过第二基底300、第二导电垫340及第一基底100/600而延伸至第一导电垫140/640内。因此，可通过延伸至开口420内的重布线层440电性连接互补式金属氧化物半导体影像感测装置与数字信号处理元件，而不需使用焊线，使得结合互补式金属氧化物半导体影像感测装置及数字信号处理元件的晶片封装体的尺寸能够进一步缩小，且降低成本。另外，采用晶圆级制程来制作晶片封装体，可大量生产晶片封装体，进而降低成本并节省制程时间。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (15)

1.一种晶片封装体，其特征在于，包括：
一第一基底，其中多个第一导电垫设置于该第一基底的一第一侧上；
一影像感测装置，设置于该第一基底的该第一侧上，且该影像感测装置与所述第一导电垫电性连接；
一第二基底，贴附于相对于该第一基底的该第一侧的一第二侧上，其中该第二基底具有一数字信号处理元件，且具有对应于所述第一导电垫的多个第二导电垫，所述第二导电垫设置于该第二基底的一第一侧上，且位于该第一基底与该第二基底之间，该数字信号处理元件与所述第二导电垫电性连接，该第二基底还具有对应于所述第二导电垫的其中之一的一第一开口；
一第二开口，经由该第一开口而穿过该第二基底、所述第二导电垫及该第一基底，且具有小于该第一开口的宽度；以及
一重布线层，设置于相对于该第二基底的该第一侧的一第二侧上，且延伸至该第二开口内，并穿过该第二基底、所述第二导电垫、该第一基底及所述第一导电垫，以与所述第一导电垫及所述第二导电垫电性连接。
2.根据权利要求1所述的晶片封装体，其特征在于，该第一基底为一空白晶圆。
3.根据权利要求1所述的晶片封装体，其特征在于，还包括：
一粘着层，将该第二基底贴附于该第一基底；以及
一绝缘层，设置于该第二基底的该第二侧上。
4.根据权利要求3所述的晶片封装体，其特征在于，该重布线层穿过该粘着层及该绝缘层。
5.根据权利要求1所述的晶片封装体，其特征在于，还包括一间隔层，该间隔层设置于该第一基底的该第一侧上，其中该重布线层还延伸进入该间隔层内。
6.根据权利要求1所述的晶片封装体，其特征在于，还包括一绝缘层，该绝缘层设置于该第二基底的该第二侧上，以覆盖该重布线层，其中该绝缘层穿过该第二基底、所述第二导电垫及该第一基底而延伸至所述第一导电垫内。
7.根据权利要求6所述的晶片封装体，其特征在于，该绝缘层还延伸穿过所述第一导电垫。
8.一种晶片封装体的制造方法，其特征在于，包括：
提供一第一基底，其中多个第一导电垫设置于该第一基底的一第一侧上；
在该第一基底的该第一侧上设置一影像感测装置，且该影像感测装置与所述第一导电垫电性连接；
将一第二基底贴附于相对于该第一基底的该第一侧的一第二侧上，其中该第二基底具有一数字信号处理元件，且具有对应于所述第一导电垫的多个第二导电垫，所述第二导电垫设置于该第二基底的一第一侧上，且位于该第一基底与该第二基底之间，该数字信号处理元件与所述第二导电垫电性连接；
形成穿过该第二基底的一第一开口，该第一开口对应于所述第二导电垫的其中之一；
形成经由所述第一开口而穿过该第二基底、所述第二导电垫及该第一基底的一第二开口，该第二开口具有小于该第一开口的宽度；以及
在相对于该第二基底的该第一侧的一第二侧上形成一重布线层，其中该重布线层延伸至所述第二开口内，并穿过该第二基底、所述第二导电垫、该第一基底及所述第一导电垫，以与所述第一导电垫及所述第二导电垫电性连接。
9.根据权利要求8所述的晶片封装体的制造方法，其特征在于，该第一基底为一空白晶圆。
10.根据权利要求8所述的晶片封装体的制造方法，其特征在于，通过一粘着层将该第二基底贴附于该第一基底。
11.根据权利要求10所述的晶片封装体的制造方法，其特征在于，还包括：
在形成该重布线层之前，在该第二基底的该第二侧上形成一绝缘层，
其中，该第二开口穿过该绝缘层及该粘着层。
12.根据权利要求8所述的晶片封装体的制造方法，其特征在于，通过激光钻孔制程形成该第二开口。
13.根据权利要求8所述的晶片封装体的制造方法，其特征在于，还包括在该第一基底的该第一侧上形成一间隔层，其中该重布线层还延伸进入该间隔层内。
14.根据权利要求8所述的晶片封装体的制造方法，其特征在于，还包括在该第二基底的该第二侧上形成一绝缘层，以覆盖该重布线层，其中该绝缘层穿过该第二基底、所述第二导电垫及该第一基底而延伸至所述第一导电垫内。
15.根据权利要求14所述的晶片封装体的制造方法，其特征在于，该绝缘层还延伸穿过所述第一导电垫。
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