CN107611099A - 包括多个半导体裸芯的扇出半导体装置 - Google Patents

包括多个半导体裸芯的扇出半导体装置 Download PDF

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Publication number
CN107611099A
CN107611099A CN201610546249.1A CN201610546249A CN107611099A CN 107611099 A CN107611099 A CN 107611099A CN 201610546249 A CN201610546249 A CN 201610546249A CN 107611099 A CN107611099 A CN 107611099A
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Prior art keywords
bare chip
semiconductor
naked core
semiconductor bare
moulding compound
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CN201610546249.1A
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CN107611099B (zh
Inventor
张聪
肖富强
许斌
吴海军
邱进添
周增钰
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SanDisk Information Technology Shanghai Co Ltd
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SanDisk Information Technology Shanghai Co Ltd
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Priority to CN201610546249.1A priority Critical patent/CN107611099B/zh
Priority to US15/619,895 priority patent/US10177119B2/en
Priority to KR1020170079148A priority patent/KR101963025B1/ko
Publication of CN107611099A publication Critical patent/CN107611099A/zh
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Abstract

公开的一种半导体封装体包括多个堆叠的半导体裸芯，该多个堆叠的半导体裸芯通过引线键合体彼此电连接。该堆叠的半导体裸芯提供在模塑料中，使得在裸芯堆叠体中的顶部裸芯和模塑料的表面之间存在间隔。至顶部裸芯的引线键合体可以提供在间隔中。再分配层垫被固定到模塑料的表面。成列的凸块可以形成在裸芯堆叠体中的顶部裸芯的裸芯接合垫上，以穿过间隔将再分配层垫电耦合到裸芯堆叠体。

Description

包括多个半导体裸芯的扇出半导体装置
技术领域
本公开涉及半导体封装体。
背景技术
对便携式消费电子产品的需求的强劲增长推动了对大容量存储装置的需求。非易失性半导体存储器装置(诸如闪存存储卡)正变得广泛地使用，以满足对数字信息存储和交换的日益增长的需求。它们的便携性、多功能性和坚固的设计以其高可靠性和大容量已经使这样的存储器装置理想地用于各种电子装置中，所述各种电子装置例如包括数码相机、数码音乐播放器、视频游戏机、PDA和移动电话。
虽然很多不同的封装配置是已知的，闪存存储卡一般可以制造为系统级封装(SiP)或多芯片模块(MCM)，在这种情形下，多个裸芯被安装和互连在小印迹基板上。基板一般可以包括具有导电层的刚性、电介质基体，该导电层在一侧或两侧上被蚀刻。在裸芯和(多个)导电层之间形成电连接，并且(多个)导电层为提供用于将裸芯连接至主机装置的电引线结构。一旦完成裸芯和基板之间的电连接，该组件则通常被包封在模塑料(moldcompound)中，该模塑料提供保护性封装体。
一种类型的半导体封装体是所谓的扇出(fan out)芯片级封装体，在这种情形下，半导体裸芯被嵌入在模塑料中，该半导体裸芯的有源表面包括与模塑料的表面共面的裸芯接合垫。再分配层的第一表面之后被固定到半导体裸芯的有源表面和模塑料。再分配层包括第二表面，该第二表面具有用于将扇出封装体安装到主机装置的焊料球。
图1中示出了常规的扇出芯片级半导体封装体20的截面侧视图。封装体20包括半导体裸芯，诸如闪存裸芯22。半导体裸芯22可以被包封在模塑料24中，裸芯22的表面26包括与模塑料24的表面共面的裸芯接合垫28。之后可以将再分配层30固定到裸芯22和模塑料24的共面表面。再分配层30经由再分配层30内的电迹线34和通孔36将裸芯22的裸芯接合垫28电连接到焊料凸块32。焊料凸块32可以表面安装到主机装置(诸如印刷电路板)以将封装体20与主机装置电连接。
在扇出芯片级封装体(诸如封装体20)中，有用于单个半导体裸芯(即，直接靠着再分配层30的半导体裸芯22)的空间。由于裸芯22的裸芯接合垫28直接靠着再分配层30的相邻表面中的电接触，因此没有空间用于附加裸芯到再分配层30的电连接。
发明内容
总的来说，在一个示例中，本技术涉及一种半导体封装体，其包括：多个堆叠的半导体裸芯，每个半导体裸芯包括裸芯接合垫，多个堆叠的半导体裸芯包括在堆叠的半导体裸芯的顶部的第一半导体裸芯；模塑料，多个半导体裸芯包封在模塑料内，以便包括裸芯接合垫的第一半导体裸芯的表面在模塑料内，并且与模塑料的表面分隔开；引线键合体，其被固定在多个堆叠的半导体裸芯的裸芯接合垫上，引线键合体电耦合多个堆叠的半导体裸芯；成列的一个或多个凸块，其形成在第一半导体裸芯上的裸芯接合垫处的引线键合体的顶部，每列的一个或多个凸块具有通过模塑料的表面暴露的凸块的表面；再分配层垫，其被固定到模塑料的表面，该再分配层垫包括：在再分配层垫的第一表面上的接触垫，该接触垫与模塑料的表面处的每列的暴露的凸块相配合，在再分配层垫的第二表面上的焊料凸块，以及导电图案，其用于将再分配层垫的第一表面上的接触垫与再分配层垫的第二表面上的所选择的那些焊料凸块电连接。
在另外的示例中，本技术涉及一种半导体封装体，其包括：多个堆叠的半导体裸芯，每个半导体裸芯包括裸芯接合垫，多个堆叠的半导体裸芯包括在堆叠的半导体裸芯的顶部的第一半导体裸芯；模塑料，多个半导体裸芯包封在模塑料内，包括裸芯接合垫的第一半导体裸芯的表面嵌入在模塑料内，以限定第一半导体裸芯的表面和模塑料的表面之间的间隔；引线键合体，其被固定在堆叠的半导体裸芯的裸芯接合垫上，引线键合体电耦合多个堆叠的半导体裸芯，至第一半导体裸芯上的裸芯接合垫的引线键合体被提供在第一半导体裸芯的表面和模塑料的表面之间的间隔中；成列的一个或多个凸块，其形成在第一半导体裸芯上的裸芯接合垫处的引线键合体的顶部，每列的一个或多个凸块填充第一半导体裸芯的表面和模塑料的表面之间的间隔；再分配层垫，其被固定到模塑料的表面，该再分配层垫包括：在再分配层垫的第一表面上的接触垫，该接触垫与模塑料的表面处的每列的暴露的凸块相配合，在再分配层垫的第二表面上的焊料凸块，以及导电图案，其用于将再分配层垫的第一表面上的接触垫与再分配层垫的第二表面上的选择的那些焊料凸块电连接。
在又一个示例中，本技术涉及一种扇出半导体封装体，其包括：多个堆叠的半导体裸芯，每个半导体裸芯包括裸芯接合垫，多个堆叠的半导体裸芯包括在堆叠的半导体裸芯的顶部的第一半导体裸芯；模塑料，多个半导体裸芯包封在模塑料内，包括裸芯接合垫的第一半导体裸芯的表面嵌入在模塑料内，以限定第一半导体裸芯的表面和模塑料的表面之间的间隔；引线键合体，其被固定在多个堆叠的半导体裸芯的裸芯接合垫上，引线键合体电耦合多个堆叠的半导体裸芯，至第一半导体裸芯上的裸芯接合垫的引线键合体被提供在第一半导体裸芯的表面和模塑料的表面之间的间隔中；再分配层垫，其被固定到模塑料的表面，该再分配层垫包括：在再分配层垫的第一表面上的接触垫，在再分配层垫的第二表面上的焊料凸块，以及导电图案，其用于将再分配层垫的第一表面上的接触垫与再分配层垫的第二表面上的所选择的那些焊料凸块电连接；以及装置，该装置被提供在间隔中以将再分配层垫的接触垫与第一半导体裸芯的裸芯接合垫电耦合。
附图说明
图1是常规扇出芯片级半导体封装体的截面边视图。
图2是根据本技术的实施例的半导体装置的组装的流程图。
图3和图4分别是根据本技术的实施例制造半导体装置的第一中间阶段的该半导体装置的局部透视图和边视图。
图5和图6分别是根据本技术的实施例制造半导体装置的第二中间阶段的该半导体装置的局部透视图和边视图。
图6A是根据本技术的实施例的包括一列凸块的上部半导体裸芯的局部放大边视图。
图7和图8分别是根据本技术的实施例制造半导体装置的第一中间阶段的该半导体装置的局部透视图和边视图。
图9和图10分别是根据本技术的实施例制造半导体装置的第一中间阶段的该半导体装置的局部透视图和边视图。
图11是根据本技术的实施例所制造的半导体装置的面板的局部透视图。
图12是示出了将载体与根据本技术的实施例所制造的半导体装置分离的边视图。
图13是根据本技术的实施例固定到主机装置的半导体装置的边视图。
图14是常规的基板半导体封装体的侧视图。
具体实施方式
现在将参照附图来描述本技术，在实施中，本技术涉及包括多个半导体裸芯的扇出半导体装置。可以理解的是，本发明可以以很多不同的形式来实施，而不应被理解为限于本文所阐述的实施例。确切地说，提供这些实施例使得本公开将是透彻和完整的，并将完全地向本领域的技术人员传达本发明。实际上，本发明旨在覆盖这些实施例的替代、修改和等同，这些实施例的替代、修改和等同被包括在由所附权利要求限定的本发明的范围和精神之内。此外，在本发明的以下详细描述中，提出许多具体的细节以便提供本发明的透彻理解。然而，对本领域的普通技术人员将清楚的是，本发明可以在没有这样的具体细节的情况下来实践。
如可以在本文中使用的术语“顶部”和“底部”、“上部”和“下部”以及“垂直”和“水平”仅为示例和说明性目的，并非意味着限制本发明，因为所引用的项目可以在位置和取向上进行交换。此外，如本文所使用的术语“大致上”、“近似”和/或“大约”的意思是，指定的尺寸或参数对于给定的应用可以在可接受的制造公差内变化。在一个实施例中，可接受的制造公差为±0.25％。
现在将参照图2的流程图及图3到图13的局部透视图和边视图来进行解释本发明的实施例。图3到图10每个示出了单独的半导体封装体100或其部分。然而，如关于图11的下述说明，封装体100可以与载体上的多个其他封装体一起成批处理，以实现规模经济。载体上的封装体100的行和列的数量可以变化。
现在参照图2的流程图及图3和图4的视图，半导体封装体100的制造可以以步骤200开始，在该步骤200中，在刚性载体112上堆叠多个半导体裸芯104。半导体裸芯104可以例如是存储器裸芯，诸如NAND闪存裸芯，但是可以使用其他类型的裸芯104。半导体裸芯104可以以偏移阶梯配置上下叠置，以形成裸芯堆叠体110。在所示的示例中，半导体封装体100包括四个半导体裸芯104。然而，在另外的实施例中，裸芯堆叠体110可以包括多于四个半导体裸芯或少于四个半导体裸芯，包括例如2、8、16和32个半导体裸芯。可以使用DAF(裸芯贴附膜)将裸芯104在堆叠体110中彼此固定。作为一个示例，DAF可以是来自美国加利福尼亚州的汉高公司(Henkel Corp)的8988UV环氧树脂。
载体112可以是由任意的各种刚性、平面材料形成的薄板。在一个实施例中，刚性载体112可以由金属(诸如，例如不锈钢)形成。然而，在另外的实施例中，刚性载体112由其他材料形成，该其他材料包括例如硅、硅化合物、塑料或其他聚合物。
可以使用临时的接合膜116将裸芯堆叠体110固定到刚性载体112。至少在最初，接合膜116可以是被层压到刚性载体112上的B阶段粘合剂。裸芯104可以堆叠在临时的接合膜116上，并且固化或部分固化以将裸芯堆叠体110临时地接合到刚性载体112。如下文所解释的，一旦完成封装体100的制造，封装体100可以从刚性载体112分离。
一旦形成裸芯堆叠体110，在步骤204中，可以使用引线键合体120将堆叠体100中的各个裸芯104彼此电连接。为了说明的目的，图3示出了具有一些被示出的引线键合体的简化透视图。可以有比所示的更多的引线键合体120。每个半导体裸芯104可以包括沿着裸芯104的边缘的一行裸芯接合垫122。应当理解的是，每个裸芯104可以包括比图9中所示的更多的裸芯接合垫122。可以使用如下所述形成的引线键合体120将半导体裸芯的行中的每个裸芯接合垫122电连接到下一个相邻半导体裸芯的行中的相对应的裸芯接合垫122。
在实施例中，柱凸块126最初可以沉积在每个裸芯接合垫122上。每个柱凸块126可以通过在引线键合体劈刀(capillary)内的引线的末端处由电子焰烧(electronic flameoff,EFO)形成球来形成，然后通过压力、升高温度和超声波振荡将柱凸块126固定到裸芯接合垫122。在一个实施例中，柱可以使用120KHz的超声波频率在145℃的温度、20g的压力下持续约12ms来形成柱凸块126。这些参数仅为示例，并且每个参数在另外的实施例中可以变化。一旦柱凸块126被固定，引线键合体劈刀可以拉远以断开引线并留下柱凸块126。
在柱凸块126沉积在接合垫122上之后，缝(stitch)引线键合体120可以在裸芯104上(例如，在底部裸芯104上)的柱凸块126上形成，直到下一个更高的裸芯(例如，从底部开始的第二裸芯104)上的对应的柱凸块126。该过程可以在裸芯堆叠体110上重复，直到在堆叠体110中的一列裸芯接合垫中的所有相对应的裸芯接合垫122之间形成引线键合体120。
在另外的实施例中，引线键合体120可以通过其他方法(包括楔形键合体和/或球形键合体)来形成。引线键合体120一般示出为从裸芯堆叠体110中的一个裸芯到下一个裸芯的直的垂直列。然而，在另外的实施例中，一个或多个引线键合体可以从一个裸芯对角地延伸到下一个裸芯。此外，它可以是跳过裸芯堆叠体110中的一个或多个裸芯的引线键合体。
在步骤208中，一个或多个凸块130可以被添加到顶部裸芯104的每个裸芯接合垫122上的引线键合体，如图6A的局部放大边视图及图5和图6中所示。每个凸块130可以由例如金或金合金通过形成柱凸块来形成，如上所解释的，即，通过在引线键合体劈刀内的引线的末端处由EFO形成球来形成，然后将凸块130固定在柱凸块126上并且将引线键合体120缝合柱凸块126上。凸块130可以以垂直列直接堆叠在柱凸块126和引线键合体120的顶部。
在一个实施例中，在每列凸块130中的每个凸块130可以使用120KHz的超声波频率在145℃的温度、18g的压力下持续约12ms来形成。这些参数仅为示例，并且每个参数在另外的实施例中可以变化。一旦一列中的第一凸块130被固定，引线键合体劈刀可以拉离以断开引线。然后，引线键合体劈刀可以在该列中沉积第二凸块，等等，直到完成一列凸块130。可替代地，引线键合体劈刀可以在顶部裸芯104上的每个裸芯接合垫122上沉积第一凸块130，然后在每个裸芯接合垫上的第一凸块上沉积第二凸块130，等等，直到完成所有的凸块列。
一列中的凸块130的数量在实施例中可以变化，但是该数量可以在柱凸块126的顶部上的一个到四个凸块130之间。在顶部裸芯上的每个裸芯接合垫122可以具有相同数量的凸块130，但是可以想到，该数量在另外的实施例中可以变化。在实施例中，凸块130可以具有30μm和33μm之间的高度(在垂直于接合垫122的方向上)，尽管该高度在另外的实施例中可以比该范围更小或更大。
垂直列中的凸块130的尺寸和数量被提供为到达一个高度，该高度可以等于或大于引线键合体120的高度。在一个示例中，该高度可以约为110μm。然而，该高度可以变化，并且如下文所解释的，在另外的实施例中，凸块130的列的高度可以略小于引线键合体的高度。在使用具有大的高度的凸块的情形下，可以使用较少的凸块。作为一列金凸块的替代，可以想到的是，一个大的焊料凸块提供在柱凸块126的顶部上。作为另一个替代，一列其他金属可以被构造在柱凸块126的顶部上。
在顶部裸芯104上形成凸块130的列之后，裸芯可以在步骤210中被包封在模塑料134中，如图7和图8所示。模塑料可以被施加在刚性载体112的表面上，围绕固定到刚性载体112的半导体裸芯104。模塑料134可以包括例如固体环氧树脂、酚醛树脂、熔融二氧化硅、结晶二氧化硅、炭黑和/或金属氢氧化物。这样的模塑料例如从总部都设在日本的住友株式会社(Sumitomo Corp.)和日东电工株式会社(Nitto-Denko Corp.)来获得。可以设想来自其他制造商的其他模塑料。模塑料可以根据各种已知的工艺被施加，该各种已知的工艺包括通过FFT(自由流动减薄(flow free thin))模塑、传递模塑或注入模塑技术。
如图中所示，半导体裸芯104和裸芯堆叠体110的总足印(长度和宽度)小于模塑料134的足印。如下文所解释的，RDL垫可以固定到模塑料，该RDL垫可以具有与其附接到的模塑料的表面相同的足印。具有增大的RDL垫(模塑料的足印，而不是裸芯的足印)提供了相对于常规的芯片级封装体的增加的I/O。如上文所提到的和下文所解释的，多个半导体封装体100可以在刚性载体112上形成。模塑料可以跨越刚性载体112的整个表面上施加，形成包封载体112上的所有封装体100的模塑料的块。
如图8所示，模塑料可以被施加，以便于在顶部裸芯104和模塑料的表面134a之间建立间隔。凸块130的列可以提供为具有填充该间隔的高度。因此，如图7所示，顶部裸芯104上的每列凸块130中的顶部凸块130的至少部分被暴露在模塑料134的表面134a处或其上方。在另外的实施例中(未示出)，到上部裸芯的引线键合体120的最高部分还可以通过模塑料134的表面暴露。模塑料134可以经过抛光和等离子处理以确保表面134a是平坦且平面的。
在步骤214中，再分布层(RDL)垫140可以固定到模塑料134的表面134a，如图9和图10所示。RDL垫140包括第一表面，该第一表面具有将RDL垫140直接固定到表面134a的粘合剂。RDL垫140可以具有匹配模塑料134的表面134a的长度和宽度。RDL垫140的第一表面包括多个接触垫142，该多个接触垫142具有的位置和配置与通过模塑料134的表面134a暴露的凸块130相配合。因此，一旦将RDL垫140安装到模塑料134，接触垫142被电耦合到一列凸块130，继而电耦合到半导体裸芯104的裸芯接合垫122。
RDL垫140由夹在第一聚酰胺层和第二聚酰胺层之间的导电图案来形成，该第一聚酰胺层具有固定到模塑料134的表面，该第二聚酰胺层在RDL垫140的相反表面。焊料球144的图案提供在第二聚酰胺层的表面上(在RDL垫140被固定到模塑料134之前或之后)。导电图案包括多个电迹线148和通孔150，电迹线148和通孔150将接触垫142与所选择的那些焊料球144电耦合，以将接触垫142电再分配到所选择的那些焊料球144。可以理解的是，所示的焊料球144的图案和电迹线148仅为示例，并且RDL垫140可以包括焊料球144和迹线148的其他图案，其具有更多数量或更少数量的焊料球144和迹线148。
引线键合体120、一列凸块130和RDL垫140将裸芯104上的裸芯接合垫电耦合到所选择的那些焊料球144，以使能半导体封装体100和在其上安装封装体100的主机装置之间的通信，如下文所解释的。凸块130的列提供上部半导体裸芯104和RDL垫140之间所需的间隔以用于引线键合体120，从而使多个半导体104能够被包括在封装体100之内。在上述的另外的实施例中，可以想到的是，到上部裸芯104的一个或多个引线键合体120可以通过模塑料134的表面暴露。如果发生这种情形，由于RDL垫140的相邻表面由聚酰胺绝缘体形成，因此任何暴露的引线键合体120的电短路被防止。
如所述的，半导体封装体100可以在刚性载体112上大量生产，例如图11的部分透视图所示的。在步骤218中，刚性载体可以与半导体封装体100分离，该半导体封装体100在模塑料134的块内保持为固定在一起。在步骤220中，单独的半导体封装体100可以从模塑料的块单片化，产生完成的包封的半导体封装体100。
如上所述，可以通过任意的各种过程来分离刚性载体112，包括移除、抵消或克服结合膜116的粘合力的热过程和机械过程。在实施例中，完成的封装体100可以在热过程中从刚性载体112分离，在该情形中，接合膜116被溶解，或者接合膜116的粘合性降低或抵消。用于在这样的热过程中使用的接合膜116的示例是来自日本大阪的日东电工株式会社的Revalpha。在另外的实施例中，完成的封装体100可以在机械分离过程中从刚性载体分离，在该情形中，在裸芯堆叠体110和接合膜116之间施加克服接合膜的粘合力的力。用于在这样的热过程中使用的接合膜116的示例是来自日本东京的日立化成株式会社(HitachiChemical Corporation,Ltd)的TM-X12-A1。当分离时，刚性载体112可以被丢弃或重新使用。
可以通过任意的各种切割方法来单片化各个半导体封装体100，该各种切割方法包括锯切、水射流切割、激光切割、水导引激光切割、干介质切割和金刚石涂层引线切割。虽然这些切割通常将限定矩形或正方形形状的半导体封装体100，但可以理解的是，在本发明的另外的实施例中，半导体封装体100可以具有除了矩形和正方形之外的形状。
图2的流程图示出了在单片化步骤之前发生的刚性载体的分离。然而，在另外的实施例中，刚性载体的分离可以在单片化步骤之后发生。此外，刚性载体的分离可以与单片化步骤(作为单片化步骤的结果)同时发生。
一旦单片化为单独的半导体封装体100，封装体100可以被翻转并且固定到主机装置160，如图13所示。主机装置可以例如是印刷电路板。封装体100可以通过焊料球144物理地且电气地耦合到主机装置160，焊料球144可以在回流工艺中被硬化以将封装体100永久地固定到主机装置160。
本技术提供能够比常规的扇出芯片级封装体容纳更多存储器裸芯的扇出半导体封装体，从而提供相对于常规的扇出芯片级封装体的增加的存储器容量。本技术还提供优于常规的基板半导体封装体的优点。图14中示出常规的基板半导体封装体50，其包括基板52、引线键合到彼此的半导体裸芯54的堆叠体、以及模塑料56。常规的基板52具有80μm至100μm的厚度。通过比较，图13的RDL垫140具有例如10μm至20μm的厚度。因此，RDL垫140比常规的基板封装体提供至少60μm的高度节约。
此外，常规的基板封装体需要为模塑料提供厚度，该厚度在最高的引线键合体上方留下间隙高度h，以确保引线键合体没有通过模塑料的表面暴露。该间隙高度h常规为95μm至110μm。通过比较，根据本技术，引线键合体可以通过封装体100中的模塑料的表面暴露。因此，本技术的封装体100中的间隙高度可以减少或完全消除，从而提供相对于常规的基板封装体100的高度的进一步减少。
此外，由于常规的基板封装体50中的底部半导体裸芯54需要通过DAF层固定到基板52，因此在常规的基板封装体中有用于每个半导体裸芯的一层DAF。相比之下，根据本技术的半导体封装体的DAF层比半导体裸芯少一层(在裸芯堆叠体110的底部或顶部表面上没有DAF)。因此，相比于常规的基板半导体封装体50，由于少了一个DAF层(例如10μm)，根据本技术的封装体100进一步减小。
在实施例中，本技术涉及半导体封装体100，其可以是扇出半导体封装体，在这种情形下，来自半导体裸芯的电连接扇出，或者被分配到半导体裸芯和/或裸芯堆叠体的足印以外的位置。特别地，来自电接触142的信号被分配到较大的RDL垫140上的焊料球142。在实施例中，半导体封装体100还可以是芯片级封装体，或CSP。在实施例中，RDL垫140可以具有比半导体裸芯104的区域大至1.2倍的区域，一列焊料球130被固定到RDL垫140的该区域。在另外的实施例中，RDL垫140的区域可以比该半导体裸芯小于或大于1.2倍。
为了说明和描述的目的，已经呈现本发明的前面的详细描述。它不旨在穷尽或限制本发明为公开的精确形式。根据上述教导的许多修改和变化是可能的。选择所描述的实施例是为了最好地解释本发明的原理及其实际应用，从而使得本领域的技术人员能够最好地利用各种实施例中的发明且各种修改适合于设想的特定用途。本发明的范围由所附的权利要求限定。

Claims (20)

1.一种半导体封装体，其包括：
多个堆叠的半导体裸芯，每个半导体裸芯包括裸芯接合垫，所述多个堆叠的半导体裸芯包括在所述堆叠的半导体裸芯的顶部的第一半导体裸芯；
模塑料，所述多个半导体裸芯包封在所述模塑料内，以便包括所述裸芯接合垫的所述第一半导体裸芯的表面在所述模塑料内，并且与所述模塑料的表面分隔开；
引线键合体，其被固定在所述多个堆叠的半导体裸芯的裸芯接合垫上，所述引线键合体电耦合所述多个堆叠的半导体裸芯；
成列的一个或多个凸块，其形成在所述第一半导体裸芯上的裸芯接合垫处的所述引线键合体的顶部，每列的所述一个或多个凸块具有通过所述模塑料的表面暴露的凸块的表面；
再分配层垫，其被固定到所述模塑料的表面，所述再分配层垫包括：
接触垫，所述接触垫在所述再分配层垫的第一表面上，所述接触垫在所述模塑料的表面处与每列的暴露的凸块相配合，
焊料凸块，所述焊料凸块在所述再分配层垫的第二表面上，以及
导电图案，其用于将所述再分配层垫的第一表面上的所述接触垫与所述再分配层垫的第二表面上的所选择的那些焊料凸块电连接。
2.如权利要求1所述的半导体封装体，其中一列凸块在裸芯接合垫的上方的高度大于或等于引线键合体在所述裸芯接合垫以上的高度。
3.如权利要求1所述的半导体封装体，其中至所述第一半导体裸芯的裸芯接合垫的引线键合体完全包封在所述模塑料内。
4.如权利要求1所述的半导体封装体，其中至所述第一半导体裸芯的裸芯接合垫的引线键合体通过所述模塑料的表面暴露。
5.如权利要求1所述的半导体封装体，其中在一列凸块中有一个至四个凸块。
6.如权利要求1所述的半导体封装体，其中所述引线键合体包括所述第一半导体裸芯的裸芯接合垫上的柱凸块。
7.如权利要求6所述的半导体封装体，其中在所述柱凸块的顶部上堆叠有一个至四个凸块。
8.如权利要求1所述的半导体封装体，其中所述再分配层垫的足印与所述模塑料的表面的足印相同。
9.如权利要求8所述的半导体封装体，其中所述再分配层垫和所述模塑料的表面的足印大于所述多个堆叠的半导体裸芯的足印。
10.一种半导体封装体，其包括：
多个堆叠的半导体裸芯，每个半导体裸芯包括裸芯接合垫，所述多个堆叠的半导体裸芯包括在所述堆叠的半导体裸芯的顶部的第一半导体裸芯；
模塑料，所述多个半导体裸芯包封在所述模塑料内，包括所述裸芯接合垫的所述第一半导体裸芯的表面嵌入在所述模塑料内，以限定所述第一半导体裸芯的表面和所述模塑料的表面之间的间隔；
引线键合体，其被固定在所述多个堆叠的半导体裸芯的裸芯接合垫上，所述引线键合体电耦合所述多个堆叠的半导体裸芯，至所述第一半导体裸芯上的裸芯接合垫的所述引线键合体被提供在所述第一半导体裸芯的表面和所述模塑料的表面之间的所述间隔中；
成列的一个或多个凸块，其形成在所述第一半导体裸芯上的裸芯接合垫处的所述引线键合体的顶部，每列的所述一个或多个凸块填充所述第一半导体裸芯的表面和所述模塑料的表面之间的所述间隔；
再分配层垫，其被固定到所述模塑料的表面，所述再分配层垫包括：
接触垫，所述接触垫在所述再分配层垫的第一表面上，所述接触垫在所述模塑料的表面处与每列的暴露的凸块相配合，
焊料凸块，所述焊料凸块在所述再分配层垫的第二表面上，以及
导电图案，其用于将所述再分配层垫的第一表面上的所述接触垫与所述再分配层垫的第二表面上的所选择的那些焊料凸块电连接。
11.如权利要求10所述的半导体封装体，其中一列凸块在裸芯接合垫的上方的高度大于或等于引线键合体在所述裸芯接合垫以上的高度。
12.如权利要求10所述的半导体封装体，其中至所述第一半导体裸芯的裸芯接合垫的引线键合体完全包封在所述模塑料内。
13.如权利要求10所述的半导体封装体，其中至所述第一半导体裸芯的裸芯接合垫的引线键合体通过所述模塑料的表面暴露。
14.如权利要求10所述的半导体封装体，其中在一列凸块中有一个至四个凸块。
15.如权利要求1所述的半导体封装体，其中所述引线键合体包括所述第一半导体裸芯的裸芯接合垫上的柱凸块。
16.如权利要求15所述的半导体封装体，其中在所述柱凸块的顶部上堆叠有一个至四个凸块。
17.一种扇出半导体封装体，其包括：
多个堆叠的半导体裸芯，每个半导体裸芯包括裸芯接合垫，所述多个堆叠的半导体裸芯包括在所述堆叠的半导体裸芯的顶部的第一半导体裸芯；
模塑料，所述多个半导体裸芯包封在所述模塑料内，包括所述裸芯接合垫的所述第一半导体裸芯的表面嵌入在所述模塑料内，以限定所述第一半导体裸芯的表面和所述模塑料的表面之间的间隔；
引线键合体，其被固定在所述多个堆叠的半导体裸芯的裸芯接合垫上，所述引线键合体电耦合所述多个堆叠的半导体裸芯，至所述第一半导体裸芯上的裸芯接合垫的所述引线键合体被提供在所述第一半导体裸芯的表面和所述模塑料的表面之间的所述间隔中；
再分配层垫，其被固定到所述模塑料的表面，所述再分配层垫包括：
接触垫，所述接触垫在所述再分配层垫的第一表面上，
焊料凸块，所述焊料凸块在所述再分配层垫的第二表面上，以及
导电图案，其用于将所述再分配层垫的第一表面上的所述接触垫与所述再分配层垫的第二表面上的所选择的那些焊料凸块电连接；以及
装置，所述装置被提供在所述间隔中，以将所述再分配层垫的接触垫与所述第一半导体裸芯的裸芯接合垫电耦合。
18.如权利要求17所述的半导体封装体，其中所述装置包括由与所述引线键合体相同的材料制成的一列柱凸块。
19.如权利要求17所述的半导体封装体，其中所述装置包括焊料凸块。
20.如权利要求17所述的半导体封装体，其中所述装置包括一列导电材料。
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