TWI574332B - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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Publication number
TWI574332B
TWI574332B TW103129085A TW103129085A TWI574332B TW I574332 B TWI574332 B TW I574332B TW 103129085 A TW103129085 A TW 103129085A TW 103129085 A TW103129085 A TW 103129085A TW I574332 B TWI574332 B TW I574332B
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Taiwan
Prior art keywords
die
die stack
substrate
stack
semiconductor device
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TW103129085A
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English (en)
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TW201523757A (zh
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志明 俞
呂忠
葛夏朗恩 席恩
顧偉
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晟碟信息科技（上海）有限公司
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

半導體裝置及其形成方法
對可攜式消費型電子器件之強勁增長需求推動對高容量儲存裝置之需求。非揮發性半導體記憶體裝置(諸如快閃記憶體儲存卡)正廣泛用於滿足對數位資訊儲存及交換之日益增長需求。非揮發性半導體記憶體裝置之便攜性、多功能性及堅固設計以及其高可靠性及大容量已使此等記憶體裝置理想地用於包含(例如)數位相機、數位音樂播放器、視訊遊戲機、PDA及蜂巢式電話之各種電子裝置中。
儘管吾人已知諸多各種封裝組態，但快閃記憶體儲存卡一般可製造為系統級封裝(SiP)或多晶片模組(MCM)，其中複數個晶粒安裝及互連於一小覆蓋區基板上。該基板一般可包含具有蝕刻於一側或兩側上之一導電層之一剛性介電基座。電連接形成於該晶粒與該(等)導電層之間，且該(等)導電層對該晶粒至一主機裝置之連接提供一電引線結構。一旦形成該晶粒與該基板之間之電連接，則總成通常圍封於提供一保護封裝之一模製化合物中。
圖1及圖2(圖2中無模製化合物)展示一習知半導體封裝20之一橫截面側視圖及一俯視圖。典型封裝包含附裝至一基板26之複數個半導體晶粒，諸如快閃記憶體晶粒22及控制器晶粒24。複數個晶粒接合墊28可在晶粒製程期間形成於半導體晶粒22、24上。類似地，複數個接觸墊30可形成於基板26上。晶粒22可附裝至基板26，且接著晶粒24可安裝於晶粒22上。接著，所有晶粒可藉由將導線接合件32附裝於各自 晶粒接合墊28與接觸墊30對之間而電耦合至基板。一旦形成所有電連接，則晶粒及導線接合件可囊封於一模製化合物34中以密封封裝且保護晶粒及導線接合件。
為最有效率地使用封裝覆蓋區，吾人已知將半導體晶粒堆疊於彼此之頂部上，彼此完全堆疊且相鄰晶粒之間具有一間隔層，或如圖1及圖2中所展示般具有一偏移。在一偏移組態中，一晶粒堆疊於另一晶粒之頂部上，使得下晶粒之接合墊保持暴露。一偏移組態提供使堆疊中之半導體晶粒之各者上之接合墊便於接達之一優點。
隨著半導體晶粒日益變薄，且為增加半導體封裝中之記憶體容量，一半導體封裝之晶粒堆疊中之晶粒數目不斷增加。此呈現之一問題在於：當一單一晶粒在晶粒堆疊之測試期間失效時，整個晶粒堆疊通常會被捨棄。改良產量以使大型晶粒堆疊有價值變得尤為重要。
20‧‧‧半導體封裝
22‧‧‧快閃記憶體晶粒/半導體晶粒
24‧‧‧控制器晶粒/半導體晶粒
26‧‧‧基板
28‧‧‧晶粒接合墊
30‧‧‧接觸墊
32‧‧‧導線接合件
34‧‧‧模製化合物
100‧‧‧半導體裝置/封裝
102‧‧‧基板
103‧‧‧核心
104‧‧‧通孔
105‧‧‧頂部導電層
106‧‧‧電跡線
107‧‧‧底部導電層
108‧‧‧接觸墊
110‧‧‧焊料遮罩
112‧‧‧被動組件
120‧‧‧第一晶粒堆疊
124‧‧‧半導體晶粒
1241‧‧‧底部晶粒
128‧‧‧模製化合物
130‧‧‧導線接合件
132‧‧‧第二晶粒堆疊
134‧‧‧晶粒接合墊/球形接合件
136‧‧‧球形接合件/球
140‧‧‧模製化合物
142‧‧‧焊料球
150‧‧‧間隔層
200‧‧‧步驟
202‧‧‧步驟
204‧‧‧步驟
206‧‧‧步驟
208‧‧‧步驟
210‧‧‧步驟
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214‧‧‧步驟
218‧‧‧步驟
220‧‧‧步驟
222‧‧‧步驟
224‧‧‧步驟
226‧‧‧步驟
228‧‧‧步驟
230‧‧‧步驟
232‧‧‧步驟
234‧‧‧步驟
236‧‧‧步驟
240‧‧‧步驟
244‧‧‧步驟
圖1係一習知半導體封裝之一橫截面側視圖。
圖2係一習知基板及導線接合半導體晶粒之一俯視圖。
圖3係根據本發明之實施例之半導體裝置之整個製程之一流程圖。
圖4係根據本發明之一實施例之製程之一第一步驟中之一半導體裝置之一側視圖。
圖5係根據本發明之一實施例之製程之一第二步驟中之一半導體裝置之一俯視圖。
圖6係根據本發明之一實施例之製程之一第三步驟中之一半導體裝置之一側視圖。
圖7係根據本發明之一實施例之製程之一第四步驟中之一半導體裝置之一側視圖。
圖8係根據本發明之一實施例之製程之一第五步驟中之一半導體 裝置之一側視圖。
圖9係根據本發明之一實施例之製程之第五步驟中之一半導體裝置之一簡化透視圖。
圖10係根據本發明之一實施例之製程之一第六步驟中之一半導體裝置之一側視圖。
圖11係根據本發明之一實施例之製程之一第七步驟中之一半導體裝置之一側視圖。
圖12係根據本發明之一實施例之製程之一第八步驟中之一半導體裝置之一側視圖。
圖13係根據本發明之一實施例之製程之一第九步驟中之一半導體裝置之一側視圖。
圖14至圖16係根據本發明之半導體裝置之一替代實施例之側視圖。
圖17至圖18係根據本發明之半導體裝置之一進一步替代實施例之側視圖。
現將參考圖3至圖18來描述本發明，在實施例中，圖3至圖18係關於包含可在安裝一額外晶粒堆疊之前被測試及囊封之中間晶粒堆疊之一半導體裝置。應瞭解，本發明可體現為諸多不同形式且不應被解釋為受限於本文所闡述之實施例。確切而言，此等實施例經提供使得本發明可透徹完整且會將本發明完全傳達給熟習技術者。其實，本發明意欲涵蓋包含於由隨附技術方案界定之本發明之範疇及精神內之此等實施例之替代例、修改方案及等效物。此外，在本發明之以下詳細描述中，諸多特定細節經闡述以提供對本發明之一透徹理解。然而，一般技術者應清楚，可在無此等特定細節之情況下實踐本發明。
如本文所使用，術語「頂部」及「底部」、「上」及「下」及 「垂直」及「水平」僅供例示及繪示，且不意謂限制本發明之描述，此係因為所提及之項目可進行位置及定向交換。此外，如本文所使用，術語「實質上」「近似」及/或「大約」意謂：對於一給定應用，指定尺寸或參數可在一可接受之製造容限內變動。在一實施例中，該可接受之製造容限係±0.25%。
現將參考圖3之流程圖及圖4至圖12之俯視圖及側視圖來解釋本發明之一實施例。儘管圖4至圖18各展示一個別裝置100或其之一部分，但應瞭解，裝置100可與在一基板面板上之複數個其他封裝100一起被批量處理以達成規模經濟。基板面板上之封裝100之列數及行數可變動。
基板面板開始於複數個基板102(圖4至圖18中亦僅展示一個此類基板)。基板102可為各種不同晶片載體介質，其包含一印刷電路板(PCB)、一引線框或一捲帶式自動接合(TAB)捲帶。當基板102係一PCB時，基板可由具有一頂部導電層105及一底部導電層107之一核心103形成，如圖4中所指示。核心103可由各種介電材料(諸如(例如)聚醯亞胺層壓板、包含FR4及FR5之環氧樹脂、雙馬來醯亞胺三嗪(BT)及類似者)形成。儘管核心並非為本發明之關鍵部分，但其可具有40微米(μm)至200微米之間之一厚度，但在替代實施例中，核心之厚度可在該範圍外變動。在替代實施例中，核心103可為陶瓷或有機物。
環繞核心之導電層105、107可由銅或銅合金、鍍銅或鍍銅合金、合金42(42Fe/58Ni)、鍍銅鋼或已知用於基板面板上之其他金屬及材料形成。該等導電層可具有約10微米至約25微米之一厚度，但在替代實施例中，該等層之厚度可在該範圍外變動。
圖3係根據本發明之實施例之用於形成一半導體裝置之製程之一流程圖。在一步驟200中，基板102可經鑽孔以界定基板102中之通孔104。通孔104(圖中僅標示其等之部分)僅供例示，且基板102可包含 比圖中所展示之通孔多之諸多通孔104，通孔104可位於除圖中所展示之位置之外之不同位置處。接著，在步驟202中，於頂部導電層及底部導電層之一者或兩者上形成導電圖案。該(等)導電圖案可包含電跡線106及接觸墊108，例如圖5及圖6中所展示。跡線106及接觸墊108(圖中僅標示其等之部分)僅供例示，且基板102可包含比圖中所展示之跡線及/或接觸墊多之跡線及/或接觸墊，且跡線106及接觸墊108可位於除圖中所展示之位置之外之不同位置處。
在實施例中，完成之半導體裝置100總成可用作為一BGA(球柵陣列)封裝。基板102之一下表面可包含用於接收焊料球之接觸墊108，如下文所解釋。在進一步實施例中，完成之半導體裝置100可為一LGA(地柵陣列)封裝，其包含用於將完成之裝置100可移除地耦合於一主機裝置內之接觸指。在此等實施例中，該下表面可包含接觸指而非接收焊料球之接觸墊。可藉由包含(例如)各種光微影程序之各種已知程序而形成基板102之頂面及/或底面上之導電圖案。
再次參考圖3，接著可在步驟204中於一自動光學檢測(AOI)中檢測基板102。一旦已檢測一焊料遮罩110，則可在步驟206中將焊料遮罩110施加至基板。在施加焊料遮罩之後，可在步驟208中於一已知電鍍或薄膜沈積程序中使導電圖案上之接觸墊、接觸指及任何其他焊料區域電鍍有一Ni/Au、合金42或類似者。接著，可在一自動檢測程序(步驟210)及一最後視覺檢測(步驟212)中檢測及測試基板102以檢查電操作且由污染引起之劃痕及褪色。
若基板102通過檢測，則可在步驟214中將被動組件112附裝至基板。一個或多個被動組件可包含(例如)一個或多個電容器、電阻器及/或電感器，但可考量其他組件。被動組件112(圖中僅標示一者)僅供例示，且在進一步實施例中，數目、類型及位置可變動。
根據本發明，接著可依容許安裝、囊封及測試一第一群組之晶 粒，且接著容許安裝一第二群組之晶粒，囊封及接著測試整個封裝之一方式將晶粒堆疊附裝於基板上。此容許包含大量半導體晶粒之一封裝之高產量(但在實施例中，本發明之原理可應用於具有少量半導體晶粒之一封裝)。在安裝第二晶粒堆疊之前測試第一晶粒堆疊藉由在將所有晶粒安裝於半導體裝置內之前識別故障半導體晶粒而改良產量。
在步驟218中，可於基板102上形成包含諸多半導體晶粒124之一第一晶粒堆疊120。此處之形成係指：將晶粒附裝至基板上呈一堆疊，如圖7中所展示；且接著使半導體晶粒彼此接合且藉由導線接合件130而使半導體晶粒與基板接合，如圖8中所展示。晶粒可堆疊成一偏移(階梯式)組態，如圖7及圖8中所展示。可使用一晶粒附著膜來將晶粒附裝至基板及/或使晶粒彼此附裝。作為一實例，晶粒附著黏著劑可為購自Henkel AG & Co.KGaA之8988UV環氧樹脂，其固化成一B級以將晶粒124初步附裝於堆疊120中且隨後固化成一最終C級以將晶粒124永久附裝於堆疊120中。
半導體晶粒124可(例如)為記憶體晶粒(諸如一NAND快閃記憶體晶粒)，但可使用其他類型之晶粒124。圖7展示其中將八個晶粒124安裝於堆疊120中之一實施例。然而，在進一步實施例中，堆疊120中可存在八個以上或八個以下晶粒124。作為進一步實例，晶粒堆疊120可包含四個或六個記憶體晶粒。
現將參考圖8之側視圖，一旦已形成晶粒堆疊120，則堆疊120中之各自晶粒124可彼此電連接且可使用導線接合件130來電連接至基板102。圖9係展示基板102及晶粒堆疊120中之僅底部兩個晶粒124之一簡化透視圖。如圖中所展示，各半導體晶粒124可包含沿著晶粒124之一邊緣之一列晶粒接合墊134。應瞭解，各晶粒124可包含比圖9所展示之晶粒接合墊多之諸多晶粒接合墊134。可使用一導線接合件130來 將一半導體晶粒之列上之各晶粒接合墊134電連接至緊鄰半導體晶粒之列上之對應晶粒接合墊134。可使用一導線接合件130來將底部半導體晶粒124之各晶粒接合墊134電連接至基板102上之接觸墊之列中之對應接觸墊108。
儘管可藉由各種技術而形成導線接合件130，但在一實施例中，導線接合件130可形成為反向球形接合件。此等可藉由使用已知建構(圖中未顯示)之一導線接合毛細管來首先將一球形接合件134沈積於一晶粒(諸如底部晶粒124)之晶粒接合墊上而塑造。可藉由饋送線一長度之導線(通常為金或銀合金)穿過該導線接合毛細管之一中央空腔而形成球形接合件136(圖9標示其等之一者)。該導線突出穿過該毛細管之一尖端，其中將一高電壓電荷自與該毛細管尖端相關聯之一換能器施加至該導線。該電荷熔化該尖端處之導線且歸因於熔融金屬之表面拉力，該導線形成於一球136中。當該換能器施加超音波能量時，球136可附裝至一負載下方之一晶粒接合墊134。
接著，導線接合毛細管可放出一小段長度之導線，且可在導電球上切斷導線以使球形接合件136留於晶粒接合墊134上。接著，自毛細管之端部垂下之導線之一小段尾部可用於形成用於列中之緊接其後之晶粒接合墊134之球形接合件136。可藉由包含(例如)晶圓層級處之接線柱凸塊或金凸塊之各種其他方法或藉由各種其他方法而於半導體晶粒124之接合墊處形成球形接合件136。
其後，另一球形接合件形成於緊接下層級上(例如基板102上)，如上文所解釋。然而，並非切斷導線，而是放出導線且使其與緊接較高層級上之一對應球形接合件136接觸(但在進一步實施例中，可跳過一個或多個層級)。當換能器施加超音波能量時，將導線施加至一負載下方之一球形接合件136。經組合之熱量、壓力及超音波能量在導線與球形接合件136之間產生一接合。接著，導線接合毛細管可放出 一小段長度之導線，且該導線可經切斷以在不同層級上之對應墊之間形成導線接合件130。
可橫跨晶粒及基板上之墊而水平地及在晶粒及基板上之墊之間垂直地重複此程序，直至已形成所有導線接合件130。在不同實施例中，導線接合件130之形成順序(水平或垂直)可變動。再者，儘管導線接合件130在晶粒堆疊120及基板中大體上展示為自一層至下一層之一筆直垂直行，但導線接合件之一者或多者可自一層對角地延伸至下一層。此外，一導線接合件可跳過晶粒堆疊120中之一層或多層。
在第一晶粒堆疊120附裝及導線接合至基板之後，可在步驟220中將晶粒堆疊120之一部分囊封於一模製化合物128中，如圖10中所展示。在實施例中，堆疊120之僅一部分包含步驟220中所囊封之導線接合件130。然而，如下文所解釋，在進一步實施例中，可在步驟220中囊封任何數量之晶粒堆疊120，其包含所有晶粒堆疊120。
模製化合物128可包含(例如)固體環氧樹脂、酚樹脂、熔融矽石、結晶二氧化矽、炭黑及/或金屬氫氧化物。此等模製化合物可(例如)購自兩者總部在日本之Sumitomo公司及Nitto-Denko公司。可考量來自其他製造商之其他模製化合物。可根據各種已知程序(其包含藉由轉移模製，其中模製空腔僅涵蓋此階段中待囊封之半導體裝置100之部分)而施加模製化合物128。在進一步實施例中，可藉由注射模製或其他技術而執行囊封程序。模製化合物128可施加為一A級或B級環氧樹脂，且接著固化成一固體C級。替代地，當附著一第二晶粒堆疊(如下文所解釋)且其後使其固化成至一C級時，可使模製化合物128保持為一B級黏著劑。
在步驟220中之囊封之後，可在步驟222中測試包含一晶粒堆疊120之半導體裝置100。步驟222可包含測試晶粒堆疊120中之各自晶粒124之功能性及裝置100之整體功能性之一個或多個操作。在步驟224 中，若裝置100未通過測試(即，不符合界定參數)，則可捨棄圖10中所展示之裝置100。替代地，根據測試之結果，可藉由停用一個或多個失效晶粒而矯正裝置100，如下文所解釋。在封包製造之此階段中偵測一失效封裝以藉由防止良好晶粒添加至一故障封裝而節省裝置製造成本，且改良整體產量。
另一方面，若圖10中所展示之半導體裝置100在步驟224中通過測試，則可在步驟228中添加一個或多個額外晶粒堆疊。特定言之，在實施例中，半導體裝置100可包含兩個晶粒堆疊120、132，如下文所描述之圖11中所展示。然而，可想像，兩個以上晶粒堆疊形成於半導體裝置100內，其中使各額外晶粒堆疊重複步驟218、220、222、224及226。然而，應注意，所添加之最終晶粒堆疊可跳過步驟220及222。即，在步驟220中無需囊封或測試最上晶粒堆疊，此係因為可在下文所解釋之步驟232、240中形成晶粒堆疊之後囊封及測試整個封裝。因此，例如，當存在兩個晶粒堆疊時，可在步驟220中部分地囊封底部晶粒堆疊且在步驟222中測試底部晶粒堆疊，但可跳過上晶粒堆疊之部分囊封及測試以取代發生於步驟232及240中之裝置100之完全囊封及測試。當存在(例如)三個晶粒堆疊時，可在步驟220、222中部分地囊封及測試前兩個晶粒堆疊，但第三晶粒堆疊及最終晶粒堆疊可跳過此等步驟。
若將在步驟228中添加一額外晶粒堆疊，則流程可返回至步驟218以形成下一記憶體晶粒堆疊，諸如(例如)圖11中所展示之晶粒堆疊132。步驟218可經重複以將晶粒堆疊132添加於晶粒堆疊120之頂部上。在圖11所展示之實施例中，晶粒堆疊132可由相同於晶粒堆疊120之晶粒數目形成，但沿相反方向分階。可如上文所描述般形成導線接合件130，其中來自堆疊132中之一底部晶粒1241之導線接合件向下延伸至基板102上之接觸墊108。此使堆疊132中之半導體晶粒124彼此電 連接且將堆疊132中之半導體晶粒124電連接至基板102。
儘管圖中未顯示，但可在晶粒堆疊120與132之間提供一插入器層以簡化導線接合。在進一步實施例中，可省略該插入器。
在實施例中，堆疊132中之底部晶粒1241可沿一水平方向向外延伸超出底部晶粒堆疊120中之最上晶粒以具有包含晶粒接合墊之一邊緣，底部晶粒1241未支撐於其下方之一半導體晶粒上，如圖11中所展示。為防止晶粒1241在導線接合程序期間破裂，底部晶粒1241可比晶粒堆疊132中之剩餘晶粒厚。在一實施例中，堆疊120及132中之晶粒(除晶粒1241之外)可具有約25微米之一厚度，且晶粒1241可為約102微米。此等厚度僅供例示且可在進一步實施例中變動。在一些實施例中，晶粒1241可具有相同於堆疊132中之其他晶粒之厚度。
在實施例中，晶粒1241可具有一厚度，使得其與模製化合物128之一上表面共面。因此，直接位於晶粒1241上之晶粒124可藉由可位於模製化合物128之上表面之頂部上之一邊緣而安裝於晶粒1241上(如圖11中所展示)，且不會在該晶粒內產生應力。在進一步實施例中，晶粒1241之厚度可使得直接位於晶粒1241上之晶粒124安裝於模製化合物128之表面上。
在將晶粒堆疊120、132等等安裝於基板102上之後，可在步驟230中安裝一控制器晶粒(圖中未顯示)且將其導線接合至基板。在實施例中，該控制器晶粒可安裝於最上晶粒堆疊之最上晶粒上。在進一步實施例中，該控制器晶粒將安裝於堆疊120中之最下晶粒下方。例如，該控制器晶粒可安裝於基板102之頂部上。具有2013年1月9日之一國際申請日之名稱為「Semiconductor Device Including an Independent Film Layer For Embedding and/or Spacing Semiconductor Die」之專利合作條約專利申請案第PCT/CN2013/070264號中揭示此一實施例之一實例。作為一進一步實施例，該控制器晶粒可安裝於基 板102內。具有2013年1月28日之一國際申請日之名稱為「Semiconductor Device Including an Embedded Controller Die and Method of Making Same」之專利合作條約專利申請案第PCT/CN2013/071051號中揭示此一實施例之一實例。此等兩個國際專利申請案之全文以引用之方式併入本文中。
在一步驟232中且如圖12中所展示，可在安裝及電連接晶粒堆疊120、132及控制器晶粒之後將晶粒堆疊、控制器、導線接合件及基板之至少一部分囊封於一模製化合物140中。模製化合物140可包含(例如)固體環氧樹脂、酚樹脂、熔融矽石、結晶二氧化矽、炭黑及/或金屬氫氧化物。此等模製化合物可購自(例如)兩者總部在日本之Sumitomo公司及Nitto-Denko公司。可考量來自其他製造商之其他模製化合物。可根據各種已知方法(其包含藉由轉移模製或注射模製技術)而施加模製化合物。在進一步實施例中，可藉由FFT(自由流動之薄)壓縮模製而執行囊封程序。
可固化之B級黏著劑及樹脂(諸如(例如)晶粒之間之晶粒附著膜)及可能之模製化合物128、140可在囊封步驟期間固化成最終交聯之C級。在進一步實施例中，黏著劑及/或樹脂可在一單獨加熱步驟中固化成C級。
如圖12中所展示，對於其中裝置100係一BGA封裝之實施例，在步驟232中囊封面板上之晶粒之後，可在步驟234中將焊料球142焊接至各自封裝之一底面上之接觸墊108。當封裝係LGA封裝時，可跳過步驟226。
可在步驟236中自面板分割各自封裝以形成圖12或圖13中所展示之完成半導體裝置100。可藉由各種切割方法之任何者(其包含鋸切、噴水切割、雷射切割、水導雷射切割、乾式介質切割及鑽石塗層線切割)而分割各半導體裝置100。儘管直線切割將大體上界定矩形或正方 形半導體裝置100，但應瞭解，在本發明之進一步實施例中，半導體裝置100可具有除矩形及正方形之外之形狀。
如上文所提及，當將各晶粒堆疊添加至裝置100時，可測試晶粒堆疊及裝置100之操作。在分割完成之半導體裝置100之後，裝置可在步驟240中經歷一最終測試以判定完成之裝置100是否適當運作。如此項技術中所知，此測試可包含電測試、燒入及其他測試。視情況而定，在步驟244中，完成之半導體裝置可圍封於一蓋(圖中未顯示)內，例如其中半導體裝置係LGA封裝。
當一個或多個晶粒無法通過測試步驟222及/或240時，可停用該等晶粒(即，電斷接或在晶粒堆疊內被隔離)。此可藉由切斷該晶粒之晶片啟用(CE)跡線而完成。其後，包含一個或多個停用晶粒之裝置可繼續通過本文所描述之製造步驟以達成一完成之裝置100，且可利用比具有完整功能晶粒之一相當封裝少之容量來操作。
完成之半導體裝置100可為(例如)一記憶卡，諸如(例如)一MMC卡、一SD卡、一多用途卡、一微SD卡、一記憶棒、一壓縮SD卡、一ID卡、一PCMCIA卡、一SSD卡、一晶片卡、一智慧卡、一USB卡、一MCP型嵌入卡儲存器或類似者。
圖14至圖16繪示根據本發明之一半導體裝置100之一進一步實施例。圖14至圖16之裝置100類似於先前圖之裝置，且由相同步驟製造。然而，當(例如)圖11中所展示之晶粒堆疊132沿與晶粒堆疊120相反之方向分階時，圖14中之晶粒堆疊132沿相同於晶粒堆疊120之方向分階。
在此實施例中，模製化合物128之上表面可高於晶粒堆疊120中之上晶粒之表面(至少更高達來自堆疊120中之上晶粒之導線接合件之高度)。為對圖14至圖16之實施例中之上晶粒堆疊132提供一層級接合表面，一間隔層150可安裝於堆疊120之頂部晶粒上，安裝至模製化合 物128之側。間隔層150可由一介電材料(諸如聚醯亞胺)形成，且可具有一厚度，使得間隔層之一上表面與模製化合物128之一上表面大體上共面。在實施例中，可在附裝第二晶粒堆疊132之前附裝間隔層。在圖14至圖16之實施例中，底部晶粒1241可具有相同於晶粒堆疊132中之其他晶粒之厚度，或其可更厚，如上文所描述。
如先前所提及，在實施例中，(若干)中間囊封步驟220囊封導線接合件130周圍之(若干)下晶粒堆疊之一部分。然而，(若干)中間囊封步驟220可囊封任何數量之(若干)下晶粒堆疊，其包含所有(若干)下晶粒堆疊，如圖17至圖18中所展示。圖17中展示兩個晶粒堆疊，其中第二晶粒堆疊相對於第一晶粒堆疊而反向分階。第一晶粒堆疊可完全囊封於模製化合物128中，且接著第二晶粒堆疊可安裝於模製化合物128之上表面上。第二晶粒堆疊之最底部晶粒可或可不比第二晶粒堆疊中之其他晶粒厚。圖18中展示兩個晶粒堆疊，其中第二晶粒堆疊沿相同於第一晶粒堆疊之方向分階。第一晶粒堆疊可完全囊封於模製化合物128中，且接著第二晶粒堆疊可安裝於模製化合物128之上表面上。可省略先前實施例中所描述之間隔層150。
總言之，在一實例中，本發明係關於一種半導體裝置，其包括：一基板；一第一晶粒堆疊附裝至該基板；一第一組導線接合件，其將該第一晶粒堆疊導線接合至該基板；一第一模製化合物，其至少囊封該第一組導線接合件；一第二晶粒堆疊，其安裝於該第一晶粒堆疊上；一第二組導線接合件，其將該第二晶粒堆疊導線接合至該基板；一第二模製化合物，其至少囊封該第二晶粒堆疊、該第二組導線接合件及該第一模製化合物。
在另一實例中，本發明係關於一種半導體裝置，其包括：一基板；一第一晶粒堆疊，其附裝至該基板；一第一組導線接合件，其將該第一晶粒堆疊導線接合至該基板；一第一模製化合物，其至少囊封 該第一組導線接合件；一第二晶粒堆疊，其安裝於該第一模製化合物及該第一晶粒堆疊上；一第二組導線接合件，其將該第二晶粒堆疊導線接合至該基板；一第二模製化合物，其囊封該第二晶粒堆疊、該第二組導線接合件、該第一模製化合物及未由該第一模製化合物囊封之該第一晶粒堆疊之任何部分。
在一進一步實例中，本發明係關於一種形成一半導體裝置之方法，其包括：(a)將一第一晶粒堆疊安裝於一基板上；(b)將該第一晶粒堆疊電連接至該基板；(c)囊封該第一晶粒堆疊之至少一部分；(d)測試該第一晶粒堆疊之功能性；(e)若該第一晶粒堆疊在該步驟(d)中於界定參數內運作，則將一第二晶粒堆疊安裝於該第一晶粒堆疊上；(f)將該第二晶粒堆疊電連接至該基板；及(g)在一第二囊封步驟中囊封該第二晶粒堆疊。
已為了繪示及描述之目的而呈現本發明之以上詳細描述。該描述不意欲具窮舉性或將本發明限制於所揭示之精確形式。可鑑於以上教示而進行諸多修改及變動。所描述之實施例經選擇以最佳地解釋本發明之原理及其實際應用以藉此使其他熟習技術者能夠在各種實施例中最佳地利用本發明且使本發明與適合於預期特定用途之各種修改一起使用。本發明之範疇意欲由本發明之隨附技術方案界定。
100‧‧‧半導體裝置/封裝
102‧‧‧基板
108‧‧‧接觸墊
140‧‧‧模製化合物
142‧‧‧焊料球

Claims (15)

  1. 一種半導體裝置，其包括：一基板；一第一晶粒堆疊，其附裝至該基板；一第一組導線接合件，其將該第一晶粒堆疊導線接合至該基板；一第一模製化合物，其囊封該第一組導線接合件及少於所有該第一晶粒堆疊；一第二晶粒堆疊，其安裝於該第一晶粒堆疊上；一第二組導線接合件，其將該第二晶粒堆疊導線接合至該基板；一第二模製化合物，其至少囊封該第二晶粒堆疊、該第二組導線接合件及該第一模製化合物。
  2. 如請求項1之半導體裝置，其中該第一晶粒堆疊沿一第一方向分階且該第二晶粒堆疊沿一第二相反方向分階。
  3. 如請求項2之半導體裝置，其中該第二晶粒堆疊之一最底部晶粒比該第二晶粒堆疊中之其他晶粒厚。
  4. 如請求項1之半導體裝置，其中該第一晶粒堆疊及該第二晶粒堆疊各包含八個記憶體晶粒。
  5. 如請求項1之半導體裝置，其中該第一晶粒堆疊及該第二晶粒堆疊各包含四個記憶體晶粒。
  6. 如請求項1之半導體裝置，其進一步包括一控制器晶粒。
  7. 如請求項1之半導體裝置，其中該半導體裝置係一地柵陣列半導體封裝。
  8. 如請求項1之半導體裝置，其中該半導體裝置係一球柵陣列半導 體封裝且進一步包括複數個焊料球，該複數個焊料球安裝至與包含該第一晶粒堆疊及該第二晶粒堆疊之一表面相對之該基板之一表面上之接觸墊。
  9. 一種半導體裝置，其包括：一基板；一第一晶粒堆疊，其附裝至該基板；一第一組導線接合件，其將該第一晶粒堆疊導線接合至該基板；一第一模製化合物，其囊封該第一組導線接合件及少於所有該第一晶粒堆疊；一第二晶粒堆疊，其安裝於該第一模製化合物及該第一晶粒堆疊上；一第二組導線接合件，其將該第二晶粒堆疊導線接合至該基板；一第二模製化合物，其囊封該第二晶粒堆疊、該第二組導線接合件、該第一模製化合物及未由該第一模製化合物囊封之該第一晶粒堆疊之任何部分。
  10. 如請求項9之半導體裝置，其中該第一模製化合物之一上表面與該第二晶粒堆疊中之最底部晶粒之一底面共面。
  11. 一種形成一半導體裝置之方法，其包括以下步驟：(a)將一第一晶粒堆疊安裝於一基板上；(b)將該第一晶粒堆疊電連接至該基板；(c)囊封該第一晶粒堆疊之一部分，該部分包括少於所有該第一晶粒堆疊；(d)測試該第一晶粒堆疊之功能性；(e)若該第一晶粒堆疊在該步驟(d)中於界定參數內運作，則將 一第二晶粒堆疊安裝於該第一晶粒堆疊上；(f)將該第二晶粒堆疊電連接至該基板；及(g)在一第二囊封步驟中囊封該第二晶粒堆疊。
  12. 如請求項11之方法，其中該步驟(b)包括：將該第一晶粒堆疊中之半導體晶粒之晶粒接合墊導線接合至該基板上之接觸墊。
  13. 如請求項11之方法，其中該步驟(c)包括：囊封非所有該第一晶粒堆疊。
  14. 如請求項11之方法，其中該步驟(c)包括：囊封所有該第一晶粒堆疊。
  15. 如請求項11之方法，其進一步包括以下步驟：停用未在該等界定參數內運作之一個或多個晶粒。
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