CN104051395B - 芯片堆叠封装及其方法 - Google Patents

芯片堆叠封装及其方法 Download PDF

Info

Publication number
CN104051395B
CN104051395B CN201410095098.3A CN201410095098A CN104051395B CN 104051395 B CN104051395 B CN 104051395B CN 201410095098 A CN201410095098 A CN 201410095098A CN 104051395 B CN104051395 B CN 104051395B
Authority
CN
China
Prior art keywords
chip
package
hole
encapsulation
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410095098.3A
Other languages
English (en)
Other versions
CN104051395A (zh
Inventor
T·迈尔
S·阿尔贝斯
A·沃尔特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Deutschland GmbH
Original Assignee
Intel Mobile Communications GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Mobile Communications GmbH filed Critical Intel Mobile Communications GmbH
Publication of CN104051395A publication Critical patent/CN104051395A/zh
Application granted granted Critical
Publication of CN104051395B publication Critical patent/CN104051395B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一种电子封装包括插入层、粘附到所述插入层的第一面的裸片、粘附到所述插入层的第二面的嵌入式电子封装、密封化合物、穿过所述密封化合物提供从所述电子封装的第一面到所述插入层的电气路径的一组通孔，以及电气地再分布所述一组通孔以便形成一组互连焊盘的再分布层。所述裸片或者所述嵌入式电子封装或者上述二者电连接到所述插入层。

Description

芯片堆叠封装及其方法
技术领域
本公开涉及制造电子器件的设备和方法，并且更具体地涉及封装及其制造方法。
背景技术
在制造集成电路(IC)时，被称为芯片或裸片的IC通常在分布和与其它电子装配件的集成之前被封装。这一封装通常包括将芯片密封在材料中并且在封装的外部上提供电触点以便提供到该芯片的接口。芯片封装可以提供从芯片到电气或电子产品的母板的电连接、防污染物的保护、提供机械支撑、散热、并且减少热机械应变。
由于IC制造和IC封装之间的关系，IC封装还必须通常随着半导体工业的快速进步而发展。特别是，存在希望封装IC和其它电子器件以便使它们更小、更快和更可靠的行动。
发明内容
在本公开的第一方面中，一种芯片封装包括第一衬底、布置在所述第一衬底上方的第一芯片、布置在所述芯片上方与第一衬底相对的面上的第二衬底，所述第二衬底包括至少一个触点以及耦合到所述触点的至少一个电传导线；以及至少局部地密封所述第二衬底和所述第一芯片的密封材料；穿过所述密封材料延伸以便电耦合所述第二衬底的所述至少一个触点的至少一个接触孔。
在本公开的另一方面中，一种用于制造芯片封装的方法包括：提供载体；将第一芯片放置在所述载体上；将所述第一芯片和插入层粘附到一起，所述插入层具有耦合到其的第二芯片；围绕所述第一芯片和所述第二芯片形成密封化合物；穿过所述密封化合物从所述密封化合物的第一面到所述插入层钻至少一个通孔；使用电传导材料填充所述至少一个通孔；并且应用电气地重分布所述至少一个通孔以便形成一组互连焊盘的再分布层。
在本公开的又一方面中，一种用于制造复合封装的方法包括：提供载体；将芯片封装放置在所述载体上，所述芯片封装包括连接到插入层或者引线框的第二芯片；将所述第一芯片粘附到所述插入层或者所述引线框；在所述第一芯片和所述芯片封装周围形成密封化合物；穿过所述密封化合物从所述密封化合物的第一面到所述插入层钻至少一个通孔；使用导电材料填充所述至少一个通孔；应用电气地再分布所述至少一个通孔以便形成至少一个互连焊盘的再分布层。
附图说明
为了进一步使本公开的上述和其它优点以及特征清楚，将通过参照在附图中说明的其具体方面来呈现本公开方面的更加具体的描述。应该意识到，这些附图仅阐释了本公开的典型方面，并且因此不应该被认为限制其范围。将通过使用附图来额外具体且详细地描述和解释本公开，在附图中：
图1是现有技术的丝焊堆叠封装。
图2是示例性堆叠封装。
图3是具有顶部安装式封装的示例性堆叠封装。
图4是具有横向堆叠配置的示例性堆叠封装。
图5说明了用于制造堆叠封装的示例性方法。
图6A-6J说明了用于堆叠封装的示例性构造序列。
图7A-7K说明了在封装的制造或装配中的可选处理流。
具体实施方式
现在将参照附图，其中类似的结构将提供有类似的附图标记。应该理解，附图是本公开的示例性方面的概略和示意性表示，而不是限制本公开，并且也不一定按比例进行绘制。
下面的详细描述参照通过说明的方式示出可以在其中实践本公开的方面的具体细节的附图。
本文使用词语“示例性”用于意指“用作示例、实例或说明”。在本文被描述为“示例性”的任何方面或设计不必被构筑为比其它方面优选或有利。
关于在面或表面“上方”形成的沉积材料使用的词语“在……上方”在本文可以用于意指可以“直接”在暗指的面或表面上，例如与暗指的面或表面直接接触，形成沉积材料。关于在面或表面“上方”形成的沉积材料使用的词语“在……上方”在本文可以用于意指可以“间接”在暗指的面或表面上形成沉积材料，一个或多个额外的层布置在暗指的面或表面和沉积材料之间。
词语“芯片”或“电子芯片”意在包括使用半导体设备制造技术制造的任何设备，包括典型地形成在晶片，例如硅，上并且被分割为单独的裸片的集成电路、MEMS、NEMS，该单独的裸片在本文中也被称为“芯片”。芯片典型地提供有一个或多个电触点或互连，这提供到芯片上的相关电路的电连接。
芯片(可选地在本文被称为裸片)通常在分布和与其它电子装配件的集成之前被封装。这一封装通常包括将芯片密封在材料中并且在封装的外部上提供电触点以便提供到电气或电子产品的母板的接口。芯片封装可以提供从芯片到电气或电子产品的母板的电连接、防污染物的保护、提供机械支撑、散热、并且减少热机械应力。
将多个芯片堆叠在单个封装内是越来越普遍的封装要求，以便例如减小整体装配尺寸、功能电路速度和总成本。将多个芯片堆叠在单个封装内的一种手段包括将现有芯片封装连同一个或多个额外的现有封装或芯片嵌入在单个封装中。
图1是丝焊堆叠封装10。丝焊堆叠封装10在单个封装中将嵌入式丝焊封装1与裸片3组合。更具体地，嵌入式丝焊封装1使用丝焊技术封装裸片5，其中裸片5提供有将裸片5电连接到衬底9的丝焊7。裸片5和丝焊7由密封化合物11密封以便形成嵌入式丝焊封装1。
嵌入式丝焊封装1提供有接触焊盘，例如衬底9上的接触焊盘16。接触焊盘16可以例如通过接合线18电耦合到衬底17。裸片或无源设备(例如，集成无源设备)13也可以提供在衬底9上，例如通过粘合剂粘附到该衬底9。丝焊15被表示为提供裸片13和衬底17之间的电连接。这些结构位于嵌入式丝焊封装1的“外部”，就它们的结构位于密封11的外部而言，并且用于将嵌入式丝焊封装1连接到它被集成在其中的丝焊堆叠封装10的周围结构。
更具体地，嵌入式丝焊封装1被表示为将其密封11粘附到裸片3。裸片3布置为“倒装芯片”互连配置。更具体地，在裸片3的一个面上的触点可以提供有建立裸片3和衬底17之间的电连接的焊料隆起焊盘。未充满层19提供在裸片3和衬底17之间。按照这种方式，裸片5、13和3中的每一个可以电耦合到衬底17。设置在衬底17的顶部面上的部件全部被埋入密封化合物21中，形成封装10，在封装10的底部面上由衬底17限定(bound)。焊球23提供在衬底17的底部面上。
在操作中，衬底17提供从其一个面上的连接到另一个面，更具体地，从由密封覆盖的顶部面到暴露的底部面，的电传导路径。从而使用前述部件形成一体封装。衬底17上的焊球23提供到密封的芯片的可焊接电气接口。
尽管丝焊堆叠封装10提供了在封装内部的封装的嵌入式结构，但是期望能够由丝焊封装实现的由于封装尺寸和电性能的改善的电子封装。
图2是根据本公开方面的电子堆叠封装20。可以是电子封装的封装20包括嵌入式电子球形栅格阵列(BGA)封装1’，其本身被表示为包括被表示为倒装芯片配置的裸片5’。可选地，也可以使用丝焊BGA或QFN(方形扁平无引脚)封装。倒装芯片BGA被表示为包括插入层衬底25。更具体地，提供在第一面上具有到裸片5’的电连接的再分布层或互连层28，并且该再分布层或互连层28典型地贯穿第二面上的较大表面区域提供多个触点。层28的第二面上的触点被表示为提供有建立插入层25和裸片5’之间的电连接的焊料隆起焊盘29。如图所示，BGA 1’是包括插入层25、焊料隆起焊盘29和嵌入在模具或密封化合物11’中的裸片5’的完整封装。而且，插入层/衬底25被表示为具有突出或延伸超出芯片3的横向尺寸的横向尺寸。
BGA封装1’被表示为通过粘合剂27粘附到裸片3’，粘合剂可以是胶带或胶水的形式，例如裸片粘附膜(DAF)或环氧树脂粘合剂。在组合中，BGA封装1’和也可以是倒装芯片的裸片3’形成可以使用模具化合物21’被包胶模具化或者可以被层叠的堆叠。包胶模具的样式可以是任何形状，例如圆形、矩形或正方形。
如图所示，嵌入式封装或BGA封装1’在插入层25的第二面25b上提供电连接，而裸片3’上的电连接朝向远离插入层25，并且沿与插入层25的第二面25b相同方向的朝向可以直接连接到再分布层33。可选地，裸片3’可以电连接到插入层25，并且经过其连接到BGA封装1’，插入层25例如在其第二面上提供对于裸片5’和裸片3’的触点。作为另一可选方案，可以包括多个裸片和/或嵌入式封装，并且可以按照各种方式连接到插入层25或者直接连接到再分布层33。
如图所示，嵌入式封装1’具有嵌入在其中的裸片5’。然而，设想嵌入式封装1’和封装20二者可以具有嵌入在其中的多个裸片和/或嵌入式封装。在一些应用中，使嵌入式封装1'简单地为衬底或其它各种无源和有源部件会是有用的。在装配封装20之前，可能期望测试并烧录嵌入式封装1’。
密封化合物11’被表示为包围裸片5'，形成一体封装，在本文与插入层25组合地被称为嵌入式封装1’。封装1’的尺寸至少部分地由密封化合物11’的范围(extent)限定，密封化合物11’被表示为延伸到互连层28的边缘。如下面提到的，提供用于层28上的接触焊盘的区域可以由提供对于层28的结构支撑的密封11’的尺寸限定。可选地，嵌入式封装1’可以是标准倒装芯片配置，其中裸片5’由未充满层粘附。
密封化合物21’包围裸片3’、插入层25和嵌入式封装1’(嵌入式封装或本身是已经被嵌入的标准倒装芯片的嵌入式封装)，并且按照这种方式形成被说明为封装20的一体封装。多个通孔31(可选地在本文被称为接触孔)被表示为穿过密封化合物21’从插入层25的第二面25b上的触点延伸到再分布层33。因而建立插入层25的第二面25b到再分布层33之间的电接触，其中导体为在再分布层的一个面上的通孔31和互连焊盘24之间的各自电连接进行布线，焊球23被表示为粘附到互连焊盘24。可以将通孔方便地定位在插入层25的横向尺寸和再分布层33之间，该插入层25的横向尺寸突出或延伸超出芯片3的横向尺寸。
可以根据标准半导体制造工艺来制造裸片3’和5’。也就是说，通常在晶锭生长之后，将其切为晶片。晶片的区域可以经历沉积、移除、构图和掺杂工艺。一旦晶片被处理，该晶片就通常被安装并且被切为单独的裸片。特别地，裸片5’进一步被封装并且被提供为嵌入式封装1’的一部分。
密封化合物11’和21’通常由塑料材料形成，并且可以填充有二氧化硅、金属或陶瓷填充物或者任何其它填料物材料。插入层衬底25可以是印刷电路板，或者可选地是陶瓷或金属，例如引线框。特别地，热固性密封化合物具有基于环氧树脂的塑料材料的类型。这些类型的化合物在历史上用在电子封装应用中。热塑性塑料或叠层以及预浸料坯是可以用作密封化合物的另一类型的塑料材料。预浸料坯是用于“预浸渍”合成纤维的术语，其中诸如环氧树脂的材料已经存在。这些通常采取编织的形式或者是单向的。它们已经包含用于在制造期间将它们粘结在一起并且粘结到其它部件的一定量的基质材料。树脂仅被局部固化以便允许容易的处理，这被称为B阶材料并且要求冷藏以便防止完全固化。B阶预浸料坯总是被存储在冷区域中，因为最常见地通过热量完成完全聚合。因而，由预浸料坯构成的合成结构大多数要求烤炉或高压锅来完成完全聚合。
可以通过穿过密封化合物21’钻孔并且然后使用电传导材料填充所钻的孔来形成通孔31。可以例如使用机械钻、激光器或经过化学蚀刻来执行通孔的钻出。如果使用激光器，则插入层衬底25的铜焊盘可以用作激光钻孔的阻挡件。
封装1’可以被与封装20中的其它部件分开地制造和供应。如上所述，封装1’可以是倒装芯片电子封装、丝焊电子封装或嵌入式晶片级球形栅格阵列(eWLB)电子封装。优选地，例如当与例如在封装20中示出的那些部件组合地进行嵌入时，倒装芯片封装或嵌入式倒装芯片封装用于封装1'，以便例如最小化封装尺寸。嵌入式倒装芯片封装例如将被理解为包含裸片和包围裸片的模具化化合物。在有源芯片面上的裸片焊盘将利用该裸片上的至少一个再分布层或互连层以及实质上与有源芯片表面共面的周围模具化合物区域而被重新布线。在再分布层的端部处应用倒装芯片隆起焊盘，并且通过焊接和后来的未充满来生成倒装芯片互连。位于芯片周围的围绕模具化合物允许处于给定的间距或更大的隆起焊盘间距中的更多倒装芯片隆起焊盘，这对于仅裸片是可能的。
图3是集成堆叠封装36的示例性复合封装30，堆叠封装36具有安装在其上的顶部封装34。封装36被表示为具有与参照图2描述的封装20的结构类似的基本结构。除了参照图2示出和描述的特征，还提供从插入层25的顶部表面25t到位于封装36的表面(例如，顶部表面)上的再分布层33’的通孔35，该封装36的表面与再分布层33的表面相对(例如，提供在其底部层上，如图2所示)。如参照通孔31描述的，通孔35经过密封化合物21’在插入层25和各自的再分布层33’之间提供电接触。
第二封装34被表示为具有与参照图2描述的封装1’的配置类似的配置。特别地，裸片37被表示为经由焊料隆起焊盘和未充满层39电连接到与插入层25类似的插入层/衬底41。然而，衬底41适合于提供有传导互连元件45，其在封装34和36之间建立物理和电连接。因此，封装34被呈现为物理地固定到封装36，从而，单独的互连元件在封装34和36之间建立分立的电连接。传导元件45可以是焊球、诸如连接盘栅格阵列的焊接互连、传导胶或类似物。封装34可以被密封在密封化合物43内。
与参照图2描述的通孔31类似，通孔35可以通过穿过密封化合物21'钻孔来形成，钻孔可以例如使用机械钻、激光器或通过化学蚀刻来执行。
封装34可以与封装36分开地制造和供应，或者可以使用各种封装技术实现，包括倒装芯片和丝焊。此外，封装34可以包含多个裸片，或者可以具有嵌入在其中的一个或多个封装。而且，封装34可以包括各种功能，例如存储器模块和/或传感器。
图4是具有横向堆叠配置的示例性堆叠封装40。可以看到，嵌入式封装1’被横向地接近于裸片47放置，在这一方面中被表示为位于单个再分布层53上。封装40包括具有在底部面上的一组互连焊盘的至少一个再分布或再布线层53。插入层51可以连同裸片47耦合到再分布层53的内部面，或者经由再分布层53的一部分与焊球23至少部分地直接连接。嵌入式封装1’耦合到插入层51的顶部面，并且密封化合物21’密封裸片47、插入层51和嵌入式封装1’。
可以使用封装40的配置，其中在单个封装中期望高密度布线和低密度布线。按照这种方式，在其中插入层51添加到再布线层的图的左侧上再分布层的数量将高于在其中仅出现布线层53的图4的右侧上的数量。在图4中，例如，高密度布线可以在附图的左侧上发生，其中除了位于插入层51下面的再分布层53，插入层51还添加某个水平的较高密度布线。在没有插入层的附图的右侧上，再分布层53可以用于较低密度布线。
图5说明了用于制造堆叠封装的示例性方法50。方法50包括提供50A模具载体，将裸片放置50B在所述模具载体上，将裸片粘附50C到具有耦合到其的封装的插入层，在裸片和封装周围形成50D密封化合物，穿过密封化合物从封装的第一面到插入层钻50E一组通孔，使用电传导材料填充50F该组通孔，并且应用50G电气地再分布该组通孔以便形成一组互连焊盘的再分布层。
裸片粘附膜(DAF)或粘合剂泡沫可以例如用作粘合剂，并且可以经过将粘合剂放置、层叠、印刷或分散到裸片、插入层或裸片和插入层二者上而被应用。
插入层是在一个表面和另一个表面之间提供布线的电气接口，并且将所接口的电气设备，例如嵌入式封装，再布线或扩展到更宽的间距。
嵌入式封装可以具有嵌入在其中的各种部件，例如一个或多个裸片和/或一个或多个嵌入式封装。在一些应用中，使嵌入式封装简单地为衬底或其它各种无源和有源部件会是有用的。
可以例如使用机械钻、激光器或通过化学蚀刻来执行钻孔50E，并且可以例如使用电化学沉积、电镀或通过应用设置在其中的电传导粒子，例如通过印刷，来执行填充50F。此外，可以例如经过薄膜技术(例如，溅射和电解电镀、无电解电镀、减法蚀刻或印刷)来执行应用50G再分布层。
方法50可以进一步包括使密封化合物在其中提供有模具载体的封装反面的面上后退。按照这种方式，封装的厚度可以减小到其最小尺寸。也就是说，可以减小封装的后面面，以使得最少量的密封化合物覆盖裸片和/或嵌入式封装。这可以例如通过研磨封装的后面面和/或通过化学蚀刻来完成。
方法50可以进一步包括将焊球应用到互连焊盘。焊球通常用于使封装与外部电路接口，并且因此在方法50中可以期望包括封装上的这样的接口。此外，方法50可以进一步包括在模具载体上与裸片进行装配之前测试并烧录嵌入式封装。这可以提供增加的可靠性和产量。而且，在与封装一起装配之前测试和烧录嵌入式封装时，可以增加产量。也就是说，有缺陷或不可靠的嵌入式封装不太可能被充分处理到封装中。结果，更完善的封装可靠地工作，并且较不完善的封装结果被丢弃。
方法50可以进一步包括穿过密封化合物从封装的第二面到插入层钻第二组通孔，使用电传导材料填充该第二组通孔，并且在所述封装的第二面上将第二封装安装到该第二组通孔。按照这种方式，可以产生与参照图3描述的配置类似的堆叠封装配置。
分别在图6A-6J中更详细地示出了并且下面更详细地描述了在根据本公开方面的封装的制造中可能的处理流。所公开的处理也说明了所公开的设备的方面，特别是上面在结构上更详细的图2所示的示例性方面。
在如图6A中所示的步骤1中，模具载体62提供有例如双面粘合箔64。这些部件提供在装配期间在其上固定封装的元件的表面。
在如图6B所示的步骤2中，将诸如3’的裸片面向下(有源侧)放置在胶带64上。多个部件可以按照这种方式进行放置，尽管仅示出了一个部件(裸片3’)。
在如图6C所示的步骤3中，将诸如DAF或环氧树脂粘合剂27的胶带或胶水应用到裸片3'的后侧。可选地，粘合剂27可以在图6的处理的步骤2之前被预先应用到裸片3’。
在如图6D所示的步骤4中，将装配的BGA或倒装芯片部件或丝焊BGA(或QFN)1’粘附到DAF 27。所产生的堆叠，裸片/倒装芯片堆叠66，因而被装配在模具载体62上。BGA 1’被表示为具有衬底的完整封装，并且对于倒装芯片示例，具有焊料隆起焊盘29和未充满层。BGA1’可以被包胶模具化，并且裸片5’可以是硅或基于eWLB的嵌入式裸片(在下面的图7中更详细示出)。
在如图6E所示的步骤5中，裸片/倒装芯片堆叠66使用具有密封材料21’的模具化合物被包胶模具化或可选地被层叠。因而装配的封装的样式可以是圆形、矩形或正方形。而且，密封21'可以被应用低轮廓(即，在裸片5'上方具有密封的最少延伸)或者可以被磨掉以便最小化封装尺寸。
在如图6F所示的步骤6中，模具载体62和64(在图6A-6E中示出)被从装配件释放。例如通过加热粘合箔64(即，通过升高整个装配件的温度)来完成释放，直到粘合剂释放该装配件为止。
在如图6G所示的步骤7中，应用电介质材料68。电介质可以经过旋涂被应用并且通过光刻法被构造，或者可以被层叠和激光钻孔或者被蚀刻以便在电介质层中提供结构化开口69。电介质层68是第一衬底或基本衬底61(见图6J，也被标识为图2和图3中的再分布层或再布线层或“载体”)的基础，可以认为在该衬底61上构建封装。下面顺序描述衬底61的剩余部件的示例性配置。
在如图6H所示的步骤8中，穿过模具化合物钻出可以是激光器通孔或蚀刻通孔的通孔31。插入层25上可以是铜的焊盘65可以用作蚀刻/钻孔阻挡件，在钻孔期间设置和/或限制通孔深度。
在如图6I所示的步骤9中，可以例如通过溅射和电镀或者通过无电解电镀和电解电镀或者具有或不具有无电解电镀和电解电镀的印刷来电气地填充通孔31。通孔31可能被塞住。在相同的步骤或随后的步骤中，将再分布层33添加到衬底61以便再分布到通孔31的电连接。
在如图6J所示的步骤10中，焊料阻挡层67被表示为应用到衬底61上，已经在其上被构造。焊球23’或半球可以被应用到焊料阻挡层中的焊盘开口。
在不偏离本公开的精神或者基本特性的情况下，本公开可以体现在其它具体形式中。所描述的方面应该在所有方面中被认为仅是说明性而非限制性的。本公开的范围因此由所附权利要求而不是前述描述来指示。出现在权利要求的等同形式的意义和范围内的所有改变应该被包括在其范围内。
图6所示的处理流的顺序说明了诸如在图2中说明的设备20的堆叠封装的示例性构造序列。逐步构造的说明公开了封装部件之间相互关系的方面，并且并不意在是限制性的或者指定部件或序列的特定组合。例如，图7A-7K说明了在诸如图2的封装20的封装的制造或者装配中的可选处理流。
在如图7A所示的步骤1中，模具载体62提供有粘合剂64，例如双面胶带或箔。在如图7B所示的步骤2中，BGA封装1’面向下(衬底25侧向上，裸片5’侧向下)放置在胶带64上。应该再次注意到，多个部件可以按照这一方式进行放置，例如以便装配图4的封装40，或者包括将被结合到单个封装中的多个横向对齐部件的任何其它组合。
在如图7C所示的步骤3中，诸如DAF或环氧树脂粘合剂的胶带或胶水27’被应用到衬底25。可选地，粘合剂27’可以被预先应用到BGA 1’。在如图7D所示的步骤4中，具有传导加强铝焊盘72(例如铜柱或立柱隆起焊盘)的裸片3’被应用到粘合剂27’上，形成堆叠99。
使用密封材料21’的堆叠99的包胶模具化或层叠以及随后的模具载体64的释放(例如，热释放)在分别在图7E和7F中示出的步骤5和6中发生。
例如通过研磨，密封21’的接触面74的移除可以如图7G所示发生，直到接触柱或隆起焊盘72被暴露为止，隆起焊盘使电传导触点能够暴露，而不损坏裸片3’上的结构。
基本或第一衬底61’的形成以如7H所示的电介质材料68’在接触面74上的应用开始，包括潜地在暴露的接触隆起焊盘72上方。电介质可以被旋涂和/或用光刻法构造，或者可以被涂敷而不构造并且可以与如图7I所示的激光钻孔一起被构造，其中通孔31提供在密封21’中。在步骤9中，通孔31可以通过激光器被钻出或者可以被蚀刻。通孔31在BGA衬底25的焊盘处停止，其中焊盘65可以例如由铜制成并且用作钻孔或蚀刻阻挡件。激光钻孔也可以用于例如根据需要从接触隆起焊盘72移除电介质68’的部分。
在如图7J和7K所示的步骤10和11中，通孔31可以被电气地填充并且可能被塞住。再分布层33可以被同时或者在分开的步骤中应用。焊料阻挡层67可以通过应用在衬底61上而被添加到其上，随后是应用到焊料阻挡层67中的焊盘开口的焊球23’或半球。
另外的或可选的处理步骤会是有利的，例如另外的激光钻孔，以便例如从密封21’的面接入插入层/衬底25上的接触点。可以提供面76上的适当结构化以便允许另外的封装的连接，例如图3的示例性说明，其中通孔31、35分别从插入层/衬底25的各自面沿相反的方向延伸。
在不偏离本公开的精神或基本特性的情况下，本公开可以体现在其它具体的形式中。所描述的本公开的方面应该在所有方面中被认为仅是说明性而非限制性的。本公开的范围因此由所附权利要求而不是前述描述来指示。出现在权利要求的等同形式的意义和范围内的所有改变应该被包括在其范围内。

Claims (17)

1.一种芯片封装，包括：
第一衬底；
第一芯片，布置在所述第一衬底上方；
第二衬底，布置在所述第一芯片上方与所述第一衬底相对的一面上，其中，所述第二衬底包括至少一个触点以及耦合到所述触点的至少一个电传导线，其中，所述第二衬底包括延伸超出所述第一芯片的横向尺寸的突出的横向尺寸部分；以及
第一密封材料，至少局部地嵌入了第二芯片；
第二密封材料，至少局部地密封所述第一密封材料、所述第二芯片、所述第二衬底和所述第一芯片；
至少一个接触孔，穿过所述密封材料延伸以便在所述第二衬底的所述突出的横向尺寸部分中电耦合所述第二衬底的所述至少一个触点；
其中，所述第二芯片被布置在所述第二衬底上方并且在非突出的横向尺寸处电连接到所述第二衬底，以便与所述一个或多个接触孔中的至少一个电连接。
2.如权利要求1所述的芯片封装，其中，所述第二芯片是由球形栅格阵列、连接盘栅格阵列、半球形栅格阵列、引线框封装QFN或QFP封装类型构成的组中的至少一个。
3.如权利要求1所述的芯片封装，其中，所述第二衬底具有至少部分地延伸超出所述第二芯片的横向尺寸的突出的横向尺寸。
4.如权利要求3所述的芯片封装，其中，所述至少一个接触孔在与所述第一芯片相对的一面上从所述第二衬底延伸。
5.如权利要求4所述的芯片封装，其中，所述至少一个接触孔从所述第二衬底的所述至少一个突出的横向尺寸延伸。
6.如权利要求1所述的芯片封装，其中，所述第二芯片是嵌入式封装，并且是预先测试的封装和烧录的封装中的至少一个。
7.一种用于制造堆叠封装的方法，所述方法包括：
提供载体；
将第一芯片放置在所述载体上；
将所述第一芯片和插入层粘附到一起，在所述插入层上方具有耦合到其的芯片封装，所述芯片封装嵌入有第二芯片；
在所述第一芯片、所述插入层和所述芯片封装周围形成密封化合物；
穿过所述密封化合物从所述密封化合物的第一面到所述插入层钻至少一个通孔；
使用电传导材料填充所述至少一个通孔；并且
应用电气地再分布所述至少一个通孔以便形成一组互连焊盘的再分布层。
8.如权利要求7所述的方法，进一步包括将焊球应用到所述互连焊盘。
9.如权利要求7所述的方法，其中，使用激光器执行钻孔。
10.如权利要求7所述的方法，进一步包括在与所述堆叠封装进行装配之前测试所述第二芯片和烧录所述第二芯片中的至少一项。
11.如权利要求7所述的方法，进一步包括：
穿过所述密封化合物从所述堆叠封装的第二面到所述插入层钻第二组通孔；
使用电传导材料填充所述第二组通孔；并且
在所述堆叠封装的所述第二面上将第二电子封装安装到所述第二组通孔上。
12.一种用于制造复合封装的方法，所述方法包括：
提供载体；
将芯片封装放置在所述载体上，所述芯片封装包括连接到插入层的第二芯片；
将第一芯片粘附到所述插入层；
在所述第一芯片和所述芯片封装周围形成密封化合物；
穿过所述密封化合物从所述密封化合物的第一面到所述插入层钻至少一个通孔；
使用电传导材料填充所述至少一个通孔；
应用电气地再分布所述至少一个通孔以便形成至少一个互连焊盘的再分布层。
13.如权利要求12所述的方法，进一步包括将焊球应用到所述互连焊盘。
14.如权利要求12所述的方法，其中，使用激光器来执行钻孔。
15.如权利要求12所述的方法，进一步包括在与所述复合封装进行装配之前测试所述芯片封装和烧录所述芯片封装中的至少一项。
16.如权利要求12所述的方法，进一步包括：
穿过所述密封化合物从所述封装的第二面到所述插入层钻第二组通孔；
使用电传导材料填充所述第二组通孔；并且
在所述封装的所述第二面上将第二电子封装安装到所述第二组通孔上。
17.如权利要求12所述的方法，进一步包括移除所述密封化合物的至少一部分以便暴露所述第一芯片。
CN201410095098.3A 2013-03-15 2014-03-14 芯片堆叠封装及其方法 Active CN104051395B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/833,514 US9312198B2 (en) 2013-03-15 2013-03-15 Chip package-in-package and method thereof
US13/833,514 2013-03-15

Publications (2)

Publication Number Publication Date
CN104051395A CN104051395A (zh) 2014-09-17
CN104051395B true CN104051395B (zh) 2018-01-12

Family

ID=51504053

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410095098.3A Active CN104051395B (zh) 2013-03-15 2014-03-14 芯片堆叠封装及其方法

Country Status (3)

Country Link
US (2) US9312198B2 (zh)
KR (1) KR101594375B1 (zh)
CN (1) CN104051395B (zh)

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090296310A1 (en) * 2008-06-03 2009-12-03 Azuma Chikara Chip capacitor precursors, packaged semiconductors, and assembly method for converting the precursors to capacitors
US9953907B2 (en) * 2013-01-29 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. PoP device
US9735134B2 (en) * 2014-03-12 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with through-vias having tapered ends
US9527723B2 (en) 2014-03-13 2016-12-27 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming microelectromechanical systems (MEMS) package
US9735129B2 (en) 2014-03-21 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9318452B2 (en) * 2014-03-21 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US10177032B2 (en) * 2014-06-18 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaging devices, and methods of packaging semiconductor devices
US9831214B2 (en) * 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
DE102014114933B4 (de) * 2014-10-15 2021-08-12 Infineon Technologies Austria Ag Halbleiterbauelement
KR101640076B1 (ko) * 2014-11-05 2016-07-15 앰코 테크놀로지 코리아 주식회사 웨이퍼 레벨의 칩 적층형 패키지 및 이의 제조 방법
US9799571B2 (en) * 2015-07-15 2017-10-24 Globalfoundries Singapore Pte. Ltd. Methods for producing integrated circuits with interposers and integrated circuits produced from such methods
US10269767B2 (en) 2015-07-31 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip packages with multi-fan-out scheme and methods of manufacturing the same
US20170098629A1 (en) 2015-10-05 2017-04-06 Mediatek Inc. Stacked fan-out package structure
CN106658967B (zh) 2015-10-30 2019-12-20 奥特斯(中国)有限公司 具有不同电荷密度的交替垂直堆叠层结构的元件载体
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
KR20170085833A (ko) * 2016-01-15 2017-07-25 삼성전기주식회사 전자 부품 패키지 및 그 제조방법
JP2017212356A (ja) * 2016-05-26 2017-11-30 京セラ株式会社 積層型基板およびその製造方法
US9991219B2 (en) * 2016-06-23 2018-06-05 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package module
CN106098676A (zh) * 2016-08-15 2016-11-09 黄卫东 多通道堆叠封装结构及封装方法
CN107785334B (zh) * 2016-08-24 2019-11-01 矽品精密工业股份有限公司 电子封装结构及其制法
KR101952862B1 (ko) * 2016-08-30 2019-02-27 삼성전기주식회사 팬-아웃 반도체 패키지
KR101994748B1 (ko) * 2016-09-12 2019-07-01 삼성전기주식회사 팬-아웃 반도체 패키지
US10741537B2 (en) * 2017-01-18 2020-08-11 Taiwan Semiconductor Manufacturing Coompany Ltd. Semiconductor structure and manufacturing method thereof
EP3462486B1 (en) 2017-09-29 2021-03-24 Qorvo US, Inc. Process for making a double-sided module with electromagnetic shielding
US10529693B2 (en) * 2017-11-29 2020-01-07 Advanced Micro Devices, Inc. 3D stacked dies with disparate interconnect footprints
US20190181115A1 (en) 2017-12-08 2019-06-13 Dialog Semiconductor (Uk) Limited Wafer Level Molded PPGA (Pad Post Grid Array) for Low Cost Package
US10431549B2 (en) * 2018-01-10 2019-10-01 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
US10692793B2 (en) * 2018-03-02 2020-06-23 Micron Technology, Inc. Electronic device with a package-level thermal regulator mechanism and associated systems, devices, and methods
US10497635B2 (en) * 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US10742217B2 (en) * 2018-04-12 2020-08-11 Apple Inc. Systems and methods for implementing a scalable system
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
KR102448248B1 (ko) * 2018-05-24 2022-09-27 삼성전자주식회사 Pop형 반도체 패키지 및 그 제조 방법
US10727204B2 (en) 2018-05-29 2020-07-28 Advances Micro Devices, Inc. Die stacking for multi-tier 3D integration
US10910344B2 (en) * 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
US10937755B2 (en) 2018-06-29 2021-03-02 Advanced Micro Devices, Inc. Bond pads for low temperature hybrid bonding
US11075151B2 (en) * 2018-06-29 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package with controllable standoff
US20200075547A1 (en) 2018-08-31 2020-03-05 Qorvo Us, Inc. Double-sided integrated circuit module having an exposed semiconductor die
US11114359B2 (en) 2018-09-13 2021-09-07 Dialog Semiconductor (Uk) Limited Wafer level chip scale package structure
US11984439B2 (en) * 2018-09-14 2024-05-14 Intel Corporation Microelectronic assemblies
KR102536269B1 (ko) * 2018-09-14 2023-05-25 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US10629575B1 (en) * 2018-12-13 2020-04-21 Infineon Techologies Ag Stacked die semiconductor package with electrical interposer
US11239173B2 (en) * 2019-03-28 2022-02-01 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out feature
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11201467B2 (en) 2019-08-22 2021-12-14 Qorvo Us, Inc. Reduced flyback ESD surge protection
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
US20220319954A1 (en) * 2021-03-31 2022-10-06 Texas Instruments Incorporated Package heat dissipation
US20230019333A1 (en) * 2021-07-14 2023-01-19 Qualcomm Incorporated Package comprising stacked integrated devices with overhang

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101681903A (zh) * 2009-03-30 2010-03-24 香港应用科技研究院有限公司 电子封装及其制作方法
CN102487059A (zh) * 2010-12-02 2012-06-06 三星电子株式会社 堆叠式封装结构
CN102931173A (zh) * 2011-08-10 2013-02-13 台湾积体电路制造股份有限公司 多芯片晶圆级封装

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6529022B2 (en) * 2000-12-15 2003-03-04 Eaglestone Pareners I, Llc Wafer testing interposer for a conventional package
US7053476B2 (en) * 2002-09-17 2006-05-30 Chippac, Inc. Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
DE10244664A1 (de) * 2002-09-24 2004-04-01 Infineon Technologies Ag Elektronisches Bauteil mit Halbleiterchips in einem Stapel und Verfahren zur Herstellung desselben
DE10317018A1 (de) * 2003-04-11 2004-11-18 Infineon Technologies Ag Multichipmodul mit mehreren Halbleiterchips sowie Leiterplatte mit mehreren Komponenten
US20070014985A1 (en) 2005-07-14 2007-01-18 Yuan-Huffman Qingwen W Activatable compositions
JP4512545B2 (ja) * 2005-10-27 2010-07-28 パナソニック株式会社 積層型半導体モジュール
SG135074A1 (en) * 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
US7501697B2 (en) * 2006-03-17 2009-03-10 Stats Chippac Ltd. Integrated circuit package system
KR101053746B1 (ko) 2007-05-23 2011-08-02 텍사스 인스트루먼츠 인코포레이티드 반도체 시스템 및 그 제조 방법
US20090041977A1 (en) * 2007-08-06 2009-02-12 Occam Portfolio Llc System for the Manufacture of Electronic Assemblies Without Solder
TWI362101B (en) * 2008-05-29 2012-04-11 Advanced Semiconductor Eng Method of fabricating a stacked type chip package structure and a stacked type package structure
US20100117242A1 (en) * 2008-11-10 2010-05-13 Miller Gary L Technique for packaging multiple integrated circuits
TWI387084B (zh) * 2009-01-23 2013-02-21 Advanced Semiconductor Eng 具有穿導孔之基板及具有穿導孔之基板之封裝結構
US8541872B2 (en) * 2010-06-02 2013-09-24 Stats Chippac Ltd. Integrated circuit package system with package stacking and method of manufacture thereof
US20130147026A1 (en) * 2011-12-12 2013-06-13 Ati Technologies Ulc Heatsink interposer
KR101649404B1 (ko) * 2014-07-28 2016-08-18 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101681903A (zh) * 2009-03-30 2010-03-24 香港应用科技研究院有限公司 电子封装及其制作方法
CN102487059A (zh) * 2010-12-02 2012-06-06 三星电子株式会社 堆叠式封装结构
CN102931173A (zh) * 2011-08-10 2013-02-13 台湾积体电路制造股份有限公司 多芯片晶圆级封装

Also Published As

Publication number Publication date
KR20140113488A (ko) 2014-09-24
US9985005B2 (en) 2018-05-29
US20160190107A1 (en) 2016-06-30
KR101594375B1 (ko) 2016-02-16
US9312198B2 (en) 2016-04-12
CN104051395A (zh) 2014-09-17
US20140264914A1 (en) 2014-09-18

Similar Documents

Publication Publication Date Title
CN104051395B (zh) 芯片堆叠封装及其方法
US10212818B2 (en) Methods and apparatus for a substrate core layer
CN103915414B (zh) 倒装芯片晶片级封装及其方法
KR101277429B1 (ko) 스택 다이 ｂｇａ 또는 ｌｇａ 컴포넌트 어셈블리
US8426246B2 (en) Vented die and package
US6020629A (en) Stacked semiconductor package and method of fabrication
CN104064551B (zh) 一种芯片堆叠封装结构和电子设备
JP5280014B2 (ja) 半導体装置及びその製造方法
KR100851072B1 (ko) 전자 패키지 및 그 제조방법
US20080006936A1 (en) Superfine-circuit semiconductor package structure
KR101837511B1 (ko) 반도체 패키지 및 그 제조방법
US9922917B2 (en) Semiconductor package including substrates spaced by at least one electrical connecting element
JP2007158331A (ja) 半導体デバイスのパッケージング方法
US7432601B2 (en) Semiconductor package and fabrication process thereof
KR101059629B1 (ko) 반도체 패키지 제조방법
US20140239497A1 (en) Packaged semiconductor device
CN110875278A (zh) 半导体封装件
US11450597B2 (en) Semiconductor package substrate having heat dissipating metal sheet on solder pads, method for fabricating the same, and electronic package having the same
KR100836642B1 (ko) 전자 패키지 및 그 제조방법
KR101514525B1 (ko) 반도체 패키지 및 그 제조 방법
KR100836645B1 (ko) 전자 패키지 및 그 제조방법
KR100836657B1 (ko) 전자 패키지 및 그 제조방법
CN118039597A (zh) 一种埋嵌芯片基板结构及制作方法
KR20040091985A (ko) 볼 그리드 어레이 패키지

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: Neubiburg, Germany

Applicant after: Intel Mobile Communications GmbH

Address before: Neubiburg, Germany

Applicant before: Intel Mobile Communications GmbH

COR Change of bibliographic data
GR01 Patent grant
GR01 Patent grant