WO2018137556A1 - 一种功率模块及其制造方法 - Google Patents

一种功率模块及其制造方法 Download PDF

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Publication number
WO2018137556A1
WO2018137556A1 PCT/CN2018/073328 CN2018073328W WO2018137556A1 WO 2018137556 A1 WO2018137556 A1 WO 2018137556A1 CN 2018073328 W CN2018073328 W CN 2018073328W WO 2018137556 A1 WO2018137556 A1 WO 2018137556A1
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Prior art keywords
insulating layer
conductive
conductive layer
layer
power
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PCT/CN2018/073328
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English (en)
French (fr)
Inventor
李慧
杨胜松
廖雯祺
杨钦耀
李艳
张建利
曾秋莲
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比亚迪股份有限公司
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Publication of WO2018137556A1 publication Critical patent/WO2018137556A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array

Definitions

  • the present application relates to the field of hybrid integrated circuits, and in particular to a power module and a method of fabricating the same.
  • a power semiconductor module is a device that packages a plurality of semiconductor chips together in a certain circuit structure.
  • IGBT Insulated Gate Bipolar Transistor
  • the IGBT chip and the diode chip are integrated on a common substrate, and the power device of the power semiconductor module is insulated from the mounting surface thereof (ie, the heat sink) .
  • the power semiconductor module includes a supporting electrical adapter block, which makes the module larger in size and less integrated.
  • the object of the present invention is to provide a power module and a manufacturing method thereof, which are intended to solve the problem that a conventional power semiconductor module needs to be opened and includes a supporting electrical switch block, and the module has a large volume.
  • the invention provides a power module comprising:
  • the insulating dielectric substrate includes a patterned first conductive layer and a first insulating layer disposed on the first conductive layer, the first insulating layer is provided with a first conductive path;
  • a second insulating layer disposed on the first insulating layer, the second insulating layer is provided with a second conductive path;
  • the power semiconductor chip is electrically connected to the first conductive layer through the first conductive path, and electrically connected to the second conductive layer through the second conductive path to constitute a power circuit.
  • the invention also provides a method for manufacturing a power module, comprising the following steps:
  • the insulating dielectric substrate comprising a first conductive layer and a first insulating layer disposed on the first conductive layer;
  • the above power module and its manufacturing method module package do not need to be opened and sealed, which saves production cost; the power semiconductor chip is embedded in the insulating layer of the insulating dielectric substrate, and the upper and lower surfaces of the power semiconductor chip are respectively separated by opening a conductive path on the insulating layer
  • the electrical connection is made with two conductive layers instead of the electrical adapter block, and the conductive layer for soldering the chip is omitted, the volume of the module is reduced, and the module is miniaturized.
  • FIG. 1 is a schematic structural view of a power module according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a power module according to a second embodiment of the present invention.
  • FIG. 3 is a schematic structural view of an embodiment of a power module overall layout
  • Figure 4 is a schematic circuit diagram of a half bridge driving circuit
  • FIG. 5 is a schematic structural diagram of a power module according to another embodiment of the present invention.
  • FIG. 6 is a schematic view showing the overall layout of the power module shown in FIG. 5;
  • FIG. 7 is a schematic structural view of a heat dissipation flat plate according to an embodiment of the present invention.
  • FIG. 8 is a flow chart of a method of fabricating a power module in accordance with a preferred embodiment of the present invention.
  • a power module in a preferred embodiment of the present invention includes an insulating dielectric substrate 10 , at least one power semiconductor chip 20 , a second insulating layer 40 , and a second conductive layer 50 .
  • the insulating dielectric substrate 10 has oppositely disposed upper and lower surfaces, at least one of which is metal-coated, and the intermediate layer is an insulating dielectric layer, that is, the first insulating layer 11.
  • the lower surface of the insulating dielectric substrate 10 is covered with a metal to form a patterned first conductive layer 12, and the upper surface is removed by a metal to expose the insulating dielectric layer, and the first insulating layer 11 is disposed on the first surface.
  • the conductive layer 12 is disposed above the conductive layer 12.
  • the metal coating on the upper surface is first removed to leave a metal layer on the resin layer and the lower surface; A single-sided metal-clad PCB can be used directly. Therefore, in the present embodiment, the first conductive path 14 penetrating the first insulating layer 11 is opened on the insulating dielectric substrate 10. It is to be understood that the use is not limited to the case where a PCB board is used as the insulating dielectric substrate 10, or the case where any other surface-covered metal dielectric substrate is used.
  • the power semiconductor chip 20 in this embodiment includes an IGBT and an FRD (Fast Recovery Diode) to constitute a driving circuit.
  • the power semiconductor chip 20 has a polarity pin on both the upper and lower surfaces.
  • the upper surface has two polarity pins, a gate and an emitter, and a collector on the lower surface.
  • the power semiconductor chip 20 is FRD, the upper surface has an anode, the lower surface has a cathode, or vice versa.
  • the power semiconductor chip 20 is embedded between the first insulating layer 11 and the second insulating layer 40, and is electrically connected to the first conductive layer 12 through the first conductive path 14. Specifically, the power semiconductor chip 20 is embedded in the first insulating layer 11 and the second insulating layer 40 to form a cavity, and the cavity is opened in the first insulating layer 11 and/or A slot (not shown) on the second insulating layer 40 is formed. That is, at least one of the two opposite surfaces of the first insulating layer 11 and the second insulating layer 40 is provided with a slot for receiving the power semiconductor chip 20, or two of the first insulating layer 11 and the second insulating layer 40 are opposite. The surface is simultaneously provided with a slot to form a cavity to receive the power semiconductor chip 20.
  • the slot is in the first insulating layer 11.
  • a circuit pattern is formed on the first conductive layer 12, and a polarity pin of a lower surface thereof is connected to a corresponding circuit pattern forming circuit through the first conductive circuit 14 to be taken out.
  • the insulating dielectric substrate 10 is provided with a first through hole extending from the side of the power semiconductor chip 20 or penetrating the first conductive layer 12, and the first via hole is filled with a conductive material to form the first conductive layer.
  • Path 40 The first vias reach the polarity pins of the lower surface of the power semiconductor chip 20 and the first conductive layer 12, respectively.
  • the first via hole reaching the first conductive layer 12 from the side of the power semiconductor chip 20 means that one end of the first via hole is in contact with the upper surface of the first conductive layer 12.
  • the second insulating layer 40 covers the first insulating layer 11 of the insulating dielectric substrate 10, encloses the first insulating layer 11 to cover the power semiconductor chip 20, and the second insulating layer 40 is laminated.
  • the method covers the insulating dielectric substrate 10.
  • the second insulating layer 40 is provided with a second conductive path 42 through which the power semiconductor chip 20 is electrically connected to the second conductive layer 50 to form a power circuit.
  • the second insulating layer 40 is provided with a second through hole extending from the side of the power semiconductor chip 20 or penetrating the second conductive layer 50 at a predetermined position, and the second via hole is filled with a conductive material.
  • the second via hole reaching the second conductive layer 50 from the side of the power semiconductor chip 20 means that one end of the second via hole is in contact with the lower surface of the second conductive layer 50.
  • the second through holes penetrate the upper and lower surfaces of the second insulating layer 40, and the plurality of through holes 42 penetrate the second insulating layer 40 to reach the polarity pins of the upper surface of the power semiconductor chip 20 and the second conductive layer 50, respectively, preferably Under the premise of the reliability of the combination of the first conductive path 14 and the second conductive path 42 and the chip, the through holes of the same circuit connection path are arranged as much as possible to ensure the overcurrent capability of the circuit and improve the heat dissipation capability of the upper portion of the chip.
  • the second insulating layer 40 is formed by pre-pregnant heating and curing, and simultaneously electrically metalizes the conductive materials in the first through hole and the second through hole during heating;
  • the prepreg Mainly composed of a resin and a reinforcing material may be a fiberglass cloth, a paper base, a composite material or the like, and the coefficient of thermal expansion of the prepreg is matched with the thermal expansion coefficient of the power semiconductor chip 20 to avoid the thermal expansion coefficient of the power device due to the package material. Failure caused by a mismatch in the device is subject to excessive stress.
  • matching means that the values of the two coefficients of thermal expansion are as close as possible or equal.
  • the second conductive layer 50 is disposed on the second insulating layer 40, specifically stacked on the second insulating layer 40 by lamination.
  • the power semiconductor chip 20 is electrically connected to the first conductive layer 12 through the first conductive path 14 formed on the first insulating layer 11, and the second conductive path 42 is opened on the second insulating layer 40.
  • the two conductive layers 50 are electrically connected to form a power circuit, which replaces the electrical adapter block to achieve electrical connection, and omits the conductive layer for soldering the chip, which reduces the volume of the module and facilitates miniaturization of the module.
  • the second conductive layer 50 is a conductive metal sheet, and may be made of a copper sheet, an aluminum sheet or other conductive metal material.
  • the second conductive layer 50 may be made of a metal coated with a lower surface of another insulating dielectric substrate.
  • Another insulating dielectric substrate has opposite upper and lower surfaces, at least one of which is coated with a metal to form the second conductive layer 50.
  • the upper surface may be coated with metal to form another conductive layer, and heat dissipating fins may also be provided.
  • each power semiconductor chip 20 includes an IGBT 21 and an FRD 22.
  • the power module includes a lead terminal 60 (ie, a power module pin), and one end of the lead terminal 60 is fixedly connected to the first insulating layer 11, the first conductive layer 12 or the second conductive layer 50, and is matched with the first conductive layer. 12, the first conductive path 14, the second conductive path 42 and the conductive material in the second conductive layer 50 are electrically connected to the corresponding polarity pins of the IGBT 21 and the FRD 22, and the other end of the lead terminal 60 Outstretched.
  • the lead terminal 60 is for taking the IGBT 21 and the FRD 22 in the form of a preset circuit to take out the terminals of the circuit for connection with an external circuit.
  • the lead terminal 60 may be fixed to the first insulating layer 11 or may be soldered to the first conductive layer 12 or the second conductive layer 50.
  • the lead-out terminal 60 is fixed on the first insulating layer 11, specifically, a groove is formed in the end surface of the first insulating layer 11, and one end of the lead-out terminal 60 is embedded in the groove, and the fixing manner may be lamination or affixing or welding; Electrically connected to the conductive layer through a conductive path.
  • the first terminal insulating layer 11 is fixed to the lead terminal 60 as an example.
  • the lead terminal 60 includes a power terminal 61 and a control terminal 62.
  • the power terminal 61 is two.
  • the control electrode of the IGBT 21 is connected to the control terminal 62 through the second conductive path 42 and the fourth circuit pattern 52 of the second conductive layer 50.
  • the collector is connected to the collector power terminal 61 through the first conductive path 14 and the first conductive layer 12, and the emitter passes through the second conductive path 42 and the second conductive layer 50 and further to the emitter power terminal 61 (in the figure and the collector)
  • the power terminals shown are coincident).
  • FIG. 3 is a schematic diagram of the overall layout of the power module in the embodiment.
  • the filled area in the figure is substantially graphically patterned for the first conductive layer 12, and the blackened area of the wire frame is substantially graphically patterned for the second conductive layer 50.
  • the IGBT 21 and the FRD 22 are buried in the corresponding positions of the first insulating layer 11, and the control terminal 62 and the power terminal 61 are also buried in the corresponding positions of the first insulating layer 11, via the metalized first conductive path 14 and the second conductive path. 42 causes the chip polarity to form an electrical connection with the corresponding terminal.
  • the control terminal 62 and the power terminal 61 are respectively located on both sides of the module, and the low voltage control end is away from the high voltage power end, which reduces the electrical interference of the high voltage end to the low voltage end, and improves the reliability of the control end.
  • each of the power semiconductor chips 20 constitutes a bridge arm to implement a half bridge power module.
  • the upper arm includes an upper bridge IGBT 101 and an upper bridge FRD 103
  • the lower arm includes a lower bridge IGBT 102 and a lower bridge FRD 104.
  • the power semiconductor chip 20 of the above bridge arm is taken as an example.
  • the upper and lower surfaces of the IGBT chip 101 have polar pins.
  • the upper surface of the IGBT chip 101 has two polarity pins, which are a gate and an emitter, respectively.
  • the lower surface has a collector.
  • the upper bridge FRD chip 103 has an anode on its upper surface and a cathode on its lower surface.
  • the power semiconductor chip 20 of the lower arm is the same.
  • the first terminal insulating layer 11 is fixed to the lead terminal as an example.
  • the lead terminal includes a control terminal 32 and a power terminal 31.
  • the control terminal 32 includes two, respectively controlling a first control terminal 321 and a second control terminal 322 of the upper and lower arms
  • the power terminal 31 includes a positive power terminal 311, The AC power terminal 312 and the negative power terminal 313.
  • the positive terminal "+" of the upper bridge is connected to the first circuit pattern 121 of the first conductive layer 12 via the first conductive path 14, and is connected to the positive power terminal 311 via the first conductive path 14.
  • the upper bridge AC terminal " ⁇ " is connected to the third circuit pattern 51 of the second conductive layer 50 via the second conductive path 42, and is connected to the AC power terminal 312 via the second conductive path 42.
  • the lower bridge AC terminal " ⁇ ” is connected to the second circuit pattern 122 of the first conductive layer 12 via the first conductive path 14, and is connected to the AC power terminal 312 via the first conductive path 14.
  • the negative terminal of the lower bridge is connected to the fourth circuit pattern 52 of the second conductive layer 50 via the second conductive path 42 , and is connected to the negative power terminal 313 via the second conductive path 42 .
  • the first control terminal 321 and the second control terminal 322 are buried in the first insulating layer 11 and electrically connected to the chip control terminal via the second conductive path 42.
  • FIG. 6 is a schematic diagram of the overall layout of the power module in the embodiment.
  • the filled area in the figure is substantially graphically patterned for the first conductive layer 12, and the blackened area of the wire frame is substantially graphically patterned for the second conductive layer 50.
  • Each device of the half-bridge driving circuit is buried in a corresponding position of the first insulating layer 11, and the control terminal 32 and the power terminal 31 are also buried in corresponding positions of the first insulating layer 11, and the polarity of the chip is made via the conductive paths 14 and 42.
  • the corresponding terminals form an electrical connection.
  • the control terminal 32 and the power terminal 31 are respectively located on both sides of the module, and the low voltage control end is away from the high voltage power end, which reduces the electrical interference of the high voltage end to the low voltage end, and improves the reliability of the control end.
  • the power module further includes a heat sink 70 that sets the lower surface of the first conductive layer 12 and/or the second conductive The upper surface of layer 50.
  • the heat sink 70 can be separately disposed on the upper surface or the lower surface of the power module to achieve single-sided heat dissipation, or can be disposed on the upper and lower surfaces of the power module to achieve double-sided heat dissipation.
  • the lower surface of the first conductive layer 12 and/or the upper surface of the second conductive layer 50 are connected to the heat sink 70 through the insulating thermally conductive adhesive 80.
  • the heat sink 70 is a heat dissipating fin or a flat heat pipe.
  • Figure 7 is a schematic view of a flat heat pipe.
  • the heat generated by the power semiconductor chip 20 is conducted to the heat pipe evaporation surface 71, and the working fluid 72 in the capillary absorbs heat and vaporizes and fills the vapor chamber.
  • the condensing surface 73 of the flat heat pipe 70 is cooled by circulating cooling liquid.
  • the steam 90 is recondensed into a liquid on the condensation surface 73. Under the action of the capillary suction force of the capillary core 74, the liquid re-flows back to the evaporation surface 71, and the above steps are repeated to achieve circulating heat dissipation.
  • FIGS. 2, 3, 7, and 8 a manufacturing method capable of manufacturing the above power module is further disclosed, including the following steps:
  • an insulating dielectric substrate 10 is disposed.
  • the insulating dielectric substrate 10 includes a first conductive layer 12 and a first insulating layer 11 disposed on the first conductive layer 12.
  • the insulating dielectric substrate 10 is provided to have oppositely disposed upper and lower surfaces, at least one of which is metal-coated.
  • the lower surface of the insulating dielectric substrate 10 is covered with a metal to form a patterned first conductive layer 12, and the upper surface is covered with a metal to remove the insulating dielectric layer 11, which is equivalent to the first insulating layer 11.
  • the first conductive layer 12 Provided on the first conductive layer 12.
  • the metal coating of one of the surfaces is removed to leave the first insulating layer 11 and the metal-clad, that is, the first conductive layer 12;
  • Use a single-sided metal-clad PCB It is to be understood that the use is not limited to the case where a PCB board is used as the insulating dielectric substrate 10, or the case where any other surface-covered metal dielectric substrate is used.
  • step S120 at least one power semiconductor chip 20 is disposed on the first insulating layer 11.
  • the power semiconductor chip 20 includes an IGBT and/or an FRD to constitute a driving circuit.
  • the upper and lower surfaces of the chip each have a polarity pin, and the power semiconductor chip 20 is attached to the upper surface of the insulating dielectric substrate 10.
  • a second insulating layer 40 is disposed on the first insulating dielectric substrate 10 such that the power semiconductor chip 20 is embedded between the first insulating layer 11 and the second insulating layer 40.
  • the power semiconductor chip 20 is embedded in the first insulating layer 11 and the second insulating layer 40 to form a cavity, and the cavity is opened in the first insulating layer 11 and/or A slot (not shown) on the second insulating layer 40 is formed. That is, at least one or two of the opposite surfaces of the first insulating layer 11 and the second insulating layer 40 are simultaneously provided with a slot for enclosing the cavity for receiving the power semiconductor chip 20.
  • the first insulating layer 11 is away from the opening hole on the surface of the first conductive layer 12, and the power semiconductor chip 20 is embedded in the slot.
  • the second insulating layer 40 is a prepreg, and the prepreg is insulated, and the thermal expansion coefficient thereof is matched with the thermal expansion coefficient of the power semiconductor chip 20 as much as possible to avoid the power device from being mismatched with the thermal expansion coefficient of the packaging material. The failure of the device is subject to excessive stress.
  • a second conductive layer 50 is disposed on the second edge layer 40.
  • the second conductive layer 50 is preferably a conductive metal sheet.
  • the second conductive layer 50, the prepreg, and the insulating dielectric substrate 10 provided with the power semiconductor chip 20 are sequentially laminated and pressed to fill the prepreg and cover the power semiconductor chip 20.
  • Step S150 a first conductive path 14 electrically connecting the first conductive layer 12 and the power semiconductor chip 20 is formed on the insulating dielectric substrate 10, and the second insulating layer 40 is opened on the second insulating layer 40.
  • the second conductive layer 50 is electrically connected to the second conductive path 42 of the power semiconductor chip 20.
  • the first conductive layer 12 and the second conductive layer 50 of the laminated module are first patterned. Then, a first via hole penetrating from the first conductive layer 12 side to the polarity pin of the power semiconductor chip 20 is formed on the insulating dielectric substrate 10 by laser technology; the second conductive layer 50 and the insulating layer 40 are formed on the insulating layer 10 Forming a second via hole reaching the polarity pin of the power semiconductor chip 20 by using a laser technology; filling the conductive material with the first and second via holes to metallize the via hole to form the first conductive path 14 and Two conductive paths 42.
  • the first conductive layer 12 and the second conductive layer 50 are required to form a circuit pattern before or after lamination.
  • step S120 further comprising, in step S120, further setting a control terminal 62 and a power terminal 61 such that one end of the control terminal 62 and the power terminal 61 and the first conductive layer 12 or the first insulating layer 11 The step of fixing the connection and extending the other end outward.
  • the control terminal 62 and the power terminal 61 are disposed, and one end of the control terminal 62 and the power terminal 61 is fixedly electrically connected to the second conductive layer 50, and One end extends outward.
  • the control terminal 32 and the power terminal 31 are respectively located on opposite sides of the half bridge power module.
  • the low voltage control terminal is away from the high voltage power terminal, which reduces the electrical interference of the high voltage terminal to the low voltage terminal and improves the reliability of the control terminal.
  • the method further includes the step of heating to cure the prepreg by heating to achieve insulation.
  • the method further includes the step of disposing a heat sink with a lower surface of the first conductive layer 12 and/or an upper surface of the second conductive layer.
  • the above manufacturing method is that the power module is manufactured without encapsulation, and the production cost is saved; the chip is electrically connected through the metalized through hole 42 to reduce the volume of the module and facilitate the miniaturization of the module.
  • the power module is manufactured by removing the copper layer on the surface of the double-sided metal-clad PCB and grooving the PCB resin layer, and burying the top of the power semiconductor chip 20, the control terminal 62, and the power terminal 61.
  • the prepreg (insulating layer) 40 and the second conductive layer 50 of the corresponding thickness are laminated with the dielectric substrate 10 to which the chip is attached, and the flow adhesive of the prepreg 40 is filled and covers the chip.
  • the prepreg 40 is insulative and its coefficient of thermal expansion needs to be as close as possible to the thermal expansion coefficient of the power device.
  • the first conductive layer 12 and the second conductive layer 50 of the laminated module are patterned, and then through holes are formed by laser technology and metallized to form conductive paths 14 and 42 so that the chip polarity pins and the corresponding lead terminals 60 are formed. Electrical connections.
  • the conductive paths 14 and 42 are disposed as much as possible to ensure the reliability of the bonding between the conductive paths 14 and 42 and the chip, so as to ensure the overcurrent capability of the circuit and improve the heat dissipation capability of the upper portion of the chip.
  • this step can be performed to form the through hole 42 after lamination.
  • the lower surface of the module (insulating dielectric substrate 10) is coated with an insulating thermal conductive adhesive 40 and connected to the heat sink 7 for heat dissipation.
  • the upper surface of the module (second conductive layer 50) is coated with an insulating thermal conductive adhesive 80 and then connected to the other heat sink 70 for heat dissipation.
  • the two heat sinks 70 do not necessarily need to be disposed at the same time, and in the case where the heat dissipation condition can be satisfied, the heat sink 70 on the lower surface alone may constitute a single-sided heat dissipation.

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Abstract

一种功率模块及其制造方法，功率模块包括：绝缘介质基板（10），包括第一导电层（12）和设于所述第一导电层（12）之上的第一绝缘层（11），所述第一绝缘层（11）开设有第一导电路径（14）；第二绝缘层（40），所述第二绝缘层（40）开设有第二导电路径（42）；图形化的第二导电层（50）；至少一个功率半导体芯片（20），嵌设于所述第一绝缘层（11）和第二绝缘层（40）之间；其中，所述功率半导体芯片（20）通过所述第一导电路径（14）与所述第一导电层（12）形成电气连接，且通过所述第二导电路径（42）与所述第二导电层（50）形成电气连接。封装无需开塑封模，节省了生产成本；另外，功率半导体芯片（20）通过在绝缘层上开设通孔并填充导电物质与上层的导电层实现电气连接，减小了模块的体积，有利于模块小型化。

Description

一种功率模块及其制造方法
本申请要求于2017年01月24日提交中国专利局、申请号为201710063230.6、申请名称为“一种功率模块及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及混合集成电路领域，特别是涉及一种功率模块及其制造方法。
背景技术
功率半导体模块是将多只半导体芯片按一定的电路结构封装在一起的器件。在一个IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)模块中，IGBT芯片及二极管芯片被集成到一块共同的底板上，且功率半导体模块的功率器件与其安装表面(即散热板)相互绝缘。
传统的功率半导体模块塑封成型需要开模，成本较高；另外，功率半导体模块包含起支撑作用的电气转接块，使得模块体积较大，集成度小。
发明内容
本发明目的在于提供一种功率模块及其制造方法，旨在解决传统的功率半导体模块需要开模，且包含起支撑作用的电气转接块，模块体积较大的问题。
本发明提供了一种功率模块，包括：
绝缘介质基板，包括图形化的第一导电层和设于所述第一导电层之上的第一绝缘层，所述第一绝缘层开设有第一导电路径；
第二绝缘层，设置于所述第一绝缘层之上，所述第二绝缘层开设有第二导电路径；
图形化的第二导电层，设置于所述第二绝缘层之上；
至少一个功率半导体芯片，嵌设于所述第一绝缘层和第二绝缘层之间；
其中，所述功率半导体芯片通过所述第一导电路径与所述第一导电层形成 电气连接，且通过所述第二导电路径与所述第二导电层形成电气连接，以构成功率电路。
本发明还提供了一种功率模块的制造方法，包括以下步骤：
设置一绝缘介质基板，所述绝缘介质基板包括第一导电层和设于所述第一导电层之上的第一绝缘层；
将至少一个功率半导体芯片设于所述第一绝缘层上；
在所述第一绝缘介质基板上设置第二绝缘层，使所述功率半导体芯片嵌设于所述第一绝缘层和第二绝缘层之间；
在所述第二缘层上设置第二导电层；
在所述绝缘介质基板上开设使所述第一导电层和所述功率半导体芯片电气连接的第一导电路径，在所述第二绝缘层上开设使所述第二导电层和所述功率半导体芯片电气连接的第二导电路径。
上述的功率模块及其制造方法模块封装无需开塑封模，节省了生产成本；将功率半导体芯片埋入在绝缘介质基板的绝缘层，通过在绝缘层上开设导电路径使功率半导体芯片的上下表面分别与两个导电层实现电气连接，取代电气转接块实现电气连接，并省略了用于焊接芯片的导电层，减小了模块的体积，有利于模块小型化。
附图说明
图1为本发明第一实施例功率模块的结构示意图；
图2为本发明第二实施例中功率模块的结构示意图；
图3是功率模块整体布局一种实施例的结构示意图；
图4半桥驱动电路的电路原理图；
图5为本发明另一个实施例中功率模块的结构示意图；
图6是图5所示功率模块的整体布局图示意图；
图7为本发明实施例中散热平板的结构示意图；
图8为本发明较佳实施例中功率模块的制造方法的流程图。
具体实施方式
为了使本发明要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
请参阅图1，本发明较佳实施例中的功率模块包括绝缘介质基板10、至少一个功率半导体芯片20、第二绝缘层40及第二导电层50。
绝缘介质基板10具有相对设置的上下表面，其中至少一个表面覆金属，中间层为绝缘介质层即第一绝缘层11。本实施例中，绝缘介质基板10的下表面覆金属形成图形化的第一导电层12，而上表面将覆金属去除使绝缘介质层裸露，相当于第一绝缘层11设于所述第一导电层12之上。
在绝缘介质基板10使用PCB(Printed Circuit Board，印刷电路板)时，由于一般PCB板是双面覆金属，需先将上表面的覆金属去除留下树脂层和下表面的覆金属；当然也可以直接使用单面覆金属的PCB。因此，本实施例中，在绝缘介质基板10开设有穿透第一绝缘层11的第一导电路径14。可以理解的是，不限于使用在使用PCB板作为绝缘介质基板10的情况，或为其他任何表面覆金属绝缘介质基板的情况。
本实施例中的功率半导体芯片20包括IGBT和FRD(Fast Recovery Diode，快速恢复二极管)以构成驱动电路。功率半导体芯片20其上下表面均具有极性引脚，本实施例中，功率半导体芯片20为IGBT时，上表面具有两个极性引脚，分别是门极和发射极，下表面具有集电极。功率半导体芯片20为FRD时，上表面具有阳极，下表面具有阴极，或反之。
功率半导体芯片20嵌设于所述第一绝缘层11和第二绝缘层40之间，通过所述第一导电路径14与所述第一导电层12形成电气连接。具体地，所述功率半导体芯片20嵌于所述第一绝缘层11与所述第二绝缘层40围合形成空腔内，所述空腔由开设在所述第一绝缘层11和/或所述第二绝缘层40上的槽孔(图未示)形成。即第一绝缘层11和第二绝缘层40中两个相对的表面上至少一个开设有用于收容功率半导体芯片20的槽孔，或者第一绝缘层11和第二绝缘层40中两个相对的表面同时开设有槽孔围合形成空腔以收容功率半导体芯 片20，本实施例中，槽孔在第一绝缘层11中。第一导电层12上形成电路图案，其下表面的极性引脚通过第一导电路14与对应的电路图案形成电路连接以引出。
本实施例中，绝缘介质基板10开设有从所述功率半导体芯片20一侧到达或贯穿所述第一导电层12的第一通孔，在第一通孔填充导电物质形成所述第一导电路径40。第一通孔分别到达功率半导体芯片20的下表面的极性引脚和第一导电层12。第一通孔从所述功率半导体芯片20一侧到达所述第一导电层12指的是第一通孔的一端与第一导电层12的上表面接触连接。
第二绝缘层40覆盖于所述绝缘介质基板10的第一绝缘层11上，与第一绝缘层11围合将所述功率半导体芯片20包覆在内，第二绝缘层40通过层压的方式覆盖在绝缘介质基板10上。第二绝缘层40开设有第二导电路径42，功率半导体芯片20通过所述第二导电路径42与所述第二导电层50形成电气连接以构成功率电路。
具体地，第二绝缘层40在预设位置开设有从所述功率半导体芯片20一侧到达或贯穿所述第二导电层50的第二通孔，在所述第二通孔填充导电物质形成所述第二导电路径42。第二通孔从所述功率半导体芯片20一侧到达所述第二导电层50指的是第二通孔的一端与第二导电层50的下表面接触连接。第二通孔贯穿第二绝缘层40上下表面，该多个通孔42贯穿第二绝缘层40分别到达功率半导体芯片20上表面的极性引脚和第二导电层50，优选地，在确保第一导电路径14和第二导电路径42与芯片之间结合的可靠性前提下，同一电路连接路径的通孔尽可能地多设置，以便保证电路的过流能力及提高芯片上部散热能力。
在制作过程中，本实施例中，第二绝缘层40由半固化片(Pre-pregnant)加热并固化形成，加热时同时将第一通孔和第二通孔内的导电物质金属化；其中，半固化片主要由树脂和增强材料组成，增强材料可以为玻纤布、纸基和复合材料等，所述半固化片的热膨胀系数与所述功率半导体芯片20的热膨胀系数匹配，避免功率器件由于与封装材料热膨胀系数不匹配而导致的器件所受的应力过大出现的失效问题。其中，匹配是指两个热膨胀系数的数值尽可能接近或相等。
第二导电层50设置于所述第二绝缘层40之上，具体是通过层压的方式叠设在第二绝缘层40上。
如此，功率半导体芯片20通过开设在所述第一绝缘层11上的第一导电路径14与第一导电层12实现电气连接，通过开设在第二绝缘层40上的第二导电路径42与第二导电层50实现电气连接，以构成功率电路，取代电气转接块实现电气连接，并省略了用于焊接芯片的导电层，减小了模块的体积，有利于模块小型化。
本实施例中，第二导电层50为导电金属片，具体可以是铜片、铝片或者其他导电金属材料制作而成。在其他实施方式中，第二导电层50可以由另一绝缘介质基板的下表面覆金属构成。另一绝缘介质基板具有相对设置的上下表面，其中至少一个表面覆金属构成第二导电层50。而上表面可以覆金属形成另一个导电层，也可以设置散热翅片。
请参阅图2和图3，在一个实施例中，功率模块中至少有一个半导体芯片20，每个功率半导体芯片20包括一个IGBT 21和一个FRD 22。功率模块包括引出端子60(即功率模块引脚)，引出端子60的一端与所述第一绝缘层11、第一导电层12或所述第二导电层50固定连接，并配合第一导电层12、第一导电路径14、第二导电路径42及第二导电层50内的导电物质电气连接到所述IGBT 21和FRD 22相应的极性引脚上，所述引出端子60的另一端向外伸出。引出端子60用于将IGBT 21和FRD 22以预设电路的形式将电路的端子引出以用作与外部电路连接。引出端子60可以固定在第一绝缘层11上，也可以焊接在第一导电层12或第二导电层50上。引出端子60固定在第一绝缘层11上具体是在第一绝缘层11的端面开设凹槽，将引出端子60的一端镶嵌在凹槽内，固定方式可以是层压或贴设或焊接；并通过导电路径与导电层电气连接。
本实施例中，以引出端子60固定在第一绝缘层11为例说明。引出端子60包括功率端子61和控制端子62，功率端子61为两个，IGBT 21的控制极通过第二导电路径42与第二导电层50中的第四电路图案52进而与控制端子62连接，集电极通过第一导电路径14和第一导电层12进而与集电极功率端子61连接，发射极通过第二导电路径42与第二导电层50进而与发射极功率 端子61(图中与集电极所示功率端子重合)连接。
图3是本实施例中功率模块整体布局图示意图。图中填充区域为第一导电层12大致所示图形化，线框加黑区域为第二导电层50大致所示图形化。IGBT21和FRD 22埋入放置于第一绝缘层11对应位置，控制端子62及功率端子61也埋入放置于第一绝缘层11对应位置，经由金属化的第一导电路径14和第二导电路径42使得芯片极性与对应端子形成电气连接。控制端子62及功率端子61分别位于模块两侧，低压控制端远离高压功率端，减小了高压端对低压端的电气干扰，提高了控制端的可靠性。
请参阅图4至图6，在另一个实施例中，功率模块中至少有一对功率半导体芯片20，每个功率半导体芯片20构成一个桥臂，实现半桥功率模块。上桥臂包括上桥IGBT 101和上桥FRD 103，下桥臂包括下桥IGBT 102和下桥FRD104。以上桥臂的功率半导体芯片20为例，IGBT芯片101其上下表面均具有极性引脚，本实施例中，IGBT芯片101上表面具有两个极性引脚，分别是门极和发射极，下表面具有集电极。上桥FRD芯片103上表面具有阳极，下表面具有阴极。下桥臂的功率半导体芯片20同之。
本实施例中，以引出端子固定在第一绝缘层11为例说明。引出端子包括控制端子32和功率端子31，本实施例中，控制端子32包括两个，分别控制上下桥臂的第一控制端子321和第二控制端子322，功率端子31包括正极功率端子311、交流功率端子312及负极功率端子313。上桥正极端“+”经第一导电路径14与第一导电层12中的第一电路图案121连接，再经第一导电路径14与正极功率端子311连接。上桥交流端“～”经第二导电路径42与第二导电层50的第三电路图案51连接，再经第二导电路径42与交流功率端子312连接。下桥交流端“～”经第一导电路径14与第一导电层12中的第二电路图案122连接，再经第一导电路径14与交流功率端子312连接。下桥负极端经第二导电路径42与第二导电层50的第四电路图案52连接，再经第二导电路径42与负极功率端子313连接。第一控制端子321和第二控制端子322埋入第一绝缘层11引出，并经第二导电路径42与芯片控制端形成电气连接。
图6是本实施例中功率模块整体布局图示意图。图中填充区域为第一导电层12大致所示图形化，线框加黑区域为第二导电层50大致所示图形化。半桥 驱动电路的各个器件埋入放置于第一绝缘层11对应位置，控制端子32及功率端子31也埋入放置于第一绝缘层11对应位置，经由导电路径14、42使得芯片极性与对应端子形成电气连接。控制端子32及功率端子31分别位于模块两侧，低压控制端远离高压功率端，减小了高压端对低压端的电气干扰，提高了控制端的可靠性。
另外，在优选的实施例中，请参阅图2、5和7，功率模块还包括散热器70，所述散热器70设置所述第一导电层12的下表面和/或所述第二导电层50的上表面。散热器70可单独设置在功率模块上表面或下表面实现单面散热，也可设置在功率模块上下表面实现双面散热。具体地，第一导电层12的下表面和/或所述第二导电层50的上表面通过绝缘导热胶80后与散热器70连接。散热器70为散热翅片或平板热管。图7是平板热管示意图。功率半导体芯片20产生的热传导到热管蒸发面71，毛细管中工作液72吸收热量汽化并充满蒸汽腔。平板热管70的冷凝面73采用循环冷却液进行冷却。蒸汽90在冷凝面73重新凝结成液体，在毛细芯74的毛吸力作用下，液体重新流回蒸发面71，重复上述步骤实现循环散热。
此外，请结合图2、3、7和8，还公开了一种可制造上述功率模块的制造方法，包括以下步骤：
步骤S110，设置一绝缘介质基板10，所述绝缘介质基板10包括第一导电层12和设于所述第一导电层12之上的第一绝缘层11。
在该步骤中，所提供的绝缘介质基板10应具有相对设置的上下表面，其中至少一个表面覆金属。本实施例中，本实施例中，绝缘介质基板10的下表面覆金属形成图形化的第一导电层12，而上表面将覆金属去除使绝缘介质层11裸露，相当于第一绝缘层11设于所述第一导电层12之上。
在绝缘介质基板10使用双面覆金属的PCB时，将其中一个表面的覆金属去除留下树脂层即第一绝缘层11和另一个表面的覆金属即第一导电层12；当然也可以直接使用单面覆金属的PCB。可以理解的是，不限于使用在使用PCB板作为绝缘介质基板10的情况，或为其他任何表面覆金属绝缘介质基板的情况。
步骤S120，将至少一个功率半导体芯片20设于所述第一绝缘层11上。
具体地，功率半导体芯片20包括IGBT和/或FRD构成驱动电路。芯片上下表面均具有极性引脚，功率半导体芯片20贴设于所述绝缘介质基板10的上表面上。
步骤S130，在所述第一绝缘介质基板10上设置第二绝缘层40，使所述功率半导体芯片20嵌设于所述第一绝缘层11和第二绝缘层40之间。
具体地，所述功率半导体芯片20嵌于所述第一绝缘层11与所述第二绝缘层40围合形成空腔内，所述空腔由开设在所述第一绝缘层11和/或所述第二绝缘层40上的槽孔(图未示)形成。即第一绝缘层11和第二绝缘层40中两个相对的表面上至少一个或两个同时开设有围合形成空腔、用于收容功率半导体芯片20的槽孔本实施例中，在所述第一绝缘层11远离所述第一导电层12一侧表面上的开设槽孔，将所述功率半导体芯片20嵌设于所述槽孔内。
本实施例中，所述第二绝缘层40为半固化片，半固化片是绝缘的，且其热膨胀系数需尽量与功率半导体芯片20的热膨胀系数匹配，避免功率器件由于与封装材料热膨胀系数不匹配而导致的器件所受的应力过大出现的失效问题。
步骤S140，在所述第二缘层40上设置第二导电层50，第二导电层50优选为导电金属片。将所述第二导电层50、半固化片和设有所述功率半导体芯片20的绝缘介质基板10依次层叠压合，使半固化片流胶填充并覆盖功率半导体芯片20。
步骤S150，在所述绝缘介质基板10上开设使所述第一导电层12和所述功率半导体芯片20电气连接的第一导电路径14，在所述第二绝缘层40上开设使所述第二导电层50和所述功率半导体芯片20电气连接的第二导电路径42。
具体地，首先对层压后模块的第一导电层12及第二导电层50图形化。然后在绝缘介质基板10上采用激光技术制作从所述第一导电层12一侧贯穿到所述功率半导体芯片20的极性引脚的第一通孔；在第二导电层50和绝缘层40上采用激光技术制作到达功率半导体芯片20的极性引脚的第二通孔；再在所述第一、第二通孔填充导电物质使通孔金属化形成所述第一导电路径14和第二导电路径42。第一导电层12及第二导电层50在层压之前或之后需制作电 路图案。
更具体的实施例中，在步骤S120中还包括：还设置控制端子62和功率端子61，使所述控制端子62和功率端子61的一端与所述第一导电层12或第一绝缘层11固定连接，另一端向外伸出的步骤。在其他实施方式中，可以设第二导电层50时，设置控制端子62和功率端子61，将使所述控制端子62和功率端子61的一端与所述第二导电层50固定电气连接，另一端向外伸出。，所述控制端子32和功率端子31分别位于所述半桥功率模块相对两侧。低压控制端远离高压功率端，减小了高压端对低压端的电气干扰，提高了控制端的可靠性。
进一步地，所述方法还包括加热的步骤，通过加热使所述半固化片固化实现绝缘。
进一步地，所述方法还包括设置与所述第一导电层12的下表面和/或所述第二导电层的上表面的散热器的步骤。
可见，上述的制作方法均在制作功率模块是封装无需开塑封模，节省了生产成本；芯片通过金属化的通孔42实现电气连接，减小了模块的体积，有利于模块小型化。
更具体地，功率模块的制造方法为：将去除双面覆金属的PCB板上表面的铜层并将PCB树脂层挖槽，功率半导体芯片20、控制端子62及功率端子61顶部均埋入放置于PCB树脂层槽孔中，将相应厚度的半固化片(绝缘层)40、第二导电层50与贴有芯片的绝缘介质基板10进行层压，使半固化片40的流胶填充并覆盖芯片，其中，半固化片40是绝缘的，且其热膨胀系数需尽量与功率器件热膨胀系数匹配。首先对层压后模块的第一导电层12和第二导电层50图形化，再采用激光技术制作通孔并金属化形成导电路径14和42，使得芯片极性引脚与对应引出端子60形成电气连接。在确保导电路径14和42与芯片之间结合的可靠性前提下导电路径14和42尽可能地多设置，以便保证电路的过流能力及提高芯片上部散热能力。其中，通过对绝缘介质基板10的下表面和绝缘介质层11采用激光技术钻开孔14并填充绝缘高导热材料以提高芯片下表面的散热能力，此步骤可以在层压之后制作通孔42的时候同时进行，也可以在准备绝缘基板10时候进行。模块(绝缘介质基板10)下表 面涂上绝缘导热胶40与散热器7连接进行散热，模块(第二导电层50)上表面涂上绝缘导热胶80后与另一个散热器70连接散热，以此实现双面散热，提高散热能力。两个散热器70不一定需要同时设置，在能够满足散热条件情况下，也可仅由下表面的散热器70单独构成单面散热。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制。虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (15)

  1. 一种功率模块，其特征在于，包括：
    绝缘介质基板，包括图形化的第一导电层和设于所述第一导电层之上的第一绝缘层，所述第一绝缘层开设有第一导电路径；
    第二绝缘层，设置于所述第一绝缘层之上，所述第二绝缘层开设有第二导电路径；
    图形化的第二导电层，设置于所述第二绝缘层之上；
    至少一个功率半导体芯片，嵌设于所述第一绝缘层和第二绝缘层之间；
    其中，所述功率半导体芯片通过所述第一导电路径与所述第一导电层形成电气连接，且通过所述第二导电路径与所述第二导电层形成电气连接，以构成功率电路。
  2. 如权利要求1所述的功率模块，其特征在于，所述绝缘介质基板开设有从所述功率半导体芯片一侧到达或贯穿所述第一导电层的第一通孔，在所述第一通孔填充导电物质形成所述第一导电路径；
    所述第二绝缘层开设有从所述功率半导体芯片一侧到达或贯穿所述第二导电层的第二通孔，在所述第二通孔填充导电物质形成所述第二导电路径。
  3. 如权利要求1或2所述的功率模块，其特征在于，所述功率半导体芯片嵌于所述第一绝缘层与所述第二绝缘层围合形成空腔内，所述空腔由开设在所述第一绝缘层和/或所述第二绝缘层上的槽孔形成。
  4. 如权利要求1或3所述的功率模块，其特征在于，还包括引出端子，所述引出端子的一端与第一导电层、第一绝缘层或第二导电层固定连接，并电气连接到所述功率半导体芯片相应的极性引脚上，所述引出端子的另一端向外伸出。
  5. 如权利要求4所述的功率模块，其特征在于，所述引出端子包括控制端子和功率端子，所述控制端子和功率端子分别位于所述半桥功率模块相对两侧。
  6. 如权利要求1-5任意一项所述的功率模块，其特征在于，还包括散热器，所述散热器设置于所述第一导电层的下表面和/或所述第二导电层的上表面。
  7. 如权利要求1-6任意一项所述的功率模块，其特征在于，所述绝缘介质基板为PCB板。
  8. 如权利要求1-7任意一项所述的功率模块，其特征在于，所述绝缘层为半固化片。
  9. 一种功率模块的制造方法，其特征在于，包括以下步骤：
    设置一绝缘介质基板，所述绝缘介质基板包括第一导电层和设于所述第一导电层之上的第一绝缘层；
    将至少一个功率半导体芯片设于所述第一绝缘层上；
    在所述第一绝缘介质基板上设置第二绝缘层，使所述功率半导体芯片嵌设于所述第一绝缘层和第二绝缘层之间；
    在所述第二缘层上设置第二导电层；
    在所述绝缘介质基板上开设使所述第一导电层和所述功率半导体芯片电气连接的第一导电路径，在所述第二绝缘层上开设使所述第二导电层和所述功率半导体芯片电气连接的第二导电路径。
  10. 如权利要求9所述的功率模块的制造方法，其特征在于，在所述绝缘介质基板上开设使所述第一导电层和所述功率半导体芯片电气连接的第一导电路径的步骤具体为：
    在所述绝缘介质基板上开设有从所述第一导电层一侧贯穿到所述功率半导体芯片的极性引脚的第一通孔；
    在所述第一通孔填充导电物质形成所述第一导电路径。
  11. 如权利要求9或10所述的功率模块的制造方法，其特征在于，所述将至少一个功率半导体芯片设于所述第一绝缘层上的步骤具体为：
    在所述第一绝缘层远离所述第一导电层一侧表面上的开设槽孔，将所述功率半导体芯片嵌设于所述槽孔内。
  12. 如权利要求9-11任意一项所述的功率模块的制造方法，其特征在于，在将至少一个功率半导体芯片设于所述第一绝缘层上时，还设置控制端子和功率端子，使所述控制端子和功率端子的一端与所述第一绝缘层固定连接，另一 端向外伸出；或
    设置第二导电层时，设置控制端子和功率端子，使所述控制端子和功率端子的一端与所述第二导电层固定连接，另一端向外伸出；
    其中，所述控制端子和功率端子分别位于所述功率模块相对两侧。
  13. 如权利要求9-12任意一项所述的功率模块的制造方法，其特征在于，所述方法还包括加热的步骤；其中，所述绝缘层为半固化片，通过加热使所述半固化片固化实现绝缘。
  14. 如权利要求9-13任意一项所述的功率模块的制造方法，其特征在于，还包括设置于所述第一导电层的下表面和/或所述第二导电层的上表面的散热器。
  15. 如权利要求9-14任意一项所述的功率模块的制造方法，其特征在于，所述设置一绝缘介质基板具体为：提供一PCB板，去除所述PCB板其中一个表面的覆金属形成所述绝缘介质基板。
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