CN104377172A - 具有嵌入式无源部件的芯片封装件 - Google Patents

具有嵌入式无源部件的芯片封装件 Download PDF

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Publication number
CN104377172A
CN104377172A CN201410361357.2A CN201410361357A CN104377172A CN 104377172 A CN104377172 A CN 104377172A CN 201410361357 A CN201410361357 A CN 201410361357A CN 104377172 A CN104377172 A CN 104377172A
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chip
passive component
semiconductor chip
passive
chip package
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CN201410361357.2A
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CN104377172B (zh
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K·霍塞尼
J·马勒
G·迈耶-伯格
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

一种芯片封装件，包括导电芯片载体和被附着到导电芯片载体的至少一个第一半导体芯片。该芯片封装件还包括无源部件。该导电芯片载体，至少一个第一半导体芯片和无源部件被嵌入在绝缘层合结构中。

Description

具有嵌入式无源部件的芯片封装件
技术领域
本发明涉及半导体芯片封装的技术，并且更具体地涉及具有嵌入式无源部件的半导体芯片封装件。
背景技术
对提供更小、更薄、更轻、更便宜的具有更低的功耗、更多样化的功能和改进的可靠性的电子系统的需求带动了在所涉及的所有技术领域中的一连串技术革新。这对于装配和封装的区域也是正确的，其向小型化的电子系统提供保护性的环境并允许高度的可靠性。
发明内容
根据芯片封装件的一个实施例，芯片封装件包括导电芯片载体，被附着到导电芯片载体的至少一个第一半导体芯片，无源部件，以及绝缘层合结构，该层合结构嵌入有该导电芯片载体，至少一个第一半导体芯片和无源部件。
根据芯片封装件的另一实施例，芯片封装件包括无源部件，至少部分地覆盖无源部件的至少一个主表面的金属层，被附着到金属层的至少一个第一半导体芯片，以及绝缘层合结构，该绝缘层合结构嵌入有该无源部件和至少一个第一半导体芯片。
根据制作芯片封装件的方法的一个实施例，包括：将第二半导体芯片和无源部件安装在彼此上以提供堆叠器件；将至少一个第一半导体芯片安装到导电芯片载体上；并且将电绝缘层层合到该导电芯片载体、至少一个第一半导体芯片、以及堆叠器件上。
本领域技术人员将通过阅读以下的详细描述及观看附图认识到附加的特征和优点。
附图说明
附图被包括以提供对实施例的进一步理解，并且附图被并入且构成本说明书的一部分。附图图示了实施例，并连同说明书一起用于解释实施例的原理。其它实施例和许多的实施方案的预期优点将很容易理解，因为通过参考下面的详细描述变得更好理解。附图中的元件不一定相对于彼此按比例绘制。相同的附图标记表示相应的类似部分。
在不同的附图中的附图标记的区别仅在于前导的数字可指代相似或相同的元件，除非上下文另有说明。添加有后缀“_n”的附图标记指代引用的部分的特定元素。
图1A概略地图示了芯片封装件的一个实施例的截面图，该芯片封装件包括芯片载体、逻辑芯片、功率芯片、无源部件、以及绝缘层合结构。
图1B概略地图示了芯片封装件的一个实施例的截面图，该芯片封装件包括芯片载体、逻辑芯片、功率芯片、无源部件、以及绝缘层合结构。
图2图示了具有安装在引线框架上的无源部件的芯片封装件的截面图。
图3图示了具有在两个电绝缘层之间嵌入的无源部件的芯片封装件的截面图。
图4图示了具有延伸到芯片封装件的顶侧的无源部件的芯片封装件的截面图。
图5图示了具有无源部件和半导体芯片的堆叠的芯片封装件的截面图。
图6图示了具有无源部件和半导体芯片的堆叠的芯片封装件的截面图。
图7图示了具有无源部件和半导体芯片的堆叠的芯片封装件的截面图。
图8图示了具有无源部件和半导体芯片的堆叠的芯片封装件的截面图，该无源部件在其表面上具有金属层。
图9图示了具有安装到引线框架上的半导体芯片和无源部件的堆叠的芯片封装件的截面图。
图10图示了制作具有无源部件和半导体芯片的堆叠的芯片封装件的方法的流程图。
具体实施方式
现在参考附图来说明各个方面和实施例。在下面的描述中，为了解释的目的，许多具体的细节被阐述以便提供对这些实施例的一个或多个方面的彻底理解。应当理解的是，可以利用其他实施例并且可以做出结构或逻辑上的改变而不脱离本发明的精神和范围。还应当指出的是，附图不是按比例绘制或不一定按比例绘制。
在下面的详细描述中参考附图，附图形成了其一部分并且附图通过在其中可以实践本发明的特定实施例的方式显示。然而，它对本领域技术人员可能是显而易见的，这些实施例中的一个或多个方面可以以较少程度的特定的细节而实践。
方位术语，诸如“顶”、“底”、“左”、“右”、“上”、“下”、“前”、“后”、“前导”等参照在本文描述的(多个)图的定向而使用。因为实施例可以被定位在不同的定向，该方位术语仅用于说明的目的而绝不是限制性的。另外，要理解的是，可以利用其他实施例兵器可以做出结构或逻辑上的改变而不脱离本发明的精神和范围。因此，下面的详细说明不应被视为具有限制意义，并且本发明的范围由所附的权利要求所限定。
此外，一个实施例中的特定特征或方面可以仅相对于若干实施方式中的一个，这些特征或方面可以与其它实施方式的一种或多种其他特征或方面相结合，如对于任何给定或特定的应用而言可能期望的及有利的，除非另外特别指出或者除非技术上的限制。此外，在某种程度上，术语“包括”、“具有”、“包含”或其他变体都在详细描述或权利要求中使用，这些术语旨在作为包容性的，以类似于术语“包括”的方式。术语“示例性”仅意味着作为示例，而非最好或最佳的。也应当理解，本文所描述的特征和/或元件为简单和便于理解起见以相对于彼此的特定尺寸被图示特定的尺寸，并且实际的尺寸可以与本文中所示出的显着不同。
如用在本说明书中，术语“键合”、“附着”、“连接”、“耦合”和/或“电连接/电耦合”并不意味着表示该元件或层必须直接联系在一起；也可以在“键合的”、“附着的”、“连接的”、“耦合的”和/或“电连接/电耦合的”元件之间分别设置中间元件或层。然而，根据本公开，上述术语可任选地还具有特定的含义使该元件或层直接接触在一起，即，在“键合的”、“附着的”、“连接的”、“耦合的”和/或“电连接/电耦合的”元件之间分别不设置中间元件或层。
在下面进一步描述的(多个)半导体芯片可以是不同类型的，可以通过不同的技术来制造，并且可以包括，例如，集成的电、光电或机电电路和/或无源器件。(多个)半导体芯片例如可以被配置作为(多个)功率芯片，诸如功率MOSFET(金属氧化物半导体场效应晶体管)、IGBT(绝缘栅双极晶体管)、JFET(结型栅场效应晶体管)、功率双极晶体管或功率二极管。此外，(多个)半导体芯片可以包括控制电路、微处理器或微机电部件。(多个)半导体芯片不需要从特定的半导体材料制成，例如Si、SiC、SiGe、GaAs、以及进而可以包含不是半导体的无机和/或有机材料，诸如绝缘器件、塑料器件或金属器件。
特别是，可以涉及具有垂直结构的(多个)半导体芯片，也就是说，(多个)半导体芯片可以以这样的方式被制作，使电流以垂直于(多个)半导体芯片的主表面的方向流动。具有垂直结构的半导体芯片尤其是在它的两个主表面上可具有接触焊盘，也就是说在其底侧和顶侧。特别是，(多个)功率芯片，即(多个)功率半导体芯片，可以具有垂直结构。通过举例的方式，功率芯片的源极电极和栅极电极，例如功率MOSFET芯片，可以位于一个主表面上，而功率芯片的漏极电极被布置在另一主表面上。
此外，本文所描述的芯片封装件可以包括(多个)逻辑集成电路芯片((多个)逻辑芯片)，其可以控制芯片封装件的其他(多个)半导体芯片。例如，功率芯片的栅既电极可通过来自逻辑芯片的电迹线来控制。在(多个)逻辑芯片的一个实施例中可具有非垂直结构，该非垂直结构包括具有芯片接触电极的有源主表面与不具有芯片接触电极的无源主表面。
(多个)半导体芯片可以具有接触焊盘(或电极)，其允许形成与包括在(多个)半导体芯片中的集成电路的电接触。电极可被全部仅布置在半导体芯片的一个主表面上或被布置在半导体芯片的两个主表面上。它们可以包括被施加到半导体芯片的半导体材料的一个或多个电极金属层。电极金属层可以以任何期望的几何形状和任何期望的材料组合物所制造。例如，它们可以包括或由选自以下组分的组的材料制成：Cu、Ni、NiSn、Au、Ag、Pt、Pd、这些金属的一种或多种的合金、导电有机材料、或导电半导体材料。
一个或多个半导体芯片可以被安装在芯片载体上且被嵌入绝缘层合结构中。绝缘层合结构可以包括至少一个电绝缘层。该至少一个电绝缘层可以具有箔或薄片的形状，其被层合在(多个)半导体芯片和载体的顶部上，或者其被层合到另一电绝缘层上。电绝缘层可以由聚合物材料制成。在一个实施例中，电绝缘层可以由涂有金属层的聚合物材料所制成，该金属层例如为铜层(所谓的RCC(背胶铜箔)箔)。可施加热和压力以适于将电绝缘层附着到底层结构的时间。在层合期间，电绝缘箔片或薄片能够流动(即处于塑性状态)，使得在(多个)半导体芯片或者在芯片载体上或例如芯片载体可形成其一部分的引线框架的其它部分上的其它拓扑结构之间的缝隙被填充有电绝缘箔或薄片的聚合物材料。
电绝缘层可以由任何适当的硬质塑料、热塑性或热固性材料或层合材料制成。在一个实施例中，电绝缘层可以由预浸材料(预浸渍纤维的略称)，其由例如纤维毡和树脂的组合制成，该纤维毡例如玻璃或碳纤维，该树脂例如硬质塑料材料。硬质塑料树脂可以例如基于环氧树脂而制成。预浸材料是本领域已知的，并且通常用于制造PCB(印刷电路板)。在另一个示例中，电绝缘层可以由颗粒增强层合树脂层制成。颗粒也可以由与预浸层的纤维相同的材料制成。在一个示例中，电绝缘层可以由未填充的层合树脂层制成。如上面所提到的，该树脂例如可以是热固性树脂。在又一示例中，电绝缘层可以由热塑性材料制成，其通过在层合期间施加压力和热而熔化并且根据冷却和压力释放而(可逆地)硬化。由热塑性材料制成的层合树脂层也可以是不被填充的，纤维增强的或颗粒增强的。热塑性材料例如可以是聚醚酰亚胺(PEI)、聚醚砜(PES)、聚苯硫醚(PPS)或聚酰胺-酰亚胺(PAI)的组中的一种或多种材料。
绝缘层合结构可以包括被施加到绝缘层合结构的电绝缘层的表面的至少一个导电层，以便于为芯片封装件的部件之间的电再分配提供电迹线或焊盘。导电层例如可以是金属层。导电层可以通过使用沉积工艺施加到电绝缘层，该沉积工艺诸如化学气相沉积、物理气相沉积、化学和电化学技术，例如溅射、电流电镀或化学电镀。在其它实施例中，例如导电箔的导电层可作为整体被施加，例如通过使用层合技术。应当理解，任何这样的术语如“施加”或“沉积”意在字面上涵盖所有将各层施加在彼此上的种类和技术。
导电层可以出于电再分配的目的被构造成提供电迹线或焊盘。通过举例的方式，绝缘层合结构的结构化导电层可以定义再分配层。可以使用各种技术以用于产生结构化导电层。通过举例的方式，可通过(部分)蚀刻来产生结构化导电层。取决于导电材料，可以使用不同的蚀刻剂，其中，例如为氯化铜、氯化铁、HF、NaOH、HNO3、K3Fe(CN)6和KI。蚀刻可以通过使用用于掩盖不被蚀刻的导电层的区域的掩模来完成。掩模可以是在导电层上施加的结构性有机掩模层。结构化有机掩模层可以通过诸如模板印刷、丝网印刷或喷墨印刷之类的印刷技术被施加。在另一个实施例中，例如光刻胶的有机材料的连续层可以被施加到导电层和随后结构化，例如通过光刻以产生结构化的有机掩模层。例如，可以使用旋涂法来施加有机材料的连续层。在其他示例中，可以通过诸如铣削或冲压之类的材料加工技术产生结构化导电层。
绝缘层合结构可以进一步包括贯通连接以便于提供通过绝缘层合结构的电绝缘层的电耦合。通过示例的方式贯通连接可以耦合芯片封装件(诸如芯片载体)的导电元件，(多个)半导体芯片的接触焊盘或绝缘层合结构的结构化导电层。贯通连接可以是过孔(垂直互连接入)。贯通连接或过孔可由开口和填充该开口的导电材料构成。该开口可以以另一导电元件的一部分被暴露的方式垂直地穿过该至少一个电绝缘层。该开口可通过例如常规的钻孔、激光钻孔、化学蚀刻、或任何适当的方法而产生。可以执行利用导电材料填充开口，例如，通过化学气相沉积、物理气相沉积、化学和电化学方法、或任何其它适当的技术。
其上安装有(多个)半导体芯片的导电芯片载体形成芯片封装件的一部分。通过举例的方式，导电芯片载体可以形成引线框的一部分。(多个)半导体芯片可以被安装在引线框架的这部分。绝缘层合结构的电绝缘层可被层合到引线框架上并且安装到其上的(多个)半导体芯片建立覆盖并嵌入(多个)半导体芯片的层合结构。
通过举例的方式，导电芯片载体可以，例如，是PCB(印刷电路板)。印刷电路板可以具有至少一个PCB绝缘层及附于该绝缘层的结构化PCB金属箔层。PCB绝缘层通常基于环氧树脂、聚四氟乙烯、芳族聚酰胺纤维或碳纤维制成，并且可以包括加固装置，诸如纤维毡，例如玻璃纤维或碳纤维。(多个)半导体芯片被安装在结构化PCB金属箔层上。因而，在电绝缘层的层合之后，芯片封装件可以实际上是在其中集成有一个或多个裸芯片的多层PCB。
通过举例的方式，导电芯片载体可以包括陶瓷的板或涂有金属层的陶瓷的板。例如，这种载体可以是DCB(直接铜键合的)陶瓷衬底。
(多个)半导体芯片是经由键合层被键合到导电芯片载体上。在一个实施例中，键合层是由焊料，例如软焊、硬焊或扩散焊所制成的。如果扩散焊接被用作连接技术，焊料材料被使用，其导致在(多个)半导体芯片的电极焊盘、扩散焊键合层和基于界面扩散工艺的芯片载体之间的界面处的焊接操作的结束之后的金属间相。通过举例的方式，也可以使用诸如以下所列的焊料材料，例如，AuSn、AgSn、CuSn、AgIn、AuIn、CuIn、AuSi、Sn或Au。
此外，(多个)半导体芯片可以通过使用可基于环氧树脂或其他聚合物材料并富含例如金、银、镍或铜颗粒的导电粘合剂被键合到芯片载体以便于提供导电性。另外，也能够通过施加所谓的纳米胶或者通过直接沉积金属颗粒及通过随后执行烧结工艺以产生烧结的金属颗粒层来制备包含电互连颗粒的层。
在一个实施例中，无源部件可以被嵌入到芯片封装件的绝缘层合结构中。无源部件可以包括至少一个无源电子器件，诸如电阻器、电容器或电感器。无源部件可包括(多个)集成无源器件，诸如IPD(集成无源器件)芯片。IPD芯片可通过诸如薄膜和光刻技术之类的标准晶片制作技术来制作。用于IPD芯片的衬底可以是比如硅、氧化铝或玻璃的衬底。另一种用于IPD芯片的制作技术可以是例如硅的3D无源集成。无源部件可选地可以是裸IPD芯片。在其它实施例中，包括至少一个无源器件(例如IPD芯片)的无源部件可以具有通过层合或模塑技术形成的壳体。该壳体可以包括电迹线，其将无源部件的至少一个无源电子器件耦合到无源部件的表面上的接触焊盘。无源部件(或无源器件封装件)的接触焊盘可以与针对半导体芯片所描述的相类似。通过举例的方式，嵌入到芯片封装件的绝缘层合结构中并具有诸如(多个)功率芯片和/或(多个)逻辑芯片的(多个)嵌入式半导体芯片的无源部件可以提供各种优点，例如，集成器件的高密度，芯片封装件的高功能性以及在芯片封装件中的电子器件的简单3D封装。
图1A中概略地图示了芯片封装件100A的截面图。芯片封装件100A包括导电芯片载体10。如上所述，芯片载体10可以是平坦的金属板。金属板的材料可以是铜、铝或任何其它合适的材料。通过举例的方式，芯片载体10可以是引线框架或其一部分。在另一个实施方式中，芯片载体10可以包括或由塑料或被涂覆有导电层陶瓷材料制成，该导电层例如为金属箔。
至少一个逻辑芯片20和/或至少一个功率芯片22可以被安装到导电芯片载体10上。半导体芯片20和例如(可选的)半导体芯片22可以被安装到芯片载体10的底侧上。在另一个实施方式中，半导体芯片20和22可以被安装到芯片载体10的顶侧上，或者半导体芯片20和22可以被安装到芯片载体10的不同侧上。逻辑芯片20可以具有非垂直结构，该非垂直结构具有无源表面和与无源表面相对的有源表面。逻辑芯片20的无源表面可以朝向导电芯片载体10并且可以通过电绝缘层21附着到导电芯片载体10。逻辑芯片20的有源表面可以具有被电耦合到逻辑芯片20的集成电路的接触焊盘(未示出)。
在图1A中所示的实施方式中，逻辑芯片20的有源表面可以具有至少两个接触焊盘。逻辑芯片20的第一接触焊盘例如可以被耦合到功率芯片22，以便于控制例如功率芯片22的栅极电极(未示出)。功率芯片22可以具有垂直结构。在一个实施方式中，漏极电极可以是在功率芯片22的一个主表面上并且源极和栅极电极可以是在功率芯片22的另一主表面上。如以举例的方式在图1中示出，功率芯片22的漏极电极可以被附着到导电芯片载体10。与漏极电极相对的栅极电极(未示出)可以被耦合到逻辑芯片20，如以上所述。功率芯片22的源极电极(未示出)可以被连接到任何适当的电连接，例如被连接到芯片封装件100A的电源端子焊盘。
芯片封装件100A可以进一步包括无源部件24。无源部件24可以包括至少一个无源器件，诸如电容器、电阻器、电感器、或实现上述无源器件中的一个或多个的IPD芯片。无源部件24可以进一步包括例如通过层合或模塑技术制成的壳体。无源部件24可以具有在一个主表面上或在两个主表面上的接触焊盘(未示出)。无源部件24的接触焊盘(未示出)可以被电耦合到无源部件24的至少一个无源器件。无源部件24的顶侧可以具有被耦合到无源部件24的至少一个无源器件的至少一个接触焊盘。在另一个实施方式中，无源部件24可以不具有布置在其顶侧表面上的接触焊盘。如图1A所示，无源部件24的底侧例如可以配备有至少一个接触焊盘(未示出)，其被连接到耦合无源部件24和逻辑芯片20的电迹线或贯通连接31。
芯片封装件100A可以进一步包括绝缘层合结构30，其嵌入有导电芯片载体10、逻辑芯片20、功率芯片22和无源部件24。绝缘层合结构30可以包括至少一个电绝缘层。在一个实施例中，如例如在图1A中所示出的，绝缘层合结构30的至少一个电绝缘层可以由第一电绝缘层30a来表示。第一电绝缘层30a可以被层合到芯片载体10的底侧上，使得半导体芯片20和22被安装在其上，并被层合到无源部件24的底侧上。第一电绝缘层30a可以部分地或完全地覆盖无源部件24的一个或所有侧壁和主表面。它可以进一步部分地或完全地覆盖背向芯片载体10的半导体芯片20和(可选的)半导体芯片22，并且可以在不被半导体芯片20和22所覆盖的区域部分地或完全地覆盖芯片载体10的底侧。无源部件24的顶侧和芯片载体10的顶侧例如可以保持不被第一电绝缘层30a所覆盖。
绝缘层合结构30还可以包括贯通连接或过孔31，其提供垂直地穿过绝缘层合结构30的至少一个电绝缘层的至少一个电连接，例如，通过如在图1A中图示的第一电绝缘层30a。另外，贯通连接31可以从功率芯片22的接触焊盘(未示出)、逻辑芯片20或无源部件24延伸到绝缘层合结构30的第一电绝缘层30a的底侧。
绝缘层合结构30还可以包括至少一个结构化导电层。第一结构化导电层32可以被施加在绝缘层合结构30的底侧，例如，如在图1A中图示的电绝缘层30a的底侧。第一结构化导电层32可以包括用于电再分配的电迹线或焊盘。通过举例的方式，第一结构化导电层32可以包括一个耦合功率芯片22与逻辑芯片20的部分和耦合逻辑芯片20与无源部件24的另一部分。
在如图1B所示的另一实施例中，绝缘层合结构30可以包括第二电绝缘层30b，其可以被层合到芯片载体10的顶侧上。第二电绝缘层30b可以部分地或完全地覆盖芯片载体10的顶侧。
此外，如图1B图示的，层合结构30可以包括第三绝缘层30c，其可以被层合到电绝缘层30a的底侧上。在芯片封装件100B的实施方式中，第一结构化导电层32被施加到第三电绝缘层30c的底侧上。耦合第一结构化导电层和例如功率芯片22、逻辑芯片20、或无源部件24的该贯通连接31可以垂直地延伸通过电绝缘层30a和30b。
在一个实施例中，第二结构化导电层(未示出)可以被施加到绝缘层合结构30的顶侧，即第二电绝缘层30b的顶侧。第二结构化导电层可以被配置作为耦合到芯片封装件100B的部件的芯片封装件100B的外部端子并被配置为被耦合诸如应用板的外部电路。
在另一个实施方案中，第三结构化导电层(未示出)可以被施加于绝缘层合结构30的第一电绝缘层30a与第二电绝缘层30b之间。可选地，第三结构化导电层可以被用作再分配层以用于提供类似于第一结构化电绝缘层32的封装内(package-internal)电互连。
无源部件24也可能不像图1B所示般被层合于绝缘层合结构30的第一电绝缘层30a与第二电绝缘层30b之间，而是在第一电绝缘层30a与第三间电绝缘层30c之间。
图2图示了芯片封装件200的示例性实施方式。无需赘言，上面所述的技术、层、材料和方法也可以被应用到在下面进一步解释的图2中的实施方式。
芯片封装件200可以包括芯片载体，不失一般性，它在以下通过例如引线框架210来例示。引线框架210(即芯片载体)可以具有介于100微米与500微米的范围内的厚度，更具体地说约250微米。引线框架210可以包括第一部分210_1、第二部分210_2、第三部分210_3和第四部分210_4，它们彼此分离。引线框架210可以是导电的，并且例如可以由铜制成。
芯片封装200可以是包括至少两个芯片的多芯片封装件，该两个芯片例如一个逻辑芯片和一个功率芯片。通过举例的方式，如图2所示，芯片封装件200可以进一步包括逻辑芯片220、第一功率芯片222，以及例如第二功率芯片226。芯片220、222和226可以被安装到引线框架210的底侧上。在另一实施方式中，芯片220、222和226可以被安装到引线框架210的顶侧上，或者可以被安装到引线框架210的不同侧上。如图2所示，逻辑芯片220和功率芯片222可以被安装到引线框架210的第一部分210_1的底侧上并且功率芯片226可以被安装到引线框架210的第二部分210_2的底侧上。
如之前所描述的，逻辑芯片220可以具有非垂直的芯片结构，它包括例如半导体芯片的接触焊盘的有源主表面以及不具有接触焊盘的无源主表面。逻辑芯片220的无源主表面可以通过电绝缘层221从导电引线框架210电绝缘。例如，电绝缘层221例如可以是电绝缘性粘合剂。在一个实施方式中，电绝缘层221可以被集成到逻辑芯片221并作为芯片结构的一部分，例如作为诸如氧化物或氮化物层之类的硬钝化层。
此外，例如，第一和第二功率芯片222和226可以具有垂直芯片结构。因而，通过举例的方式，功率芯片222和226的漏极电极焊盘(未在图2中示出)可以分别被机械地安装并被电耦合到引线框架部分210_1和210_2。功率芯片222和226背向引线框架210的相对的主表面可以提供用于源极电极(未示出)和栅极电极(未示出)的接触焊盘。例如，第一功率芯片222的源极电极可以被耦合到第二部分210_2并且第二功率芯片226的源极电极可以被耦合到引线框架210的第三部分210_3。第一功率芯片222的栅极电极可以被耦合到逻辑芯片220的接触焊盘。并且，第二功率芯片226的栅极电极可以被耦合到逻辑芯片220(然而这没有在图2中示出)，因为连接迹线可能在截面图的平面以外。
芯片封装件200可以进一步包括无源部件224。无源部件224可以被安装到引线框架210的第四部分210_4的底侧上。在另一个实施方式中，无源部件224可以被安装到芯片载体210的第四部分210_4的顶侧上，或者无源部件224可以被安装到引线框架210的另一部分上。在一个实施方式中，无源部件224的顶侧可以具有至少一个接触焊盘(未示出)，其被电耦合到无源部件224的至少一个无源器件。如图2所示，无源部件224的顶侧可以被机械地安装并被直接耦合到引线框架210的第四部分210_4。在另一个实施方式中，无源部件224的顶侧在该表面上可以不具有接触焊盘。无源部件224的底侧，如图2的实施方式中所示，可以具有多个(例如5个)接触焊盘，其由连接到接触焊盘的贯通连接231间接地示出。
芯片封装件200可以进一步包括绝缘层合结构230。绝缘层合结构230可以以同样的方式并且以如上相对于图1A和图1B所述相同的程度被嵌入引线框架210、逻辑芯片220、第一功率芯片222、第二功率芯片226和无源部件224。也就是说，在一个实施例中，绝缘层合结构230可以包括被安装到引线框架210的底侧上的第一电绝缘层230a，被安装到引线框架210的顶侧上的可选的第二电绝缘层230b，以及被附着到第一电绝缘层230a的底侧的可选的第三电绝缘层230c，其中逻辑芯片220、第一功率芯片222、第二功率芯片226和无源部件224被安装到第一电绝缘层230a上。第一电绝缘层230a的厚度可以介于50微米与500微米之间，且更具体地说，大约为100微米。第二电绝缘层230b的厚度可以介于20微米与100微米之间，且更具体地说，大约为45微米。第三电绝缘层230c的厚度可以介于20微米与200微米之间，且更具体地说，大约为50微米。
第二电绝缘层230b可以被省略。在这种情况下，它对应于图1A的芯片封装件100A的实施方式，引线框架210的部分210_1、210_2、210_3和/或210_4中的一个或多个的顶侧可以保持暴露并且本身可以用作被配置为安装到热沉上或应用板上的外部端子。
此外，芯片封装件200例如可以包括第一结构化导电层232、第二结构化导电层236和第三结构化导电层234。第三结构化导电层234可以被嵌入在绝缘层合结构230的两个电绝缘层之间，例如在层230a和230c之间。第一结构化导电层232可以被施加到绝缘层合结构230的底侧表面。第二结构化导电层236可以被施加到绝缘层合结构230的顶侧表面。
第一结构化导电层232和第三结构化导电层234可以用作电再分配结构，其提供介于逻辑芯片220、功率芯片222和226、无源部件224和/或引线框架210的部分210_1、210_2、210_3、210_4的电极焊盘之间的互连。第三结构化导电层234是可选的并且在不需要它的情况下可以被省略。第一和第三导电层232和234的厚度可以在5微米和100微米之间，且更具体地说，大约为40微米。
如图2中图示的第二结构化导电层236可以被配置作为芯片封装件200的外部接触焊盘(即外部端子)。第二结构化导电层236例如可以包括被电耦合到引线框架的第一部分210_1的第一外部接触焊盘，被电连接到第二部分210_2的第二外部接触焊盘，被电连接到第三部分210_3的第三外部接触焊盘以及被电耦合到第四部分210_4的第四外接触焊盘。第二结构化导电层236可以任选地由安装在层236的顶部上的附加层238所加固。层238可以是金属层，诸如铜层，以用于例如外部接触焊盘焊接到应用板。也就是说，第二结构化导电层236与可选的加强层238可以限定芯片封装件200的覆盖区。第二结构化导电层236加上可选的加强层238的厚度可以介于5微米与100微米之间，且更具体地说，大约为50微米。
芯片封装件200的绝缘层合结构230可以包括至少一个过孔或贯通连接231。该至少一个贯通连接231可以提供通过绝缘层合结构230的一个或多个电绝缘层的电连接，例如通过层230a、230b、和/或230c。通过举例的方式，引线框架210和/或半导体芯片220、222、226和无源部件224的接触焊盘的底侧可以通过贯通连接231被电耦合到第三结构化导电层234或耦合到第一结构化导电层232。第一结构化导电层232可以通过贯通连接231被电耦合到第三结构化导电层234。第二结构化导电层236例如可以通过贯通连接231被电耦合到引线框架210的顶侧。
在图2中所示的芯片封装件200可以任选地包括施加到具有第一结构化导电层232在其上的绝缘层合结构230的底侧的电绝缘层240。例如，电绝缘层240可以通过层合方法或通过任何其它适当的方法而施加。电绝缘层240可以部分地或完全地覆盖第一结构化导电层232。电绝缘层240可以用作保护层以便于防止受到环境的攻击，例如由机械、化学或其它类型的冲击造成的芯片封装件200的底侧的可能损坏。
在图3中示出了芯片封装件300的一个实施方式。图3中的芯片封装件300的实施方式与图2中的芯片封装件200的实施方式相同，不同之处在于无源部件324没有被安装到引线框架310。此外，引线框架310例如可以只包括三个部分，第一部分310_1、第二部分310_2和第三部分310_3。
如图3所示，无源部件324通过层合技术可被嵌入在绝缘层和结构330的第一电绝缘层330a与第三电绝缘层330c之间。在另一个实施方式中，无源部件324可以通过层合技术被嵌入在第一电绝缘层330a的顶侧处，类似于图1A的芯片封装件100A的实施方式，使得第二电绝缘层230b被施加或不被施加在第一电绝缘层330a的顶侧上。在该实施方式中，第三电绝缘层330c可以在不需要的情况下被省略。
芯片封装件300的无源部件324可以具有底侧，该底侧可以具有耦合到无源部件324的至少一个无源器件的接触焊盘。如通过贯通连接331被附着到无源部件324的底侧所示，无源部件324可以包括多个(例如至少五个)接触焊盘。无源部件的顶侧可以不具有接触焊盘。在其他实施方式中，无源部件324的顶侧可以包括接触焊盘。
图4图示了与在图3中的芯片封装件300的实施例相同或类似的示范性芯片封装件400的实施方式，不同的是无源部件424的顶侧具有至少一个连接焊盘，其被直接连接到芯片封装件400的外部端子或者其本身被配置作为芯片封装件400的外部端子。无源部件424的顶侧可以保持不被绝缘层和结构430的任何电绝缘层所覆盖。
在芯片封装件400的实施方式中，在绝缘层合结构430被施加到芯片封装件400之后，芯片封装件424可以被插入到绝缘层合结构430中，该绝缘层合结构430包括第一电绝缘层430a、第二电绝缘层430b和第三电绝缘层430c。这可以在通过例如常规的钻孔、激光钻孔、蚀刻、冲压、或通过任何其它适当的方法插入芯片封装件424之前通过在绝缘层合结构430的顶侧中形成开口而实施。该开口可以在层合之后或层合之前被形成(即可以是预先形成的开口)。该开口可以被形成在绝缘层合结构430的顶侧的一部分处，其在垂直投影中是在引线框架410的一部分的轮廓的横向外侧。该开口的至少一个或所有横向尺寸可以对应于芯片封装件424的至少一个或所有的横向尺寸。该开口的深度可以是至少第二电绝缘层430b的厚度，并且可以通过第一电绝缘层430a延伸到第三电绝缘层430c中。无源部件424可以以具有被配置作为例如外部端子的接触焊盘的顶侧与绝缘层合结构430的顶侧在相同的平面的方式被插入到开口中。任选地，第二结构化导电层436和在层436的顶部上的加强层438可以覆盖并耦合到无源部件424的外部端子。如上文所述，具有加强层438在顶部的第二结构化导电层436可以限定芯片封装件400的覆盖区。无源部件424可以被直接耦合到芯片封装件400的覆盖区或者可以是芯片封装件400的覆盖区的一部分。
在另一个实施方式中，无源部件424可以从绝缘层合结构430的底侧，即从第三电绝缘层430c的底侧或者从第一电绝缘层430a的底侧，以与上文所述类似的方式被插入到绝缘层压结构430中。在该情况下，无源部件424的外部端子可以经由再分配结构和/或贯通连接被连接到第二结构化导电层436以便于被耦合到芯片封装件400的覆盖区。
图5图示了示例性芯片封装件500的实施方式。无需赘言，上文所描述的技术、层、材料和方法也可以被应用到在下面进一步解释的图5中的实施方式。
芯片封装件500可以包括具有多个单独部分，例如第一部分510_1、第二部分510_2、第三部分510_3和第四部分510_4的导电引线框架510。引线框架可以例如由铜所制成。此外，引线框架510可以具有在100微米与500微米之间的范围内的厚度，并且更具体地说，大约为250微米。
芯片封装500可以包括无源部件524，其可以被定位在由引线框架所限定的平面内或穿过该平面，该平面例如由引线框架510的下表面或上表面所定义。无源部件524可以从引线框架510分离。无源部件524可以在其顶侧上和/或在其底侧上具有接触焊盘。如上所述，接触焊盘通过附着到相应的接触焊盘的贯通连接531所间接地指示。
另外，无源部件524可以被配置为用作针对半导体芯片的载体。如图在图5的实施方式中所示，无源部件524的底侧的一部分可以被用于将半导体芯片安装到其上。无源部件524的底侧表面和/或顶侧表面可以分别与引线框架的底和/或顶表面共面。半导体芯片可以被安装到无源部件524的底侧上，并且可以形成堆叠式器件，即无源部件524与半导体芯片的堆叠。在另一个实施方式中，半导体芯片可以被安装到无源部件524的顶侧上。同样在另一个实施方式中，无源部件524和半导体芯片的堆叠可以在封装过程期间，例如在半导体芯片被安装到引线框架上时被产生。在另一个实施例中，无源部件524和半导体芯片的堆叠作为一个整体可以被预先制造并层合到芯片封装件500中。
安装到芯片封装件500中的无源部件524的底侧的半导体芯片例如可以是逻辑芯片520。逻辑芯片520可以被安装成使其无源表面(在逻辑芯片520的顶侧)在无源部件524的底侧上被引导。在无源部件524与逻辑芯片520之间，可以施加电绝缘层521。如上所述，电绝缘层521例如可以是用于将芯片520附着到无源部件524的电绝缘粘合剂。在另一实施方式中，电绝缘层521可以构成逻辑芯片520的一部分并且逻辑芯片520可以通过任何适当的方法被安装到无源部件524上。逻辑芯片520的有源表面可以是逻辑芯片520的底侧。如图5所示，逻辑芯片510例如可以包括六个接触焊盘，其通过贯通连接531被附着到逻辑芯片520而被间接地示出。接触焊盘中的一个或多个(例如两个)可以在无源部件524的底侧处被耦合到接触焊盘。
芯片封装件500可以进一步包括第一功率芯片522和第二功率芯片526。第一功率芯片522可以被附着到引线框架510的第一部分510_1。第二功率芯片526可以被附着到引线框架510的第二部分510_2。功率芯片522和526可以具有垂直结构。功率芯片的漏极电极，其可以在功率芯片522和526的顶侧，可以被机械地安装并电耦合到引线框架510。电源芯片522和526的相对的表面，其背向引线框架510，可以提供功率芯片的源极电极(未示出)和栅极电极(未示出)的接触焊盘。
芯片封装件500进一步包括绝缘层合结构530。以与结合图1A、1B和2所描述的相同的方法和相同的程度，绝缘层合结构530可以嵌入具有功率芯片522和526安装在其上的引线框架510以及具有逻辑芯片520安装在其上的无源部件524。也就是说，在一个实施例中，绝缘层合结构530可以包括第一电绝缘层530a，其被施加到具有功率芯片522和526被安装在其上的引线框架510的底侧上并被施加到具有逻辑芯片520被安装在其上的无源部件524的底侧上。绝缘层合结构530可以进一步包括可选地安装在引线框架510和无源部件524的顶侧上的第二电绝缘层530b以及可选地被附着到第一电绝缘层530a的底侧的第三电绝缘层530c。第一电绝缘层530a的厚度可以在50微米与500微米之间，更具体地说大约为100微米。第二电绝缘层530b的厚度可以在20微米与100微米之间，更具体地说大约为45微米。第三电绝缘层530c的厚度可以在20微米与200微米之间，更具体地说大约为50微米。
第二电绝缘层530b可以被省略。在该情况下，引线框架510的部分510_1、510_2、510_3和/或510_4的一个或多个的顶侧可以保持暴露并且其本身可以用作被配置为安装在热沉上或应用板上的外部端子。
此外，芯片封装件500可以包括以下部件：第一结构化导电层532；第二结构化导电层536；第三结构化导电层534；加强层538；至少一个贯通连接531；以及保护的电绝缘层540。芯片封装件500的这些部件的这些特征和布置方式，其也包括在芯片封装件200中，可以与用于芯片封装200的相同或相似。因此，为了避免重复，对于这些部件可以参考芯片封装件200的描述。与芯片封装件200的一个差异是第二结构化导电层536额外包括被电耦合到无源部件524的第五外部接触焊盘(外部端子)。
图6显示了示例性芯片封装件600。芯片封装件600的实施方式与图5中的芯片封装件500的实施方式相同或相似，不同之处在于代替无源部件524的是，逻辑芯片620可以被定位在由引线框架610所限定的平面内或穿过该平面(例如通过引线框架610的下表面或上表面)并且可以被配置为用作无源部件624的载体。为了避免重复，除非另外指出，对于芯片封装件600的部件的特征和布置方式可以参考芯片封装件200的描述特别是芯片封装件500的描述。
在芯片封装件600的实施方式中，无源部件624可以被安装到逻辑芯片620的底侧上。此外，逻辑芯片620可以具有例如作为有源表面的顶侧和具有例如附加的接触焊盘(例如通过TSV(硅通孔)产生的)的底侧。底侧的其中无源部件624可以被安装的一部分可以不具有接触焊盘。可选地，电绝缘层621可以被施加在逻辑芯片620与无源部件624之间。
图7示出了示例性芯片封装件700。芯片封装件700的实施方式与在图5中的芯片封装件500的实施方式相同或相似，不同之处在于逻辑芯片720可以具有通孔723，例如TSV，其将逻辑芯片720的底侧电耦合到在其顶侧的接触焊盘，该通孔本身在无源部件724的底侧处被耦合到接触焊盘。为了避免重复，除非另外指出，对于芯片封装件700的部件的特征和布置方式可以参考芯片封装件200的描述特别是芯片封装件500的描述。
逻辑芯片720可以具有作为无源表面的顶侧和底侧，该底侧可以是具有被耦合到逻辑芯片720的集成电路的接触焊盘(未示出)的有源表面。逻辑芯片720的至少一个通孔或硅通孔(TSV)723可以连接到在逻辑芯片720的顶侧的至少一个接触焊盘。
在一个实施例中，逻辑芯片720可以通过由上述的焊料形成的键合层被附着到无源部件724。至少一个焊球725可以被施加到在逻辑芯片720的顶侧处的至少一个接触焊盘，以用于将逻辑芯片720机械地附着并电耦合到无源部件724的底侧。此外，逻辑芯片720的顶侧可以包括焊球725的阵列。焊球725的阵列可以被耦合到无源部件724的接触焊盘的相应阵列。
此外，逻辑芯片720被安装在倒装芯片取向的无源部件724上也是可能的。在该情况下，逻辑芯片720的有源表面面对无源部件724的底表面。例如，TSV可被省略。在这两种情况下(正常和倒装芯片安装)，在逻辑芯片720通过焊球725被附着到无源部件724之后，电绝缘层723(例如所谓的底部填充层)可以任选地被施加在逻辑芯片720与无源部件724之间。
任何其他适当的方法可以被用来将在逻辑芯片720的顶侧处的接触焊盘机械地附着及电耦合到在无源部件724的底侧处的接触焊盘。例如，可以使用如上文所述的导电粘合剂。
在一个实施方式中，无源部件724和逻辑芯片720的堆叠可以在封装过程期间，例如当功率芯片722和726可以被安装到引线框架710上时被实施。然而，在另一个实施方式中，无源部件724和逻辑芯片720的堆叠可以提前进行并且预制作的堆叠器件可以作为一个整体被嵌入在芯片封装件700中。
图8显示了示例性芯片封装件800的一个实施方式。芯片封装件800的实施方式与图5中的芯片封装件500的实施方式相同，不同之处在于功率芯片822和826也安装在无源部件828_1和828_2上，其中，无源部件828_1和828_2的表面可以至少部分地或完全地分别由金属层829_1和829_2涂覆。为了避免重复，除非另外指出，对于芯片封装件800的部件的特征和布置方式可以参考芯片封装件200的描述特别是芯片封装件500的描述。
如图8所示，芯片封装件800的引线框810的第一部分810_1和第二部分810_2对应于芯片封装件500的引线框架510的第三部分510_3和第四部分510_4。此外，芯片封装件500的引线框架510的第一部分510_1和第二部分510_2在图8的实施方式中被无源部件828_1和828_2代替。
金属层829_1和829_2可以部分地或完全地覆盖无源部件828_1和828_2的至少一个侧壁和/或至少一个或两个主表面。通过举例的方式，半导体芯片822的轮廓可以在无源部件828_1的底表面上限定表面区域，其中金属层829_1覆盖例如等于或超过或无源部件828_1的整体底表面的或表面区域的50％，80％或100％。金属层829_1和829_2可以用作电触点，例如半导体功率芯片822、826各自的漏极触点，以及作为热导体以用于将在功率半导体芯片822、826产生的热量驱散到芯片封装件800的外部接触焊盘836。在芯片封装件800的实施方式中，金属层829_1和829_2例如可以被完全涂在无源部件828_1或828_2的所有侧/表面以提供最小电阻和最大传热能力。在该实施方式中，芯片封装件800的其它元件的布置和特征，诸如贯通连接831或第一和第三结构化导电层832和834，可以是类似于芯片封装件500的实施方式。在另一个实施方式中，金属层829_1或829_2可以是结构化层，其提供从无源部件828_1和828_2的底表面延伸至其顶表面的电和热迹线。通过举例的方式，金属层829_1和829_2可以由铜制成。
功率芯片822可以在无源部件828_1的底侧被机械地安装及电耦合到金属层829_1。以同样的方式，功率芯片826可以在无源部件828_2的底侧被机械地安装及电耦合到金属层829_2。功率芯片822和826可以以相同的方式被附着到无源部件828_1和828_2，该方式例如为功率芯片222和226可被附着到在芯片封装件200的实施方式中的引线框元件210_1和210_2。换言之，具有涂覆在其表面上的金属层829_1和/或829_2的无源部件828_1和/或828_2可以被用作芯片载体而取代例如引线框架。涂覆有金属的无源部件828_1和/或828_2的底侧表面和/或和顶侧表面以及例如无源部件824的底侧表面和/或顶侧表面可以是共面的。在芯片封装件800中，芯片载体(引线框架)完全由无源部件828_1、828_2和824实现是可能的。在该情况下，不需要引线框架。
在一个实施例中，在其表面上涂覆有金属层829_1或829_2的无源部件828_1或828_2和在其上的各自的功率芯片822或826的堆叠可以在封装过程期间产生，例如在施加绝缘层合结构830的第一电绝缘层830a之前。在另一个实施例中，在其表面上涂覆有金属层829_1或829_2的无源部件828_1或828_2和在其上的各自的功率芯片822或826的堆叠器件作为一个整体可以被预先制造并被嵌入层合结构830。
图9显示了示例性芯片封装件900的一个实施方式。芯片封装件900的实施方式与图5中的芯片封装件500的实施方式相同或相似，不同之处在于无源部件924和逻辑芯片920的堆叠可以被安装在引线框架910的第一部分910_1上。为了避免重复，除非另外指出，对于芯片封装件900的部件的特征和布置方式可以参考芯片封装件200的描述特别是芯片封装件500的描述。
在一个实施例中，无源部件924的顶侧可以安装到引线框架910的第一部分910_1的底侧上，其中无源部件924不被电连接到引线框架910。在另一个实施方式中，无源部件924的顶侧的至少一个接触焊盘可以被电耦合到引线框910。无源部件924可以被附着到引线框910的第一部分910_1，例如经由如上所述的键合层或粘合剂。此后，逻辑芯片920的顶侧可以被施加到无源部件924的底侧并使得电绝缘层921被施加在其间。逻辑芯片920的顶侧可以是无源侧或例如有源侧(例如，当使用如前所述的倒装芯片安装技术时)。
无源部件924和逻辑芯片920的堆叠可以被预先制造，使得该堆叠可作为一个整体被安装到引线框架的第一部分910_1的底侧上。
无源部件924与半导体芯片的堆叠可以尤其是与图7中的芯片封装件700或图8中的芯片封装件800的实施方式的描述相类似。例如，逻辑芯片920可以包括通孔，其类似于通孔723，被耦合到无源部件924，或金属层可以类似于金属层829_1或829_2至少部分地被涂覆到无源部件924上。在进一步的实施方式中，无源部件924和半导体芯片的堆叠可以被电耦合到引线框910的第一部分910_1。
无源部件924和逻辑芯片920的堆叠可以被安装到引线框架910的第一部分910_1上，在其上还安装有另一个半导体芯片，例如功率半导体芯片922。再次，在另一个实施方式中，无源部件924和逻辑芯片920的堆叠可以被安装到引线框架910不具有半导体芯片被附着到例如引线框架910的第四部分910_4的一部分。
在所示的芯片封装件的所有实施方式中，芯片封装件可以被配置作为半桥电路。半桥电路可以具有至少一个无源部件，其包括至少一个无源器件，诸如电感器、电容器、电阻器、或IPD(集成无源器件)，其按照本文的描述所实现。
在图1至图9中所示的所有芯片封装件可以以类似的过程被制造。用于制造具有如图5至图9中所示的半导体芯片和无源部件的堆叠的芯片封装件的一个示例性过程在图10中被图示。
根据图10，用于制造具有无源部件和半导体芯片的堆叠的芯片封装件的方法可以包括，在S1，将第二半导体芯片和无源部件安装在彼此上已提供堆叠器件。在S2，至少一个第一半导体芯片被安装到导电芯片载体上。在S3，电绝缘层被层合在导电芯片载体、至少一个第一半导体芯片和堆叠器件之上。
根据芯片封装件的不同实施方式，可以添加其它过程。例如，在进行S3的层合之前，堆叠器件可以被安装在导电载体上。此外，在S3之前，堆叠器件可以以隔开的关系相对于导电芯片载体被放置。
虽然具体的实施方式已经在本文中图示和描述，但本领域的普通技术人员将理解多种替代和/或等同实施方式可在不脱离本发明的范围下取代所示和所述的具体实施例。本申请旨在涵盖本文所讨论的具体实施例的任何适配或变化。因此，其意图是，本发明只能由权利要求及其等同物所限定。

Claims (25)

1.一种芯片封装件，包括：
导电芯片载体；
至少一个第一半导体芯片，被附着到所述导电芯片载体；
无源部件；以及
绝缘层合结构，嵌入有所述导电芯片载体、所述至少一个第一半导体芯片和所述无源部件。
2.根据权利要求1所述的芯片封装件，其中所述无源部件包括选自由以下项构成的组的至少一个无源器件：电阻器、电容器和电感器。
3.根据权利要求1所述的芯片封装件，其中所述无源部件包括被配置作为集成无源器件的至少一个半导体芯片。
4.根据权利要求1所述的芯片封装件，其中所述无源部件包括层合的壳体。
5.根据权利要求1所述的芯片封装件，其中所述无源部件被安装在所述导电芯片载体上。
6.根据权利要求1所述的芯片封装件，其中所述绝缘层合结构包括第一电绝缘层和第二电绝缘层，并且其中所述无源部件被安装在所述第一电绝缘层上并被嵌入所述第二电绝缘层中。
7.根据权利要求1所述的芯片封装件，其中所述无源部件穿过由所述导电芯片载体所定义的平面。
8.根据权利要求1所述的芯片封装件，其中所述无源部件的接触焊盘被耦合到所述至少一个第一半导体芯片的接触焊盘。
9.根据权利要求1所述的芯片封装件，其中所述无源部件的接触焊盘被配置作为所述芯片封装件的外部接触焊盘。
10.根据权利要求1所述的芯片封装件，其中所述至少一个第一半导体芯片包括功率芯片或逻辑芯片。
11.根据权利要求1所述的芯片封装件，进一步包括第二半导体芯片，其中所述第二半导体芯片和所述无源部件被安装在彼此上。
12.根据权利要求11所述的芯片封装件，其中所述第二半导体芯片包括有源表面和无源表面，并且其中所述第二半导体芯片的所述无源表面被安装到所述无源部件。
13.根据权利要求11所述的芯片封装件，其中所述第二半导体芯片的至少一个电接触焊盘被键合到所述无源部件的接触焊盘。
14.根据权利要求11所述的芯片封装件，其中所述第二半导体芯片包括电接触元件和通孔，所述电接触元件布置在所述第二半导体芯片的无源表面上，所述通孔穿过所述第二半导体芯片并电连接到所述无源表面上的所述电接触元件。
15.根据权利要求11所述的芯片封装件，其中所述第二半导体芯片是逻辑芯片。
16.根据权利要求11所述的芯片封装件，其中所述无源部件穿过由所述导电芯片载体所定义的平面。
17.根据权利要求11所述的芯片封装件，其中所述第二半导体芯片穿过由所述导电芯片载体所定义的平面。
18.根据权利要求11所述的芯片封装件，其中所述无源部件被安装在所述导电芯片载体上，并且所述第二半导体芯片被安装在所述无源部件上。
19.根据权利要求15所述的芯片封装件，其中所述至少一个第一半导体芯片是功率芯片。
20.一种芯片封装件，包括：
无源部件；
金属层，至少部分地覆盖所述无源部件的至少一个主表面；
至少一个第一半导体芯片，被附着到所述金属层；以及
绝缘层合结构，嵌入有所述无源部件和所述至少一个第一半导体芯片。
21.根据权利要求20所述的芯片封装件，其中所述金属层是结构化金属层，所述结构化金属层包括电气再分配结构的导电路径。
22.根据权利要求20所述的芯片封装件，其中所述金属层至少部分地覆盖相对的主表面和所述无源部件的至少一个侧表面。
23.一种制作芯片封装件的方法，包括：
将第二半导体芯片和无源部件安装在彼此上以提供堆叠器件；
将至少一个第一半导体芯片安装到导电芯片载体上；并且
将电绝缘层层合到所述导电芯片载体、所述至少一个第一半导体芯片、以及所述堆叠器件上。
24.根据权利要求23所述的方法，进一步包括：
在层合之前将所述堆叠器件以隔开的关系放置到所述导电芯片载体。
25.根据权利要求23所述的方法，进一步包括：
在层合之前将所述堆叠器件安装在所述导电芯片载体上。
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