WO2018137559A1 - 一种功率模块及其制造方法 - Google Patents

一种功率模块及其制造方法 Download PDF

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Publication number
WO2018137559A1
WO2018137559A1 PCT/CN2018/073367 CN2018073367W WO2018137559A1 WO 2018137559 A1 WO2018137559 A1 WO 2018137559A1 CN 2018073367 W CN2018073367 W CN 2018073367W WO 2018137559 A1 WO2018137559 A1 WO 2018137559A1
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Prior art keywords
conductive layer
power module
insulating
power
semiconductor chip
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PCT/CN2018/073367
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English (en)
French (fr)
Inventor
李慧
杨胜松
廖雯祺
杨钦耀
李艳
张建利
曾秋莲
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比亚迪股份有限公司
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Publication of WO2018137559A1 publication Critical patent/WO2018137559A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Definitions

  • the present application relates to the field of hybrid integrated circuits, and in particular to a power module and a method of fabricating the same.
  • a power semiconductor module is a device that packages a plurality of semiconductor chips together in a certain circuit structure.
  • IGBT Insulated Gate Bipolar Transistor
  • the IGBT chip and the diode chip are integrated on a common substrate, and the power devices of the module are insulated from their mounting surfaces (ie, heat sinks).
  • the power semiconductor module includes a supporting electrical adapter block, which makes the module larger in size and less integrated.
  • the object of the present invention is to provide a power module and a manufacturing method thereof, which are intended to solve the problem that a conventional power semiconductor module needs to be opened and includes a supporting electrical switch block, and the module has a large volume.
  • the invention provides a power module comprising:
  • the insulating medium substrate has an upper surface having a patterned first conductive layer, and the insulating dielectric substrate is provided with a heat conduction path from the lower surface to the first conductive layer;
  • At least one power semiconductor chip the power semiconductor chip being attached to an upper surface of the insulating dielectric substrate to form an electrical connection with the first conductive layer;
  • a patterned second conductive layer is disposed over the insulating layer, and the second conductive layer electrically connects the power semiconductor chip through the conductive material and the first conductive layer.
  • the invention also provides a method for manufacturing a power module, comprising the following steps:
  • an insulating dielectric substrate having a first conductive layer on the upper surface thereof and opening a heat conduction path from the lower surface to the first conductive layer;
  • An insulating layer is disposed on the first insulating dielectric substrate to encapsulate the power semiconductor chip
  • the above power module and its manufacturing method module package do not need to be opened and sealed, which saves production cost; heat conduction path is arranged on the insulating dielectric substrate to improve heat dissipation performance; in addition, the power semiconductor chip is filled with a through hole and filled with conductive on the insulating layer. The material is electrically connected to the upper conductive layer, which reduces the volume of the module and facilitates miniaturization of the module.
  • FIG. 1 is a schematic structural view of a power module according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a power module according to a second embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of an embodiment of a power module overall layout according to the present invention.
  • Figure 4 is a schematic circuit diagram of a half bridge driving circuit
  • FIG. 5 is a schematic structural diagram of a power module according to a third embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of another embodiment of an overall layout of a power module according to the present invention.
  • FIG. 7 is a schematic structural view of a heat dissipation flat plate according to an embodiment of the present invention.
  • FIG. 8 is a flow chart of a method of fabricating a power module in accordance with a preferred embodiment of the present invention.
  • a power module in a preferred embodiment of the present invention includes an insulating dielectric substrate 10 , at least one power semiconductor chip 20 , an insulating layer 40 , and a second conductive layer 50 .
  • the insulating dielectric substrate 10 has oppositely disposed upper and lower surfaces, at least one of which is metal-coated, and the intermediate layer is an insulating dielectric layer 11.
  • the upper surface of the insulating dielectric substrate 10 is covered with a metal to form a patterned first conductive layer 12, and the lower surface may be covered with a metal to form another patterned conductive layer 13, or the heat dissipating fins may be directly disposed.
  • the insulating medium substrate 10 is provided with a heat conduction path from the lower surface to the first conductive layer 12.
  • the insulating dielectric substrate 10 is provided with an opening 14 extending from the lower surface (ie, the conductive layer 13) to the first conductive layer 12, and the opening 14 is filled with an insulating and thermally conductive material to improve the lower surface of the power module. Cooling capacity. It is to be understood that the manner of improving the heat dissipation capability is not limited to the case of using a PCB as the insulating dielectric substrate 10, or the case of any other surface-covered metal dielectric substrate.
  • the power semiconductor chip 20 in this embodiment includes an IGBT and an FRD (Fast Recovery Diode) to constitute a driving circuit.
  • the power semiconductor chip 20 has a polarity pin on both the upper and lower surfaces.
  • the upper surface has two polarity pins, a gate and an emitter, and a collector on the lower surface.
  • the power semiconductor chip 20 is FRD, the upper surface has an anode, the lower surface has a cathode, or vice versa.
  • the power semiconductor chip 20 is attached to the upper surface of the insulating dielectric substrate 10 to form an electrical connection with the first conductive layer 12. Specifically, a circuit pattern is formed on the first conductive layer 12, and when the power semiconductor chip 20 is attached to the circuit pattern by soldering or crimping, the polarity pins of the lower surface are connected to the corresponding circuit pattern forming circuit. Lead out.
  • the insulating layer 40 covers the insulating dielectric substrate 10, and the power semiconductor chip 20 is covered, and the insulating layer 40 is overlaid on the insulating dielectric substrate 10. Specifically, in the product, the lower surface of the insulating layer 40 is provided with a recess for receiving the power semiconductor chip 20.
  • the predetermined position of the insulating layer 40 defines a plurality of through holes 42 extending through the upper and lower surfaces thereof. As shown in FIG. 1 , FIG. 2 and FIG. 5 , the plurality of through holes 42 extend through the insulating layer 40 to reach the power semiconductor chip 20 and the second conductive layer 50 respectively, and the through holes 42 are filled with the power semiconductor chip. 20 and a conductive material electrically connected to the second conductive layer 50. As shown in FIG.
  • the plurality of through holes 42 extend through the second conductive layer 50 and the insulating layer 40 to reach the power semiconductor chip 20 , and the through holes 42 are filled with the power semiconductor chip 20 .
  • the through holes 42 of the same circuit connection path are disposed as much as possible to ensure the overcurrent capability of the circuit and improve the heat dissipation capability of the upper portion of the chip.
  • the insulating layer 40 is formed by pre-pregnant heating and curing, and at the same time, the conductive material in the through hole 42 is simultaneously metalized; wherein the prepreg is mainly composed of a resin and a reinforcing material.
  • the reinforcing material may be a fiberglass cloth, a paper base, a composite material or the like, and the coefficient of thermal expansion of the prepreg is matched with the thermal expansion coefficient of the power semiconductor chip 20 to prevent the device from being affected by the thermal expansion coefficient of the package material. The failure of the stress is too large.
  • matching means that the values of the two coefficients of thermal expansion are as close as possible or equal.
  • the second conductive layer 50 is disposed on the insulating layer 40, specifically, laminated on the insulating layer 40 by lamination.
  • the second conductive layer 50 is electrically connected to the power semiconductor chip 20 via the conductive material.
  • a circuit pattern is formed on the second conductive layer 50, and the polarity pins on the upper surface of the power semiconductor chip 20 are electrically connected to the corresponding circuit patterns to be taken out.
  • the power semiconductor chip 20 is electrically connected to the second conductive layer 50 through the through hole 42 which is formed on the insulating layer 40.
  • the electrical connection is replaced by the electrical adapter block, which reduces the volume of the module and facilitates miniaturization of the module. .
  • the second conductive layer 50 is a conductive metal sheet, and may be made of a copper sheet, an aluminum sheet or other conductive metal material.
  • the second conductive layer 50 may be made of a metal coated with a lower surface of another insulating dielectric substrate.
  • Another insulating dielectric substrate has opposite upper and lower surfaces, at least one of which is coated with a metal to form the second conductive layer 50.
  • the upper surface may be coated with metal to form another conductive layer, and heat dissipating fins may also be provided.
  • power semiconductor chip 20 includes an IGBT 21 and an FRD 22.
  • the power module includes a lead terminal 60 (ie, a power module pin), and one end of the lead terminal 60 is fixedly electrically connected to the first conductive layer 12 or the second conductive layer 50, and cooperates with the conductive material in the through hole 42. Electrically connected to the corresponding polarity pins of the IGBT 21 and the FRD 22, the other end of the extraction terminal 60 projects outward.
  • the lead terminal 60 is for taking the IGBT 21 and the FRD 22 in the form of a preset circuit to take out the terminals of the circuit for connection with an external circuit.
  • the lead terminal 60 may be fixed to the first conductive layer 12 or may be fixed to the second conductive layer 50.
  • the first terminal 12 is fixed to the first conductive layer 12 as an example.
  • the lead terminal 60 includes a power terminal 61 including an emitter power terminal 61A and a collector power terminal 61B, and the first conductive layer 12 including first circuit patterns 121 and the first sides on opposite sides of the power module.
  • the two circuit patterns 122 include a emitter pad 121A and a collector pad 121B which are disposed side by side on the same side of the power module.
  • the polarity pins of the lower surface of the IGBT 21 and the FRD 22 are electrically connected to the collector pad 121B of the first circuit pattern 121, and the collector power terminal 61B is electrically connected to the collector pad 121B; the IGBT 21 and the FRD 22
  • the polarity pins of the upper surface are electrically connected to the emitter pads 121A and the second of the first circuit pattern 121 through the conductive substances in the one-to-one corresponding through holes 42 and the second conductive layer 50, respectively.
  • the circuit pattern 122, the control terminal 62 and the second circuit pattern 122 are soldered, and the emitter power terminal 61A and the emitter pad 121A of the first circuit pattern 121 are soldered. It can be understood that the second circuit pattern 122 is also a pin pad.
  • the second conductive layer 50 includes a third circuit pattern 51 and a fourth circuit pattern 52.
  • the first circuit pattern 121 is connected to the IGBT through the conductive substance in the through hole 42 and the third circuit pattern 51. 21 and the polarity pins on the upper surface of the FRD 22.
  • the second circuit pattern 122 passes through the corresponding conductive substance in the through hole 42 and the fourth circuit pattern 52 to be connected to the polarity pin of the upper surface of the IGBT 21.
  • the IGBT 21 is electrically connected to the emitter pad 121A of the first circuit pattern 121, and is electrically connected to the second circuit pattern 122, and is connected to the collector pad of the first circuit pattern 121.
  • the 121B is electrically connected to the collector.
  • FIG. 3 is a schematic diagram of the overall layout of the power module in the embodiment.
  • the filled area in the figure is substantially graphically patterned for the first conductive layer 12, and the blackened area of the wire frame is substantially graphically patterned for the second conductive layer 50.
  • the IGBT 21 and the FRD 22 are soldered to the corresponding positions of the first conductive layer 12, and the control terminal 62 and the power terminal 61 are also soldered to the corresponding positions of the first conductive layer 12, and the polarity of the chip is electrically connected to the corresponding terminal via the metalized through hole 42.
  • the control terminal 62 and the power terminal 61 are respectively located on both sides of the module, and the low voltage control end is away from the high voltage power end, which reduces the electrical interference of the high voltage end to the low voltage end, and improves the reliability of the control end.
  • each power semiconductor chip 20 constitutes a bridge arm, and the second conductive layer 50 passes through the conductive material and The first conductive layer 12 electrically connects every two pairs of the power semiconductor chips 20 to form a half bridge power module 1.
  • the upper arm includes an upper bridge IGBT 101 and an upper bridge FRD 103, and the lower arm includes a lower bridge IGBT 102 and a lower bridge FRD 104.
  • the power semiconductor chip 20 of the above bridge arm is taken as an example.
  • the upper and lower surfaces of the IGBT chip 101 have polar pins.
  • the upper surface of the IGBT chip 101 has two polarity pins, which are a gate and an emitter, respectively.
  • the lower surface has a collector.
  • the upper bridge FRD chip 103 has an anode on its upper surface and a cathode on its lower surface.
  • the power semiconductor chip 20 of the lower arm is the same.
  • the first conductive layer 12 is fixed to the lead terminal as an example.
  • the lead terminal includes a control terminal 32 and a power terminal 31.
  • the control terminal 32 includes two first control terminals 321 and a second control terminal 322 respectively controlling the upper and lower arms.
  • the power terminal 31 includes a positive power terminal 311 and an AC. Power terminal 312 and negative power terminal 313.
  • the first conductive layer 12 includes a first circuit pattern 121 and a second circuit pattern 122 on opposite sides of the half-bridge power module.
  • the polarity pins of the power semiconductor chip 20 are electrically connected to the first circuit pattern 121 and the second circuit pattern 122 through the conductive materials in the corresponding through holes 42 and the second conductive layer 50, respectively.
  • the control terminal 32 and the second circuit pattern 122 are fixedly electrically connected, and the power terminal 31 and the first circuit pattern 121 are fixedly electrically connected. It can be understood that the first circuit pattern 121 and the second circuit pattern 122 are pin pads.
  • the first circuit pattern 121 includes three lead pads 121A, 121B, and 121C respectively soldered to the positive power terminal 311, the alternating current power terminal 312, and the negative power terminal 313. In this embodiment, three lead pads are used. 121A, 121B, and 121C are placed side by side on the same side of the half-bridge power module.
  • the second circuit pattern 122 includes pin pads 122A and 122B soldered to the first control terminal 321 and the second control terminal 322, respectively, and the pin pads 122A and 122B are disposed in the half bridge power module and the first The other side of the circuit pattern 121 is opposite.
  • the second conductive layer 50 includes a third circuit pattern 51 and a fourth circuit pattern 52, and the third circuit pattern 51 and the fourth circuit pattern 52 are respectively used to match the polarity pins of the power semiconductor chip 20
  • the conductive substances in the holes 42 are electrically connected to the first circuit pattern 121 and the second circuit pattern 122, respectively.
  • FIG. 6 is a schematic diagram of the overall layout of the power module in the embodiment.
  • the filled area in the figure is substantially graphically patterned for the first conductive layer 12, and the blackened area of the wire frame is substantially graphically patterned for the second conductive layer 50.
  • Each device of the half-bridge driving circuit is soldered to a corresponding position of the first conductive layer 12, and the control terminal 32 and the power terminal 31 are also soldered to corresponding positions of the first conductive layer 12, and the chip polarity and the corresponding terminal are formed via the metalized through hole 42. Electrical connections.
  • the control terminal 32 and the power terminal 31 are respectively located on both sides of the module, and the low voltage control end is away from the high voltage power end, which reduces the electrical interference of the high voltage end to the low voltage end, and improves the reliability of the control end.
  • the power module further includes a heat sink 70 disposed on a lower surface of the insulating dielectric substrate 10 and/or the second conductive The upper surface of layer 50.
  • the heat sink 70 can be separately disposed on the lower surface of the power module and in contact with the insulating and heat conductive material in the opening 14 , or can be disposed on the upper and lower surfaces of the power module to achieve double-sided heat dissipation.
  • the lower surface of the insulating dielectric substrate 10 and/or the upper surface of the second conductive layer 50 are connected to the heat sink 70 through the insulating thermally conductive adhesive 80.
  • the heat sink 70 is a heat dissipating fin or a flat heat pipe.
  • Figure 7 is a schematic view of a flat heat pipe.
  • the heat generated by the power semiconductor chip 20 is conducted to the heat pipe evaporation surface 71, and the working fluid 72 in the capillary absorbs heat and vaporizes and fills the vapor chamber.
  • the condensing surface 73 of the flat heat pipe 70 is cooled by circulating cooling liquid.
  • the steam 90 is recondensed into a liquid on the condensation surface 73. Under the action of the capillary suction force of the capillary core 74, the liquid re-flows back to the evaporation surface 71, and the above steps are repeated to achieve circulating heat dissipation.
  • FIGS. 2, 3, 7, and 8 a manufacturing method capable of manufacturing the above power module is further disclosed, including the following steps:
  • Step S110 an insulating dielectric substrate 10 having a first conductive layer 12 on its upper surface is disposed, and a heat conduction path from the lower surface to the first conductive layer is opened.
  • the insulating dielectric substrate 10 is provided to have oppositely disposed upper and lower surfaces, at least one of which is metal-coated.
  • the upper surface of the insulating dielectric substrate 10 is covered with a metal to form a patterned first conductive layer 12, and the lower surface may be covered with a metal to form another conductive layer, or a heat dissipating fin may be disposed; and, the first conductive layer 12
  • the corresponding circuit pattern should be preset.
  • the insulating medium substrate 10 is provided with a heat conduction path from the lower surface to the first conductive layer 12.
  • the insulating dielectric substrate 10 is provided with an opening 14 extending from the lower surface (ie, the conductive layer 13) to the first conductive layer 12, and the opening 14 is filled with an insulating and thermally conductive material to improve the lower surface of the power module. Cooling capacity. It is to be understood that the manner of improving the heat dissipation capability is not limited to the case of using a PCB as the insulating dielectric substrate 10, or the case of any other surface-covered metal dielectric substrate.
  • step S120 the power semiconductor chip 20 is disposed on the first conductive layer 12 to form an electrical connection with the first conductive layer 12.
  • the power semiconductor chip 20 includes an IGBT and/or an FRD to constitute a driving circuit.
  • the upper and lower surfaces of the chip each have a polarity pin, and the power semiconductor chip 20 is attached to the upper surface of the insulating dielectric substrate 10 to form an electrical connection with the first conductive layer 12.
  • the power semiconductor chip 20 is attached to the circuit pattern of the first conductive layer 12 by soldering or crimping, the polarity pins of the lower surface thereof are connected to the corresponding circuit pattern forming circuits to be taken out.
  • step S130 an insulating layer 40 is disposed on the first insulating dielectric substrate 10 to encapsulate the power semiconductor chip 20.
  • the insulating layer 40 is a prepreg, and the prepreg is insulated, and its thermal expansion coefficient needs to be matched with the thermal expansion coefficient of the power semiconductor chip 20 as much as possible.
  • Step S140 providing a second conductive layer 50 on the insulating layer 40, opening a through hole 42 penetrating the insulating layer 40 and the second conductive layer 50, and filling the through hole 42 with a conductive material.
  • the second conductive layer 50 electrically connects the power semiconductor chip 20 through the conductive material in the via hole 42 and the first conductive layer 12.
  • the second conductive layer 50 is preferably a conductive metal sheet.
  • the second conductive layer 50, the prepreg, and the insulating dielectric substrate 10 provided with the power semiconductor chip 20 are sequentially laminated and pressed to fill the prepreg and cover the power semiconductor chip 20.
  • Polarity pins reaching the power semiconductor chip 20 and through holes 42 reaching the first conductive layer 12 are formed on the second conductive layer 50 and the insulating layer 40 by laser technology, and the conductive holes are filled in the through holes 42 to pass through Hole 42 is metallized.
  • the second conductive layer 50 needs to be formed with a circuit pattern before or after lamination, and the polarity pins of the upper surface of the power semiconductor chip 20 are connected to the corresponding circuit pattern forming circuits through the metalized vias 42.
  • the step S120 further includes: further providing a lead-out terminal 60, wherein the one end of the lead-out terminal 60 is fixedly electrically connected to the first conductive layer 12, and the other end is outwardly extended.
  • the lead-out terminal when the patterned second conductive layer 50 can be disposed, the lead-out terminal is provided, and one end of the lead-out terminal 60 is fixedly electrically connected to the second conductive layer 50, and the other end is outwardly extended.
  • the lead-out terminal includes a control terminal 62 and a power terminal 61, and the control terminal 62 and the power terminal 61 are respectively located on opposite sides of the half-bridge power module.
  • the low voltage control terminal is away from the high voltage power terminal, which reduces the electrical interference of the high voltage terminal to the low voltage terminal and improves the reliability of the control terminal.
  • the method further includes the step of heating to cure the prepreg by heating to achieve insulation.
  • the method further includes the step of disposing a heat sink disposed on a lower surface of the insulating dielectric substrate and/or an upper surface of the second conductive layer.
  • the above manufacturing method is that the power module is manufactured without encapsulation, and the production cost is saved; the chip is electrically connected through the metalized through hole 42 to reduce the volume of the module and facilitate the miniaturization of the module.
  • the power module is manufactured by soldering the power semiconductor chip 20, the control terminal 62, and the power terminal 61 to the first conductive layer 12 patterned on the insulating dielectric substrate 10, and the prepreg (insulating layer) of a corresponding thickness.
  • the second conductive layer 50 is laminated with the chip-attached insulating dielectric substrate 10, the flow of the prepreg 40 is filled and covers the chip, wherein the prepreg 40 is insulated, and the thermal expansion coefficient thereof should be as close as possible to the thermal expansion coefficient of the power device. match.
  • the second conductive layer 50 of the laminated module is patterned, and the via hole 42 is formed by laser technology and metallized, so that the chip polarity pin and the corresponding lead terminal 60 are electrically connected.
  • the via hole 42 is disposed as much as possible in order to ensure the reliability of the bonding between the metallized via 42 and the chip, so as to ensure the overcurrent capability of the circuit and improve the heat dissipation capability of the upper portion of the chip.
  • this step can be performed after the through hole 42 is formed after lamination. Simultaneously, it can also be performed while the insulating substrate 10 is being prepared.
  • the lower surface of the module (insulating dielectric substrate 10) is dissipated by the heat sink 70, and the upper surface of the module (second conductive layer 50) is coated with an insulating thermal conductive adhesive 80, and then connected to the other heat sink 70 to dissipate heat, thereby achieving double-sided heat dissipation and improving Cooling capacity.
  • the two heat sinks 70 do not necessarily need to be disposed at the same time, and in the case where the heat dissipation condition can be satisfied, the heat sink 70 on the lower surface alone may constitute a single-sided heat dissipation.

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Abstract

一种功率模块及其制造方法，功率模块包括：绝缘介质基板（10），其上表面具有第一导电层（12），且开设有从下表面到达第一导电层的导热路径；至少一个功率半导体芯片（20），芯片贴设于绝缘介质基板的上表面上；绝缘层（40），覆盖于绝缘介质基板上，将芯片包覆在内，绝缘层开设有位于芯片上方的通孔（42），且通孔内填充有导电物质；第二导电层（50），设置于绝缘层之上，第二导电层通过导电物质与芯片电气连接。封装无需开塑封模，节省了生产成本；另外，功率半导体芯片通过在绝缘层上开设通孔并填充导电物质与上层的导电层实现电气连接，减小了模块的体积，有利于模块小型化。

Description

一种功率模块及其制造方法
本申请要求于2017年01月24日提交中国专利局、申请号为201710063328.1、申请名称为“一种功率模块及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及混合集成电路领域，特别是涉及一种功率模块及其制造方法。
背景技术
功率半导体模块是将多只半导体芯片按一定的电路结构封装在一起的器件。在一个IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)模块中，IGBT芯片及二极管芯片被集成到一块共同的底板上，且模块的功率器件与其安装表面(即散热板)相互绝缘。
传统的功率半导体模块塑封成型需要开模，成本较高；另外，功率半导体模块包含起支撑作用的电气转接块，使得模块体积较大，集成度小。
发明内容
本发明目的在于提供一种功率模块及其制造方法，旨在解决传统的功率半导体模块需要开模，且包含起支撑作用的电气转接块，模块体积较大的问题。
本发明提供了一种功率模块，包括：
绝缘介质基板，其上表面具有图形化的第一导电层，所述绝缘介质基板开设有从下表面到达所述第一导电层的导热路径；
至少一个功率半导体芯片，所述功率半导体芯片贴设于所述绝缘介质基板的上表面上，与所述第一导电层形成电气连接；
绝缘层，覆盖于所述绝缘介质基板上，将所述功率半导体芯片包覆在内，所述绝缘层开设有贯穿其上下表面的第一通孔，且所述通孔内填充有与所述功率半导体芯片电气连接的导电物质；
图形化的第二导电层，设置于所述绝缘层之上，所述第二导电层通过所述导电物质和所述第一导电层将所述功率半导体芯片电路连接。
本发明还提供了一种功率模块的制造方法，包括以下步骤：
设置一上表面具有第一导电层的绝缘介质基板，且开设有从下表面到达所述第一导电层的导热路径；
将至少一个功率半导体芯片设于所述第一导电层上，与所述第一导电层形成电气连接；
在所述第一绝缘介质基板上设置一绝缘层，将所述功率半导体芯片包覆在内；
在所述绝缘层上设置第二导电层，开设穿透所述绝缘层和第二导电层的通孔，并在所述通孔内填充导电物质，使所述第二导电层通过所述导电物质和所述第一导电层将所述功率半导体芯片电路连接。
上述的功率模块及其制造方法模块封装无需开塑封模，节省了生产成本；在绝缘介质基板上设置导热路径，提高了散热性能；另外，功率半导体芯片通过在绝缘层上开设通孔并填充导电物质与上层的导电层实现电气连接，减小了模块的体积，有利于模块小型化。
附图说明
图1为本发明第一实施例中功率模块的结构示意图；
图2为本发明第二实施例中功率模块的结构示意图；
图3为本发明功率模块整体布局一种实施例的结构示意图；
图4半桥驱动电路的电路原理图；
图5为本发明第三实施例中功率模块的结构示意图；
图6为本发明功率模块整体布局另一种实施例的结构示意图；
图7为本发明实施例中散热平板的结构示意图；
图8为本发明较佳实施例中功率模块的制造方法的流程图。
具体实施方式
为了使本发明要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
请参阅图1，本发明较佳实施例中的功率模块包括绝缘介质基板10、至少一个功率半导体芯片20、绝缘层40及第二导电层50。
绝缘介质基板10具有相对设置的上下表面，其中至少一个表面覆金属，中间层为绝缘介质层11。本实施例中，绝缘介质基板10的上表面覆金属形成图形化的第一导电层12，而下表面可以覆金属形成另一个图形化的导电层13，也可以直接设置散热翅片。
在绝缘介质基板10使用PCB(Printed Circuit Board，印刷电路板)时，PCB的绝缘介质层11(树脂层)的导热能力太差。因此，本实施例中，在绝缘介质基板10开设有从下表面到达所述第一导电层12的导热路径。绝缘介质基板10开设有从下表面(即导电层13)到达或穿透所述第一导电层12的开孔14，且所述开孔14内填充有绝缘导热材料以提高功率模块下表面的散热能力。可以理解的是，提高散热能力的方式不限于使用在使用PCB板作为绝缘介质基板10的情况，或为其他任何表面覆金属绝缘介质基板的情况。
本实施例中的功率半导体芯片20包括IGBT和FRD(Fast Recovery Diode，快速恢复二极管)以构成驱动电路。功率半导体芯片20其上下表面均具有极性引脚，本实施例中，功率半导体芯片20为IGBT时，上表面具有两个极性引脚，分别是门极和发射极，下表面具有集电极。功率半导体芯片20为FRD时，上表面具有阳极，下表面具有阴极，或反之。
功率半导体芯片20贴设于所述绝缘介质基板10的上表面上，与所述第一导电层12形成电气连接。具体地，在第一导电层12上形成电路图案，功率半导体芯片20通过焊接或压接的方式贴设于电路图案上时，其下表面的极性引脚与对应的电路图案形成电路连接以引出。
绝缘层40覆盖于所述绝缘介质基板10上，将所述功率半导体芯片20包覆在内，绝缘层40通过层压的方式覆盖在绝缘介质基板10上。具体地，在产 品中，绝缘层40的下表面开设有用于收容功率半导体芯片20的凹槽。所述绝缘层40的预设位置开设有多个贯穿其上下表面的通孔42。如图1、图2和图5所示，该多个通孔42贯穿绝缘层40分别到达功率半导体芯片20和第二导电层50，且所述通孔42内填充有实现所述功率半导体芯片20和第二导电层50电气连接的导电物质。如图3和图6所示，该多个通孔42贯穿所述第二导电层50和绝缘层40分别到达功率半导体芯片20，且所述通孔42内填充有实现所述功率半导体芯片20和第二导电层50电气连接的导电物质。优选地，在确保金属化通孔42与芯片之间结合的可靠性前提下，同一电路连接路径的通孔42尽可能地多设置，以便保证电路的过流能力及提高芯片上部散热能力。
在制作过程中，本实施例中，绝缘层40由半固化片(Pre-pregnant)加热并固化形成，加热时同时将通孔42内的导电物质金属化；其中，半固化片主要由树脂和增强材料组成，增强材料可以为玻纤布、纸基和复合材料等，所述半固化片的热膨胀系数与所述功率半导体芯片20的热膨胀系数匹配，避免功率器件由于与封装材料热膨胀系数不匹配而导致的器件所受的应力过大出现的失效问题。其中，匹配是指两个热膨胀系数的数值尽可能接近或相等。
第二导电层50设置于所述绝缘层40之上，具体是通过层压的方式叠设在绝缘层40上。第二导电层50通过该导电物质与所述功率半导体芯片20电路连接。
本实施例中，第二导电层50上形成电路图案，功率半导体芯片20上表面的极性引脚与对应的电路图案形成电气连接以引出。如此，功率半导体芯片20通过开设在绝缘层40上金属化的通孔42与第二导电层50实现电气连接，取代电气转接块实现电气连接，减小了模块的体积，有利于模块小型化。
本实施例中，第二导电层50为导电金属片，具体可以是铜片、铝片或者其他导电金属材料制作而成。在其他实施方式中，第二导电层50可以由另一绝缘介质基板的下表面覆金属构成。另一绝缘介质基板具有相对设置的上下表面，其中至少一个表面覆金属构成第二导电层50。而上表面可以覆金属形成另一个导电层，也可以设置散热翅片。
请参阅图2和图3，在一个实施例中，功率半导体芯片20包括一个IGBT 21和一个FRD 22。功率模块包括引出端子60(即功率模块引脚)，引出端子 60的一端与所述第一导电层12或所述第二导电层50固定电气连接，并配合所述通孔42内的导电物质电气连接到所述IGBT 21和FRD 22相应的极性引脚上，所述引出端子60的另一端向外伸出。引出端子60用于将IGBT 21和FRD 22以预设电路的形式将电路的端子引出以用作与外部电路连接。引出端子60可以固定在第一导电层12上，也可以固定在第二导电层50上。
本实施例中，以引出端子60固定在第一导电层12为例说明。引出端子60包括功率端子61和控制端子62，功率端子61包括发射极功率端子61A和集电极功率端子61B，所述第一导电层12包括位于功率模块相对两侧的第一电路图案121和第二电路图案122，第一电路图案121包括并排设置在功率模块的提同一侧的发射极焊盘121A和集电极焊盘121B。所述IGBT 21和FRD 22下表面的极性引脚与第一电路图案121的集电极焊盘121B电气连接，集电极功率端子61B与集电极焊盘121B电气连接；所述IGBT 21和FRD 22上表面的极性引脚分别通过一一对应的所述通孔42内的导电物质以及所述第二导电层50分别电气连接到所述第一电路图案121的发射极焊盘121A和第二电路图案122，所述控制端子62和第二电路图案122焊接，所述发射极功率端子61A和所述第一电路图案121的发射极焊盘121A焊接。可以理解的是第二电路图案122也引脚焊盘。
更具体地，第二导电层50包括第三电路图案51和第四电路图案52，第一电路图案121通过一一对应的所述通孔42内的导电物质及第三电路图案51连接到IGBT 21和FRD 22上表面的极性引脚。第二电路图案122通过对应的所述通孔42内的导电物质和第四电路图案52以连接到IGBT 21上表面的极性引脚。本实施例中，IGBT 21与第一电路图案121的发射极焊盘121A电气连接的是发射极，与第二电路图案122电气连接的是门极，与第一电路图案121的集电极焊盘121B电气连接的是集电极。
图3是本实施例中功率模块整体布局图示意图。图中填充区域为第一导电层12大致所示图形化，线框加黑区域为第二导电层50大致所示图形化。IGBT 21和FRD 22焊接在第一导电层12对应位置，控制端子62及功率端子61也焊接在第一导电层12对应位置，经由金属化的通孔42使得芯片极性与对应端子形成电气连接。控制端子62及功率端子61分别位于模块两侧，低压控制端 远离高压功率端，减小了高压端对低压端的电气干扰，提高了控制端的可靠性。
请参阅图4至图6，在另一个实施例中，功率模块中至少有一对功率半导体芯片20，每个功率半导体芯片20构成一个桥臂，所述第二导电层50通过所述导电物质和所述第一导电层12将每两对所述功率半导体芯片20电路连接构成半桥功率模块1。上桥臂包括上桥IGBT 101和上桥FRD 103，下桥臂包括下桥IGBT 102和下桥FRD 104。以上桥臂的功率半导体芯片20为例，IGBT芯片101其上下表面均具有极性引脚，本实施例中，IGBT芯片101上表面具有两个极性引脚，分别是门极和发射极，下表面具有集电极。上桥FRD芯片103上表面具有阳极，下表面具有阴极。下桥臂的功率半导体芯片20同之。
本实施例中，以引出端子固定在第一导电层12为例说明。引出端子包括控制端子32和功率端子31，本实施例中，控制端子32包括两个分别控制上下桥臂的第一控制端子321和第二控制端子322，功率端子31包括正极功率端子311、交流功率端子312及负极功率端子313。所述第一导电层12包括位于半桥功率模块相对两侧的第一电路图案121和第二电路图案122。功率半导体芯片20的极性引脚分别通过对应的所述通孔42内的导电物质以及所述第二导电层50分别电气连接到所述第一电路图案121和第二电路图案122，所述控制端子32和第二电路图案122固定电气连接，功率端子31和所述第一电路图案121固定电气连接。可以理解的是第一电路图案121和第二电路图案122为引脚焊盘。
具体地，第一电路图案121包括三个分别与正极功率端子311、交流功率端子312及负极功率端子313焊接的引脚焊盘121A、121B和121C，本实施例中，三个引脚焊盘121A、121B和121C并排设置在半桥功率模块的同一侧。请参阅图4，第二电路图案122包括分别与第一控制端子321和第二控制端子322焊接的引脚焊盘122A和122B，引脚焊盘122A和122B同设置在半桥功率模块与第一电路图案121相对的另一侧。
更具体地，第二导电层50包括第三电路图案51和第四电路图案52，第三电路图案51和第四电路图案52分别用于将功率半导体芯片20的极性引脚配合对应的通孔42内的导电物质分别电路连接到第一电路图案121和第二电路图案122。
图6是本实施例中功率模块整体布局图示意图。图中填充区域为第一导电层12大致所示图形化，线框加黑区域为第二导电层50大致所示图形化。半桥驱动电路的各个器件焊接在第一导电层12对应位置，控制端子32及功率端子31也焊接在第一导电层12对应位置，经由金属化的通孔42使得芯片极性与对应端子形成电气连接。控制端子32及功率端子31分别位于模块两侧，低压控制端远离高压功率端，减小了高压端对低压端的电气干扰，提高了控制端的可靠性。
另外，在优选的实施例中，请参阅图2、5和7，功率模块还包括散热器70，所述散热器70设置于所述绝缘介质基板10的下表面和/或所述第二导电层50的上表面。散热器70可单独设置在功率模块下表面与开孔14内的绝缘导热材料接触，也可设置在功率模块上下表面实现双面散热。具体地，绝缘介质基板10的下表面和/或所述第二导电层50的上表面通过绝缘导热胶80后与散热器70连接。散热器70为散热翅片或平板热管。图7是平板热管示意图。功率半导体芯片20产生的热传导到热管蒸发面71，毛细管中工作液72吸收热量汽化并充满蒸汽腔。平板热管70的冷凝面73采用循环冷却液进行冷却。蒸汽90在冷凝面73重新凝结成液体，在毛细芯74的毛吸力作用下，液体重新流回蒸发面71，重复上述步骤实现循环散热。
此外，请结合图2、3、7和8，还公开了一种可制造上述功率模块的制造方法，包括以下步骤：
步骤S110，设置一上表面具有第一导电层12的绝缘介质基板10，且开设有从下表面到达所述第一导电层的导热路径。
在该步骤中，所提供的绝缘介质基板10应具有相对设置的上下表面，其中至少一个表面覆金属。本实施例中，绝缘介质基板10的上表面覆金属形成图形化的第一导电层12，而下表面可以覆金属形成另一个导电层，也可以设置散热翅片；并且，第一导电层12上应预设相应的电路图案。
在绝缘介质基板10使用PCB时，PCB的树脂层的导热能力太差。因此，本实施例中，在绝缘介质基板10开设有从下表面到达所述第一导电层12的导热路径。绝缘介质基板10上开设有从下表面(即导电层13)到达或穿透所述第一导电层12的开孔14，且所述开孔14内填充有绝缘导热材料以提高功率 模块下表面的散热能力。可以理解的是，提高散热能力的方式不限于使用在使用PCB板作为绝缘介质基板10的情况，或为其他任何表面覆金属绝缘介质基板的情况。
步骤S120，将功率半导体芯片20设于所述第一导电层12上，与所述第一导电层12形成电气连接。
具体地，功率半导体芯片20包括IGBT和\或FRD构成驱动电路。芯片上下表面均具有极性引脚，功率半导体芯片20贴设于所述绝缘介质基板10的上表面上，与所述第一导电层12形成电气连接。具体地，功率半导体芯片20通过焊接或压接的方式贴设于第一导电层12的电路图案上时，其下表面的极性引脚与对应的电路图案形成电路连接以引出。
步骤S130，在所述第一绝缘介质基板10上设置一绝缘层40，将所述功率半导体芯片20包覆在内。
本实施例中，所述绝缘层40为半固化片，半固化片是绝缘的，且其热膨胀系数需尽量与功率半导体芯片20的热膨胀系数匹配。
步骤S140，在所述绝缘层40上设置第二导电层50，开设穿透所述绝缘层40和第二导电层50的通孔42，并在所述通孔42内填充导电物质，使所述第二导电层50通过所述通孔42内的导电物质和所述第一导电层12将功率半导体芯片20电路连接。
具体地，第二导电层50优选为导电金属片。将所述第二导电层50、半固化片和设有所述功率半导体芯片20的绝缘介质基板10依次层叠压合，使半固化片流胶填充并覆盖功率半导体芯片20。在第二导电层50和绝缘层40上采用激光技术制作到达功率半导体芯片20的极性引脚，以及到达第一导电层12的通孔42，在所述通孔42内填充导电物质使通孔42金属化。第二导电层50在层压之前或之后需制作电路图案，功率半导体芯片20上表面的极性引脚通过金属化的通孔42与对应的电路图案形成电路连接。
更具体的实施例中，在步骤S120中还包括：还设置引出端子60，使所述引出端子60的一端与所述第一导电层12固定电气连接，另一端向外伸出的步骤。在其他实施方式中，可以设置图形化的第二导电层50时，设置引出端子， 将使所述引出端子60的一端与所述第二导电层50固定电气连接，另一端向外伸出。引出端子包括控制端子62和功率端子61，所述控制端子62和功率端子61分别位于所述半桥功率模块相对两侧。低压控制端远离高压功率端，减小了高压端对低压端的电气干扰，提高了控制端的可靠性。
进一步地，所述方法还包括加热的步骤，通过加热使所述半固化片固化实现绝缘。
进一步地，所述方法还包括设置于所述绝缘介质基板的下表面和/或所述第二导电层的上表面的散热器的步骤。
可见，上述的制作方法均在制作功率模块是封装无需开塑封模，节省了生产成本；芯片通过金属化的通孔42实现电气连接，减小了模块的体积，有利于模块小型化。
更具体地，功率模块的制造方法为：将功率半导体芯片20、控制端子62和功率端子61均焊接在绝缘介质基板10图形化的第一导电层12上，将相应厚度的半固化片(绝缘层)40、第二导电层50与贴有芯片的绝缘介质基板10进行层压，使半固化片40的流胶填充并覆盖芯片，其中，半固化片40是绝缘的，且其热膨胀系数需尽量与功率器件热膨胀系数匹配。首先对层压后模块的第二导电层50图形化，再采用激光技术制作通孔42并金属化，使得芯片极性引脚与对应引出端子60形成电气连接。在确保金属化通孔42与芯片之间结合的可靠性前提下通孔42尽可能地多设置，以便保证电路的过流能力及提高芯片上部散热能力。其中，通过对绝缘介质基板10的下表面和绝缘介质层11采用激光技术钻开孔14并填充绝缘导热材料以提高芯片下表面的散热能力，此步骤可以在层压之后制作通孔42的时候同时进行，也可以在准备绝缘基板10时候进行。模块(绝缘介质基板10)下表面由散热器70进行散热，模块(第二导电层50)上表面涂上绝缘导热胶80后与另一个散热器70连接散热，以此实现双面散热，提高散热能力。两个散热器70不一定需要同时设置，在能够满足散热条件情况下，也可仅由下表面的散热器70单独构成单面散热。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制。虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述 揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (15)

  1. 一种功率模块，其特征在于，包括：
    绝缘介质基板，其上表面具有图形化的第一导电层，所述绝缘介质基板开设有从下表面到达所述第一导电层的导热路径；
    至少一个功率半导体芯片，所述功率半导体芯片贴设于所述绝缘介质基板的上表面上，与所述第一导电层形成电气连接；
    绝缘层，覆盖于所述绝缘介质基板上，将所述功率半导体芯片包覆在内，所述绝缘层开设有贯穿其上下表面的通孔，且所述通孔内填充有与所述功率半导体芯片电气连接的导电物质；
    图形化的第二导电层，设置于所述绝缘层之上，所述第二导电层通过所述导电物质和所述第一导电层将所述功率半导体芯片电路连接。
  2. 如权利要求1所述的功率模块，其特征在于，所述绝缘介质基板开设有从下表面到达或穿透所述第一导电层的开孔，且所述开孔内填充有绝缘导热材料。
  3. 如权利要求1或2所述的功率模块，其特征在于，包括至少一对所述功率半导体芯片，所述第二导电层通过所述导电物质和所述第一导电层将每两对所述功率半导体芯片电路连接构成半桥功率模块。
  4. 如权利要求1或3所述的功率模块，其特征在于，还包括引出端子，所述引出端子的一端与所述第一导电层或所述第二导电层固定电气连接，并配合所述通孔内的导电物质电气连接到所述功率半导体芯片相应的极性引脚上，所述引出端子的另一端向外伸出。
  5. 如权利要求4所述的功率模块，其特征在于，所述引出端子包括控制端子和功率端子，所述控制端子和功率端子分别位于所述功率模块相对两侧。
  6. 如权利要求1或2所述的功率模块，其特征在于，还包括散热器，所述散热器设置于所述绝缘介质基板的下表面和/或所述第二导电层的上表面。
  7. 如权利要求1-6任意一项所述的功率模块，其特征在于，所述绝缘介质基板为PCB板。
  8. 如权利要求1-7任意一项所述的功率模块，其特征在于，所述绝缘层为半固化片。
  9. 如权利要求1-8任意一项所述的功率模块，其特征在于，所述通孔还贯穿所述第二导电层。
  10. 一种功率模块的制造方法，其特征在于，包括以下步骤：
    设置一上表面具有第一导电层的绝缘介质基板，且开设有从下表面到达所述第一导电层的导热路径；
    将至少一个功率半导体芯片设于所述第一导电层上，与所述第一导电层形成电气连接；
    在所述第一绝缘介质基板上设置一绝缘层，将所述功率半导体芯片包覆在内；
    在所述绝缘层上设置第二导电层，开设穿透所述绝缘层和第二导电层的通孔，并在所述通孔内填充导电物质，使所述第二导电层通过所述导电物质和所述第一导电层将所述功率半导体芯片电路连接。
  11. 如权利要求10所述的功率模块的制造方法，其特征在于，所述开设有从下表面到达所述第一导电层的导热路径的步骤包括：
    于所述绝缘介质基板上开设有从下表面到达或穿透所述第一导电层的开孔；
    于所述开孔内填充有绝缘导热材料。
  12. 如权利要求10或11所述的功率模块的制造方法，其特征在于，在将至少一个功率半导体芯片设于所述第一导电层上时，还设置引出端子，使所述引出端子的一端与所述第一导电层固定电气连接，另一端向外伸出；或
    设置第二导电层时，设置引出端子，使所述引出端子的一端与所述第二导电层固定电气连接，另一端向外伸出。
  13. 如权利要求12所述的半桥功率模块的制造方法，其特征在于，所述引出端子包括控制端子和功率端子，所述控制端子和功率端子分别位于所述功率模块相对两侧。
  14. 如权利要求10-13任意一项所述的功率模块的制造方法，其特征在于，所述方法还包括加热的步骤；其中，所述绝缘层为半固化片，通过加热使所述半固化片固化实现绝缘。
  15. 如权利要求10-14任意一项所述的功率模块的制造方法，其特征在于， 还包括设置于所述绝缘介质基板的下表面和/或所述第二导电层的上表面的散热器。
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