CN101231709A - 记忆卡的结构与其方法 - Google Patents

记忆卡的结构与其方法 Download PDF

Info

Publication number
CN101231709A
CN101231709A CNA2008100007931A CN200810000793A CN101231709A CN 101231709 A CN101231709 A CN 101231709A CN A2008100007931 A CNA2008100007931 A CN A2008100007931A CN 200810000793 A CN200810000793 A CN 200810000793A CN 101231709 A CN101231709 A CN 101231709A
Authority
CN
China
Prior art keywords
dielectric layer
crystal grain
layer
rerouting
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2008100007931A
Other languages
English (en)
Inventor
杨文焜
余俊辉
林志伟
周昭男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yupei Science & Technology Co Ltd
Original Assignee
Yupei Science & Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yupei Science & Technology Co Ltd filed Critical Yupei Science & Technology Co Ltd
Publication of CN101231709A publication Critical patent/CN101231709A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

本发明系提供一种记忆卡结构，包含一上表面具有晶粒容纳凹槽之基底、一通孔结构及形成于基底之布线。一第一晶粒配置于晶粒容纳凹槽。一第一介电层形成于第一晶粒与基底之上。一第一重布层(re－distribution layer，RDL)形成于第一介电层上，其中第一重布层系耦合至第一晶粒与布线。一第二介电层形成于第一重布层上。一第二晶粒配置于第二介电层之上。一第三介电层形成于第二介电层与第二晶粒上。一第二重布层形成于第三介电层上，其中第二重布层系耦合至第二晶粒与第一重布层。一第四介电层形成于第二重布层上。一第三晶粒形成于第四介电层上并耦合至第二重布层。一第五介电层形成于第三晶粒周围，并由一塑胶盖罩住第一、第二及第三晶粒。

Description

记忆卡的结构与其方法
技术领域
本发明系有关一种记忆卡结构，特别是关于具有晶粒容纳凹槽以配置晶粒之基底。
背景技术
在半导体装置领域中，装置之密度持续增加，且体积逐渐减小。高密度装置之封装或交互连接技术的需求亦日益增加，以符合上述情况。一般而言，在覆晶接合方法(flip-chip attachmentmethod)中，焊锡凸块数组系形成于晶粒表面上。焊锡凸块之形成系利用焊锡合成材料通过锡球罩幕(solder mask)，以产生所需焊锡凸块之图案。晶粒封装之功能包含电源分配(powerdistribution)、讯号分配(signal distribution)、散热(heatdissipation)、保护及支撑等。由于半导体结构趋向复杂化，而一般传统技术，例如导线架封装(lead frame package)、软性封装(flex package)、刚性封装(rigid package)技术，已无法达成于晶粒上产生具有高密度组件之小型晶粒。
与半导体同时发展的还有一种名为电子电路卡(electroniccircuit card)的产品。记忆卡系应用于个人电脑、手机、个人数位助理(PDA)、数码相机、数码摄像机、随身听以及其它装置上以储存数据。随着电子卡规格的发展也产生了许多不同种类的记忆卡。记忆卡较窄的一边为一电子接头。
记忆卡系一可坎入主装置的延伸卡。典型的记忆卡可供高速读取以及广大的内存容量。近年来，记忆卡的容量已发展到以GB(Giga-Bytes)为单位。目前有众多不同的记忆卡可供选择。快闪记忆卡可藉由电子处理来清除。因此，闪存可以替代硬盘应用于携带型电脑中。快闪记忆卡被广泛应用于各种装置中以储存与复制数据。
图1提供了若干比较常见之记忆卡图式。先前技术之缺点在于因为受到打线接合(wire bonding)外形的限制，令其难以提供较薄的封装。  采用打线接合堆栈(W/B stacking)时，由于晶粒堆栈中间需要空间加上需要模具来保护芯片与电线，因此在提供较薄的封装上有相当程度的困难。相关制程包含了模具灌模(胶)法(molding injection)或液体印刷法(liquid printing)。其引发了关于良率的问题。Micro SD卡所需要的整体厚度为0.7mm+/-0.1mm。
因此，目前所需要的系具有可解决上述封装厚度问题并拥有简易制程之高阶记忆卡结构。
发明内容
本发明之一目的系在于提供一种超薄及小尺寸(small formfactor)的记忆卡。
本发明之另一目的系在于提供一种拥有简易制程以及低成本方案的可靠产品。
记忆卡的结构包含了一上表面具有晶粒容纳凹槽之基底、一通孔结构及形成于基底之布线。一第一晶粒配置于晶粒容纳凹槽。一第一介电层形成于第一晶粒与基底之上。一第一重布层(re-distribution layer，RDL)形成于第一介电层上，其中第一重布层系耦合至第一晶粒与布线。一第二介电层形成于第一重布层上。一第二晶粒配置于第二介电层之上。一第三介电层形成于第二介电层与第二晶粒上。一第二重布层形成于第三介电层上，其中第二重布层系耦合至第二晶粒与第一重布层。一第四介电层形成于第二重布层上。一第三晶粒形成于第四介电层之上并耦合至第二重布层。一第五介电层形成于第三晶粒周围(当第三晶粒系采用覆晶形式(flip chip type)时，此步骤可略过)，并由一塑胶盖罩住第一、第二及第三晶粒。
另外包含了被动组件(passive device)形成于该第四介电层上。在一实施例中，  第三晶粒系由覆晶配置法(flip chipconfiguration)所形成的。在另一实施例中，第三晶粒系连结于该第四介电层之上，而第三重布层系形成于第五介电层上并耦合至该第二重布层。
第一、第二、第三、第四及第五介电层其中之一包含一弹性介电层(elastic dielectric layer)。第一、第二、第三、第四及第五介电层其中之一包含一以硅介电(silicone dielectric)为主的材质、苯环丁烯(benzo-cyclo-butene，BCB)或聚酰亚胺(polyimide，PI)。以硅介电为主的材质包含了硅氧烷聚合物(SINR)、硅氧化物、硅氮化物或其合成物。第一、第二、第三、第四及第五介电层其中之一包含一感光层(photosensitivelayer)。由第一及第二晶粒扩散出(fan out)第一及第二重布层。
附图说明
图1系为根据先前技术之记忆卡结构之剖面图。
图2系为根据本发明之基底结构之剖面图。
图3系为根据本发明之结构之剖面图。
图4系为根据本发明之结构之剖面图。
图5(a)-(i)系为根据本发明之记忆卡制程之流程图。
图6系为根据本发明之结构之剖面图。
图7系为根据本发明之结构之剖面图。
图8系为根据本发明之结构之剖面图。
图中：
2基底            28黏着性材质
4晶粒容纳凹槽    30第三介电层
6布线            32第二重布层
8通孔            34第四介电层
10第一晶粒       36输入/输出垫
12黏着性材质     38第三晶粒
14输入/输出垫    40被动组件
16接触垫         42顶层
18第一介电层     44通孔
20第一重布层     48第五介电层
22填充材质       50第三重布层
24第二介电层     54预形成之塑胶盖
26第二晶粒       56端点垫
具体实施方式
本发明将配合其较佳实施例与后附之图式详述于下。应可理解，本发明中之较佳实施例系仅用以说明，而非用以限定本发明。此外，除文中之较佳实施例外，本发明亦可广泛应用于其它实施例，并且本发明并不限定于任何实施例，而应视后附之申请专利范围而定。
本发明揭露一种晶圆级封装(wafer level package，WLP)之结构，其基底具有预定凹槽，并有通孔形成于基底。感光层系涂布于晶粒及预形成基底之上。较佳的情况下，感光层之材料系由弹性材料所形成。
图2系为预形成之基底，图3及图4系为记忆卡之结构，而图5则系根据本发明所实施的一例之流程。如图2、图3以及图5(a)所示，此结构包含具有晶粒容纳凹槽4之基底2得以配置晶粒。复数的通孔8以及布线6设计于基底2之中或之上。通孔8系形成于基底2之上表面至基底2之下表面。一导电材质将填入于通孔8之中以利电子连接。一端点垫56形成于基底2之下表面。
一第一晶粒10系配置于基底2的晶粒容纳凹槽4之中并藉由黏着性材质12加以固定。如熟知该项技术者所熟知，接触垫(连接垫(bonding pads))14系形成于晶粒10之上，而接触垫16则形成于基底2之上。填充材质22系装填于晶粒及晶粒容纳凹槽4侧壁间之空隙，此填充材质可与上述之黏着性材质12相同。一感光层(photosensitive layer)或介电层18系形成于晶粒之上并填入晶粒10以及晶粒容纳凹槽4墙壁间之空隙(以保持相同之表面层)。于微影制程(lithography process)或曝光制程(exposure procedure)中，复数开口将形成于介电层18之内。复数开口系分别经由通孔8对准(aligned)接触，以及对准接触或输入/输出垫(I/O pad)14。重布层(re-distribution layer，RDL)20，亦可称为金属布线，系藉由移除部份形成于介电层18上之金属层而形成于介电层18之上，其中重布层20系藉由输入/输出垫14以与晶粒10保持电性连接(electricallyconnected)。部份重布层之材质将重新填入介电层18之开口，因此藉由通孔8上的金属以及垫16上的金属而形成接触。如图3以及图5(c)所示，另一介电层24系覆盖于重布层20之上。
请参照图3以及图5(d)-(e)，介电层18系形成于晶粒10以及基底之顶上并填满晶粒2周遭的空间。一第二晶粒26系藉由黏着性材质28而装配于第二介电层24之上。同样地，第三介电层或感光层30系形成于第二晶粒26之上并填入邻接晶粒26之空间。于微影制程或曝光制程中，复数开口将形成于介电层30之内。复数开口系分别经由第二晶粒26之输入/输出垫36而对准接触。一第二重布层32，系藉由移除部份形成于介电层上之金属层而形成于第三介电层30之上，其中重布层32系藉由输入/输出垫36以与第二晶粒26保持电性连接。一第四介电层34覆盖于第二重布层32之上。复数开口形成于第四介电层34中。
请参照图3以及图5(f)-(g)，一第三晶粒38系装配于第四介电层34之上并藉由第四介电层34之开口以及第三晶粒38之凸块而耦合至第二重布层32。较佳的情况下，第三晶粒38系藉由覆晶配置法(flip chip configuration)而耦合。另外，至少一被动组件(passive device)40可藉由表面黏着技术(surfacemount technology，SMT)耦合至第二重布层32。最后，一顶层42系被形成来覆盖住被动组件40并至少包围住第三晶粒38(在本发明中，此过程系可略过)。在一实施例中，晶粒38之上表面得为无遮蔽，以藉此减少厚度并增强散热(thermal dissipation)效果。第二重布层32系藉由通孔结构44与第一重布层20相连。在另一情况下，如图6及图5(h)-(i)所示，第三晶粒38并非藉由覆晶配置法而系藉由黏着性材质4 6装配于第二重布层上。一第五介电层48系被形成来覆盖被动组件40以及第三晶粒38。一第三重布层50系形成于第五介电层48上并连结至第三晶粒、被动组件以及第二重布层32。如图5(h)-(i)所示，一顶层52系形成于第三重布层50之上。由于其它结构与图5(a)-(e)相似，因此省略了相关叙述。图4及图7标明了记忆卡结构的尺寸，如图所示，a：底层基底厚度；b：具有开放凹槽之上基底厚度；c：增层后之第二晶粒厚度；d：FC/SMT后之第三晶粒厚度；e：基底之接触金属厚度~25μm；预形成之基底厚度a+b+c＝300μm。本发明之尺寸较先前技术之尺寸为薄。
图8描述了记忆卡之最终结构。一预形成之塑胶盖54罩住众多晶粒。标志可以标于上盖之上，锡球罩幕(solder mask)则形成于封装结构之下藉以露出端点垫56。
较佳的情况下，基底2之材料系为有机基底例如FR5、BT、FR4、具有已定义凹槽(defined cavity)之印刷电路板(PCB)或具有预蚀刻电路(pre-etching circuit)之Alloy42。具有高玻璃化转变温度(glass transition temperature，Tg)之有机基底系为环氧化物型(epoxy type)FR5或BT(Bismaleimide triazine)型基底。Alloy42系由镍(42％)以及铁(58％)所组成。也可使用柯华合金(Kovar)，其成份为镍(29％)、钴(17％)以及铁(54％)。玻璃、陶瓷、硅亦可做为基底。凹槽4之厚度可以比晶粒10稍微厚一点。而深度也可以更深一点。
基底可为圆形(round type)，例如晶圆型(wafer type)，且其直径(diameter)可为200、300mm或更高。也可以采用矩形(rectangular type)，例如面板型(panel form)。在本发明之一实施例中，本发明之介电层在较佳情况下系以硅介电(siliconedielectric)为主之弹性材质，其包含硅氧烷聚合物(SINR)、硅氧化物、硅氮化物或其合成物。在另一实施例中，介电层系由包含苯环丁烯(BCB)、环氧化物(epoxy)、聚酰亚胺(PI)或树脂。在较佳的情况下，为了制程的简便，其将采用感光层。
在本发明之一实施例中，上述弹性介电层系为一种热膨胀系数(CTE)大于100(ppm/℃)、延伸速率(elongation rate)约40％(较佳的为30％至50％)及硬度(hardness)介于塑胶与橡胶间之材质。弹性介电层18之厚度系依照温度循环试验(temperaturecycling test)期间重布层/介电层界面中所累积之应力(stress)而决定。
在本发明之一实施例中，重布层之材质包含钛/铜/金合金(Ti/Cu/Au alloy)或钛/铜/镍/金合金(Ti/Cu/Ni/Au alloy)；重布层之厚度系介于2μm及15μm之间。钛/铜合金(Ti/Cu alloy)系利用溅镀(sputtering)技术所形成，例如晶种金属层(seedmetal layers)，而铜/金(Cu/Au)或铜/镍/金合金(Cu/Ni/Aualloy)系由电镀(electroplating)技术所形成，利用电镀制程形成重布层可使重布层具有足够之厚度以容忍温度循环期间之热膨胀系数不相符(mismatching)。金属垫可为铝或铜或其组合。
如图2(a)-(g)所示，重布层系由晶粒扩散，并且往下与布线6连接。连接布线系经由通孔8穿过基底2。因此可缩减晶粒封装之厚度。本发明之封装将较先前技术为薄。再者，基底系于封装前预先形成。凹槽4以及布线6也系预先形成的。因此，生产率(throughput)可较以往更为增进。本发明揭露一种不需在重布层上堆栈增层(built-up layers)之扩散式晶圆级封装(WLP)技术。
本发明之优点详述如下：
超薄封装及小尺寸(small form factor)：封装之厚度系约450μm至600μm，而封装尺寸(form factor)可以只较芯片尺寸稍微大一点。其可轻易控制包含塑胶盖之完成品之总厚度。晶粒之厚度可控制在约50μm至100μm，并可藉由在封装内堆栈晶粒而达成较高密度之内存。
较可靠的产品：芯片系完整包装于封装内。至少100μm厚之环氧化物材质形成于芯片的两面。芯片系配置于凹槽中，而弹性材质则充填于芯片周围及凹槽壁面之中，用以吸收芯片及基底(FR5之热膨胀系数约为17至20)之间热膨胀系数不相符所产生之机械应力(mechanical stress)。再者，介电层系采用弹性材质故可以吸收温度循环期间之机械应力。芯片可以堆栈在第一芯片上，解决热膨胀系数不相符的问题。
简易制程以及低成本方案：本发明利用具有晶粒容纳凹槽之基底(FR5)以及其中所形成之电路。块板(piece panel)或批次式(batch type)之「封装」制造系采用增层(build-up layers)步骤。晶粒系藉由板面连结(panel bonding)步骤装配以提供较高的准确性。封装之分割系采用晶粒切割步骤(dicing saw process)来使「封装」分离。并采用一预形成之塑胶盖以完成最终产品。本发明可根据板面层级(panel level)来测试FGS产品以降低测试成本。
本发明以较佳实施例说明如上，然其并非用以限定本发明所主张之专利权利范围。其专利保护范围当视后附之申请专利范围及其等同领域而定。凡熟悉此领域之技艺者，在不脱离本专利精神或范围内，所作之更动或润饰，均属于本发明所揭示精神下所完成之等效改变或设计，且应包含在下述之申请专利范围内。

Claims (10)

1.一种记忆卡结构，其特征在于：所述记忆卡结构包含：
一基底具有一晶粒容纳凹槽位于该基底之上表面、一通孔结构及一形成于该基底之布线；
一第一晶粒配置于该晶粒容纳凹槽之内；
一第一介电层形成于该第一晶粒与该基底之上；
一第一重布层形成于该第一介电层之上，其中该第一重布层系耦合至该第一晶粒与该布线；
一第二介电层形成于该第一重布层；
一第二晶粒配置于该第二介电层；
一第三介电层形成于该第二介电层与该第二晶粒之上；
一第二重布层形成于该第三介电层之上，其中该第二重布层系耦合至该第二晶粒与该第一重布层；
一第四介电层形成于该第二重布层之上；
一第三晶粒形成于该第四介电层之上并耦合至该第二重布层；
一第五介电层形成于该第三晶粒之周围；及
一塑胶盖罩住该第一、第二及第三晶粒。
2.根据权利要求1所述的记忆卡结构，其特征在于：更包含形成于该第四介电层之被动组件。
3.根据权利要求1所述的记忆卡结构，其特征在于：其中该第三晶粒系由覆晶配置法所形成。
4.根据权利要求1所述的记忆卡结构，其特征在于：其中该第三晶粒系附属于该第四介电层之上，而一第三重布层系形成于该第五介电层之上并耦合至该第二重布层。
5.根据权利要求1所述的记忆卡结构，其特征在于：其中该第一、第二、第三、第四及第五介电层中有一层包含一弹性介电层。
6.根据权利要求1所述的记忆卡结构，其特征在于：其中该第一、第二、第三、第四及第五介电层中有一层包含一以硅介电为主的材质、苯环丁烯(BCB)或聚酰亚胺(PI)。
7.根据权利要求6所述的记忆卡结构，其特征在于：其中该以硅介电为主的材质包含硅氧烷聚合物(SINR)、硅氧化物、硅氮化物或其合成物。
8.根据权利要求1所述的记忆卡结构，其特征在于：其中该第一、第二、第三、第四及第五介电层中有一层包含一感光层。
9.根据权利要求1所述的记忆卡结构，其特征在于：其中该第一及第二晶粒扩散出该第一及第二重布层。
10.一种形成半导体装置封装之方法，包含：
提供一基底具有一晶粒容纳凹槽位于该基底之上表面及一通孔结构，其中一传导布线形成于该基底之上或之中；
提供一第一晶粒配置于该晶粒容纳凹槽之内；
形成一第一介电层于该第一晶粒与该基底之上；
形成一第一重布层于该第一介电层之上，其中该第一重布层系耦合至该第一晶粒与该布线；
形成一第二介电层于该第一重布层；
形成一第二晶粒配置于该第二介电层；
形成一第三介电层于该第二介电层与该第二晶粒之上；
形成一第二重布层于该第三介电层之上，其中该第二重布层系耦合至该第二晶粒与该第一重布层；
形成一第四介电层于该第二重布层之上；
提供一第三晶粒于该第四介电层之上并耦合至该第二重布层；
形成一第五介电层于该第三晶粒之周围；及
提供一塑胶盖罩住该第一、第二及第三晶粒。
CNA2008100007931A 2007-01-18 2008-01-17 记忆卡的结构与其方法 Pending CN101231709A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/624,629 2007-01-18
US11/624,629 US20080174008A1 (en) 2007-01-18 2007-01-18 Structure of Memory Card and the Method of the Same

Publications (1)

Publication Number Publication Date
CN101231709A true CN101231709A (zh) 2008-07-30

Family

ID=39640450

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2008100007931A Pending CN101231709A (zh) 2007-01-18 2008-01-17 记忆卡的结构与其方法

Country Status (3)

Country Link
US (1) US20080174008A1 (zh)
CN (1) CN101231709A (zh)
TW (1) TW200834877A (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101719484B (zh) * 2008-10-09 2012-03-14 台湾积体电路制造股份有限公司 具有再分布线的tsv的背连接
CN103545288A (zh) * 2012-07-13 2014-01-29 英特尔移动通信有限责任公司 堆叠的扇出半导体芯片
CN103681606A (zh) * 2012-08-29 2014-03-26 台湾积体电路制造股份有限公司 三维（3d）扇出封装机制
CN104392937A (zh) * 2013-06-28 2015-03-04 英特尔公司 增加bbul封装中的i/o密度和降低层数的方法
CN105280615A (zh) * 2014-06-11 2016-01-27 旺宏电子股份有限公司 一种多芯片封装结构以及制备此多芯片封装的方法
CN106531644A (zh) * 2016-12-09 2017-03-22 华进半导体封装先导技术研发中心有限公司 一种芯片的封装工艺和封装结构
CN106783748A (zh) * 2016-12-09 2017-05-31 华进半导体封装先导技术研发中心有限公司 一种芯片的封装工艺和封装结构

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100836663B1 (ko) * 2006-02-16 2008-06-10 삼성전기주식회사 캐비티가 형성된 패키지 온 패키지 및 그 제조 방법
TW200743035A (en) * 2006-05-09 2007-11-16 Siliconware Precision Industries Co Ltd Circuit card module and method for fabricating the same
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
US20090230554A1 (en) * 2008-03-13 2009-09-17 Broadcom Corporation Wafer-level redistribution packaging with die-containing openings
TWI453877B (zh) * 2008-11-07 2014-09-21 Advanced Semiconductor Eng 內埋晶片封裝的結構及製程
US8114708B2 (en) * 2008-09-30 2012-02-14 General Electric Company System and method for pre-patterned embedded chip build-up
US9875911B2 (en) * 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
US8143097B2 (en) * 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8320134B2 (en) 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
US8618654B2 (en) 2010-07-20 2013-12-31 Marvell World Trade Ltd. Structures embedded within core material and methods of manufacturing thereof
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
TWI426587B (zh) * 2010-08-12 2014-02-11 矽品精密工業股份有限公司 晶片尺寸封裝件及其製法
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8487426B2 (en) 2011-03-15 2013-07-16 Advanced Semiconductor Engineering, Inc. Semiconductor package with embedded die and manufacturing methods thereof
US8546900B2 (en) * 2011-06-09 2013-10-01 Optiz, Inc. 3D integration microelectronic assembly for integrated circuit devices
US20130040423A1 (en) 2011-08-10 2013-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Multi-Chip Wafer Level Packaging
US8754514B2 (en) * 2011-08-10 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip wafer level package
US9620580B2 (en) * 2013-10-25 2017-04-11 Mediatek Inc. Semiconductor structure
US9527723B2 (en) 2014-03-13 2016-12-27 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming microelectromechanical systems (MEMS) package
US9601463B2 (en) * 2014-04-17 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) and the methods of making the same
US9978729B2 (en) * 2015-03-06 2018-05-22 Mediatek Inc. Semiconductor package assembly
KR102549402B1 (ko) 2016-08-04 2023-06-28 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US10672741B2 (en) * 2016-08-18 2020-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
WO2018182595A1 (en) 2017-03-29 2018-10-04 Intel Corporation Embedded die microelectronic device with molded component
WO2019066945A1 (en) * 2017-09-29 2019-04-04 Intel IP Corporation INTEGRATION AND ACCESS TO PASSIVE COMPONENTS IN WAFER-LEVEL BOXES
KR102491103B1 (ko) 2018-02-06 2023-01-20 삼성전자주식회사 반도체 패키지 및 그 제조방법
CN108831876B (zh) * 2018-08-10 2024-03-08 浙江熔城半导体有限公司 滤波器芯片内嵌且具有孔洞的封装结构及其制作方法
KR102653213B1 (ko) 2019-05-13 2024-04-01 삼성전기주식회사 반도체 패키지
US11088125B2 (en) 2019-09-17 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. IPD modules with flexible connection scheme in packaging
US20230282614A1 (en) * 2022-03-01 2023-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods of forming the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101719484B (zh) * 2008-10-09 2012-03-14 台湾积体电路制造股份有限公司 具有再分布线的tsv的背连接
CN103545288A (zh) * 2012-07-13 2014-01-29 英特尔移动通信有限责任公司 堆叠的扇出半导体芯片
CN103681606A (zh) * 2012-08-29 2014-03-26 台湾积体电路制造股份有限公司 三维（3d）扇出封装机制
CN104392937A (zh) * 2013-06-28 2015-03-04 英特尔公司 增加bbul封装中的i/o密度和降低层数的方法
CN105280615A (zh) * 2014-06-11 2016-01-27 旺宏电子股份有限公司 一种多芯片封装结构以及制备此多芯片封装的方法
CN106531644A (zh) * 2016-12-09 2017-03-22 华进半导体封装先导技术研发中心有限公司 一种芯片的封装工艺和封装结构
CN106783748A (zh) * 2016-12-09 2017-05-31 华进半导体封装先导技术研发中心有限公司 一种芯片的封装工艺和封装结构

Also Published As

Publication number Publication date
TW200834877A (en) 2008-08-16
US20080174008A1 (en) 2008-07-24

Similar Documents

Publication Publication Date Title
CN101231709A (zh) 记忆卡的结构与其方法
CN109979924B (zh) 插入基底和半导体封装件
US10008533B2 (en) Semiconductor package
US7459729B2 (en) Semiconductor image device package with die receiving through-hole and method of the same
US8232633B2 (en) Image sensor package with dual substrates and the method of the same
US6593220B1 (en) Elastomer plating mask sealed wafer level package method
US6710446B2 (en) Semiconductor device comprising stress relaxation layers and method for manufacturing the same
TWI533412B (zh) 半導體元件封裝結構及其形成方法
KR101387706B1 (ko) 반도체 칩 패키지, 그 제조 방법 및 이를 포함하는 전자소자
KR101918139B1 (ko) 성형된 저 cte 유전체를 갖는 인터포저
US20080083980A1 (en) Cmos image sensor chip scale package with die receiving through-hole and method of the same
KR101209980B1 (ko) 반도체 패키지 및 그 제조 방법
US9754866B2 (en) Reversed build-up substrate for 2.5D
US7208824B2 (en) Land grid array module
TWI358814B (en) Semiconductor device package having multi-chips wi
CN101261984A (zh) 半导体组件封装结构及其方法
US20080211075A1 (en) Image sensor chip scale package having inter-adhesion with gap and method of the same
US20080284047A1 (en) Chip Package with Stiffener Ring
JP2008166824A (ja) マルチチップパッケージおよびその形成方法
US6396145B1 (en) Semiconductor device and method for manufacturing the same technical field
AU738124B2 (en) Semiconductor device and manufacturing method of same
EP3140861A1 (en) SUBSTRATE BLOCK FOR PoP PACKAGE
TW200901396A (en) Semiconductor device package having chips
KR101965127B1 (ko) 반도체 패키지 및 그 제조 방법
KR102674312B1 (ko) 반도체 패키지

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication